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15#include <virglrenderer.h>
16#include "virgl.h"
17
18void
19vg_virgl_update_cursor_data(VuGpu *g, uint32_t resource_id,
20 gpointer data)
21{
22 uint32_t width, height;
23 uint32_t *cursor;
24
25 cursor = virgl_renderer_get_cursor_data(resource_id, &width, &height);
26 g_return_if_fail(cursor != NULL);
27 g_return_if_fail(width == 64);
28 g_return_if_fail(height == 64);
29
30 memcpy(data, cursor, 64 * 64 * sizeof(uint32_t));
31 free(cursor);
32}
33
34static void
35virgl_cmd_context_create(VuGpu *g,
36 struct virtio_gpu_ctrl_command *cmd)
37{
38 struct virtio_gpu_ctx_create cc;
39
40 VUGPU_FILL_CMD(cc);
41
42 virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
43 cc.debug_name);
44}
45
46static void
47virgl_cmd_context_destroy(VuGpu *g,
48 struct virtio_gpu_ctrl_command *cmd)
49{
50 struct virtio_gpu_ctx_destroy cd;
51
52 VUGPU_FILL_CMD(cd);
53
54 virgl_renderer_context_destroy(cd.hdr.ctx_id);
55}
56
57static void
58virgl_cmd_create_resource_2d(VuGpu *g,
59 struct virtio_gpu_ctrl_command *cmd)
60{
61 struct virtio_gpu_resource_create_2d c2d;
62 struct virgl_renderer_resource_create_args args;
63
64 VUGPU_FILL_CMD(c2d);
65
66 args.handle = c2d.resource_id;
67 args.target = 2;
68 args.format = c2d.format;
69 args.bind = (1 << 1);
70 args.width = c2d.width;
71 args.height = c2d.height;
72 args.depth = 1;
73 args.array_size = 1;
74 args.last_level = 0;
75 args.nr_samples = 0;
76 args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
77 virgl_renderer_resource_create(&args, NULL, 0);
78}
79
80static void
81virgl_cmd_create_resource_3d(VuGpu *g,
82 struct virtio_gpu_ctrl_command *cmd)
83{
84 struct virtio_gpu_resource_create_3d c3d;
85 struct virgl_renderer_resource_create_args args;
86
87 VUGPU_FILL_CMD(c3d);
88
89 args.handle = c3d.resource_id;
90 args.target = c3d.target;
91 args.format = c3d.format;
92 args.bind = c3d.bind;
93 args.width = c3d.width;
94 args.height = c3d.height;
95 args.depth = c3d.depth;
96 args.array_size = c3d.array_size;
97 args.last_level = c3d.last_level;
98 args.nr_samples = c3d.nr_samples;
99 args.flags = c3d.flags;
100 virgl_renderer_resource_create(&args, NULL, 0);
101}
102
103static void
104virgl_cmd_resource_unref(VuGpu *g,
105 struct virtio_gpu_ctrl_command *cmd)
106{
107 struct virtio_gpu_resource_unref unref;
108
109 VUGPU_FILL_CMD(unref);
110
111 virgl_renderer_resource_unref(unref.resource_id);
112}
113
114
115#ifndef VIRTIO_GPU_CAPSET_VIRGL2
116#define VIRTIO_GPU_CAPSET_VIRGL2 2
117#endif
118
119static void
120virgl_cmd_get_capset_info(VuGpu *g,
121 struct virtio_gpu_ctrl_command *cmd)
122{
123 struct virtio_gpu_get_capset_info info;
124 struct virtio_gpu_resp_capset_info resp;
125
126 VUGPU_FILL_CMD(info);
127
128 if (info.capset_index == 0) {
129 resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
130 virgl_renderer_get_cap_set(resp.capset_id,
131 &resp.capset_max_version,
132 &resp.capset_max_size);
133 } else if (info.capset_index == 1) {
134 resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL2;
135 virgl_renderer_get_cap_set(resp.capset_id,
136 &resp.capset_max_version,
137 &resp.capset_max_size);
138 } else {
139 resp.capset_max_version = 0;
140 resp.capset_max_size = 0;
141 }
142 resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
143 vg_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
144}
145
146uint32_t
147vg_virgl_get_num_capsets(void)
148{
149 uint32_t capset2_max_ver, capset2_max_size;
150 virgl_renderer_get_cap_set(VIRTIO_GPU_CAPSET_VIRGL2,
151 &capset2_max_ver,
152 &capset2_max_size);
153
154 return capset2_max_ver ? 2 : 1;
155}
156
157static void
158virgl_cmd_get_capset(VuGpu *g,
159 struct virtio_gpu_ctrl_command *cmd)
160{
161 struct virtio_gpu_get_capset gc;
162 struct virtio_gpu_resp_capset *resp;
163 uint32_t max_ver, max_size;
164
165 VUGPU_FILL_CMD(gc);
166
167 virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
168 &max_size);
169 resp = g_malloc0(sizeof(*resp) + max_size);
170
171 resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
172 virgl_renderer_fill_caps(gc.capset_id,
173 gc.capset_version,
174 (void *)resp->capset_data);
175 vg_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
176 g_free(resp);
177}
178
179static void
180virgl_cmd_submit_3d(VuGpu *g,
181 struct virtio_gpu_ctrl_command *cmd)
182{
183 struct virtio_gpu_cmd_submit cs;
184 void *buf;
185 size_t s;
186
187 VUGPU_FILL_CMD(cs);
188
189 buf = g_malloc(cs.size);
190 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
191 sizeof(cs), buf, cs.size);
192 if (s != cs.size) {
193 g_critical("%s: size mismatch (%zd/%d)", __func__, s, cs.size);
194 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
195 goto out;
196 }
197
198 virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);
199
200out:
201 g_free(buf);
202}
203
204static void
205virgl_cmd_transfer_to_host_2d(VuGpu *g,
206 struct virtio_gpu_ctrl_command *cmd)
207{
208 struct virtio_gpu_transfer_to_host_2d t2d;
209 struct virtio_gpu_box box;
210
211 VUGPU_FILL_CMD(t2d);
212
213 box.x = t2d.r.x;
214 box.y = t2d.r.y;
215 box.z = 0;
216 box.w = t2d.r.width;
217 box.h = t2d.r.height;
218 box.d = 1;
219
220 virgl_renderer_transfer_write_iov(t2d.resource_id,
221 0,
222 0,
223 0,
224 0,
225 (struct virgl_box *)&box,
226 t2d.offset, NULL, 0);
227}
228
229static void
230virgl_cmd_transfer_to_host_3d(VuGpu *g,
231 struct virtio_gpu_ctrl_command *cmd)
232{
233 struct virtio_gpu_transfer_host_3d t3d;
234
235 VUGPU_FILL_CMD(t3d);
236
237 virgl_renderer_transfer_write_iov(t3d.resource_id,
238 t3d.hdr.ctx_id,
239 t3d.level,
240 t3d.stride,
241 t3d.layer_stride,
242 (struct virgl_box *)&t3d.box,
243 t3d.offset, NULL, 0);
244}
245
246static void
247virgl_cmd_transfer_from_host_3d(VuGpu *g,
248 struct virtio_gpu_ctrl_command *cmd)
249{
250 struct virtio_gpu_transfer_host_3d tf3d;
251
252 VUGPU_FILL_CMD(tf3d);
253
254 virgl_renderer_transfer_read_iov(tf3d.resource_id,
255 tf3d.hdr.ctx_id,
256 tf3d.level,
257 tf3d.stride,
258 tf3d.layer_stride,
259 (struct virgl_box *)&tf3d.box,
260 tf3d.offset, NULL, 0);
261}
262
263static void
264virgl_resource_attach_backing(VuGpu *g,
265 struct virtio_gpu_ctrl_command *cmd)
266{
267 struct virtio_gpu_resource_attach_backing att_rb;
268 struct iovec *res_iovs;
269 int ret;
270
271 VUGPU_FILL_CMD(att_rb);
272
273 ret = vg_create_mapping_iov(g, &att_rb, cmd, &res_iovs);
274 if (ret != 0) {
275 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
276 return;
277 }
278
279 virgl_renderer_resource_attach_iov(att_rb.resource_id,
280 res_iovs, att_rb.nr_entries);
281}
282
283static void
284virgl_resource_detach_backing(VuGpu *g,
285 struct virtio_gpu_ctrl_command *cmd)
286{
287 struct virtio_gpu_resource_detach_backing detach_rb;
288 struct iovec *res_iovs = NULL;
289 int num_iovs = 0;
290
291 VUGPU_FILL_CMD(detach_rb);
292
293 virgl_renderer_resource_detach_iov(detach_rb.resource_id,
294 &res_iovs,
295 &num_iovs);
296 if (res_iovs == NULL || num_iovs == 0) {
297 return;
298 }
299 g_free(res_iovs);
300}
301
302static void
303virgl_cmd_set_scanout(VuGpu *g,
304 struct virtio_gpu_ctrl_command *cmd)
305{
306 struct virtio_gpu_set_scanout ss;
307 struct virgl_renderer_resource_info info;
308 int ret;
309
310 VUGPU_FILL_CMD(ss);
311
312 if (ss.scanout_id >= VIRTIO_GPU_MAX_SCANOUTS) {
313 g_critical("%s: illegal scanout id specified %d",
314 __func__, ss.scanout_id);
315 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
316 return;
317 }
318
319 memset(&info, 0, sizeof(info));
320
321 if (ss.resource_id && ss.r.width && ss.r.height) {
322 ret = virgl_renderer_resource_get_info(ss.resource_id, &info);
323 if (ret == -1) {
324 g_critical("%s: illegal resource specified %d\n",
325 __func__, ss.resource_id);
326 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
327 return;
328 }
329
330 int fd = -1;
331 if (virgl_renderer_get_fd_for_texture(info.tex_id, &fd) < 0) {
332 g_critical("%s: failed to get fd for texture\n", __func__);
333 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
334 return;
335 }
336 assert(fd >= 0);
337 VhostUserGpuMsg msg = {
338 .request = VHOST_USER_GPU_DMABUF_SCANOUT,
339 .size = sizeof(VhostUserGpuDMABUFScanout),
340 .payload.dmabuf_scanout.scanout_id = ss.scanout_id,
341 .payload.dmabuf_scanout.x = ss.r.x,
342 .payload.dmabuf_scanout.y = ss.r.y,
343 .payload.dmabuf_scanout.width = ss.r.width,
344 .payload.dmabuf_scanout.height = ss.r.height,
345 .payload.dmabuf_scanout.fd_width = info.width,
346 .payload.dmabuf_scanout.fd_height = info.height,
347 .payload.dmabuf_scanout.fd_stride = info.stride,
348 .payload.dmabuf_scanout.fd_flags = info.flags,
349 .payload.dmabuf_scanout.fd_drm_fourcc = info.drm_fourcc
350 };
351 vg_send_msg(g, &msg, fd);
352 close(fd);
353 } else {
354 VhostUserGpuMsg msg = {
355 .request = VHOST_USER_GPU_DMABUF_SCANOUT,
356 .size = sizeof(VhostUserGpuDMABUFScanout),
357 .payload.dmabuf_scanout.scanout_id = ss.scanout_id,
358 };
359 g_debug("disable scanout");
360 vg_send_msg(g, &msg, -1);
361 }
362 g->scanout[ss.scanout_id].resource_id = ss.resource_id;
363}
364
365static void
366virgl_cmd_resource_flush(VuGpu *g,
367 struct virtio_gpu_ctrl_command *cmd)
368{
369 struct virtio_gpu_resource_flush rf;
370 int i;
371
372 VUGPU_FILL_CMD(rf);
373
374 if (!rf.resource_id) {
375 g_debug("bad resource id for flush..?");
376 return;
377 }
378 for (i = 0; i < VIRTIO_GPU_MAX_SCANOUTS; i++) {
379 if (g->scanout[i].resource_id != rf.resource_id) {
380 continue;
381 }
382 VhostUserGpuMsg msg = {
383 .request = VHOST_USER_GPU_DMABUF_UPDATE,
384 .size = sizeof(VhostUserGpuUpdate),
385 .payload.update.scanout_id = i,
386 .payload.update.x = rf.r.x,
387 .payload.update.y = rf.r.y,
388 .payload.update.width = rf.r.width,
389 .payload.update.height = rf.r.height
390 };
391 vg_send_msg(g, &msg, -1);
392 vg_wait_ok(g);
393 }
394}
395
396static void
397virgl_cmd_ctx_attach_resource(VuGpu *g,
398 struct virtio_gpu_ctrl_command *cmd)
399{
400 struct virtio_gpu_ctx_resource att_res;
401
402 VUGPU_FILL_CMD(att_res);
403
404 virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
405}
406
407static void
408virgl_cmd_ctx_detach_resource(VuGpu *g,
409 struct virtio_gpu_ctrl_command *cmd)
410{
411 struct virtio_gpu_ctx_resource det_res;
412
413 VUGPU_FILL_CMD(det_res);
414
415 virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
416}
417
418void vg_virgl_process_cmd(VuGpu *g, struct virtio_gpu_ctrl_command *cmd)
419{
420 virgl_renderer_force_ctx_0();
421 switch (cmd->cmd_hdr.type) {
422 case VIRTIO_GPU_CMD_CTX_CREATE:
423 virgl_cmd_context_create(g, cmd);
424 break;
425 case VIRTIO_GPU_CMD_CTX_DESTROY:
426 virgl_cmd_context_destroy(g, cmd);
427 break;
428 case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
429 virgl_cmd_create_resource_2d(g, cmd);
430 break;
431 case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
432 virgl_cmd_create_resource_3d(g, cmd);
433 break;
434 case VIRTIO_GPU_CMD_SUBMIT_3D:
435 virgl_cmd_submit_3d(g, cmd);
436 break;
437 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
438 virgl_cmd_transfer_to_host_2d(g, cmd);
439 break;
440 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
441 virgl_cmd_transfer_to_host_3d(g, cmd);
442 break;
443 case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
444 virgl_cmd_transfer_from_host_3d(g, cmd);
445 break;
446 case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
447 virgl_resource_attach_backing(g, cmd);
448 break;
449 case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
450 virgl_resource_detach_backing(g, cmd);
451 break;
452 case VIRTIO_GPU_CMD_SET_SCANOUT:
453 virgl_cmd_set_scanout(g, cmd);
454 break;
455 case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
456 virgl_cmd_resource_flush(g, cmd);
457 break;
458 case VIRTIO_GPU_CMD_RESOURCE_UNREF:
459 virgl_cmd_resource_unref(g, cmd);
460 break;
461 case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
462
463 virgl_cmd_ctx_attach_resource(g, cmd);
464 break;
465 case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
466
467 virgl_cmd_ctx_detach_resource(g, cmd);
468 break;
469 case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
470 virgl_cmd_get_capset_info(g, cmd);
471 break;
472 case VIRTIO_GPU_CMD_GET_CAPSET:
473 virgl_cmd_get_capset(g, cmd);
474 break;
475 case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
476 vg_get_display_info(g, cmd);
477 break;
478 default:
479 g_debug("TODO handle ctrl %x\n", cmd->cmd_hdr.type);
480 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
481 break;
482 }
483
484 if (cmd->finished) {
485 return;
486 }
487
488 if (cmd->error) {
489 g_warning("%s: ctrl 0x%x, error 0x%x\n", __func__,
490 cmd->cmd_hdr.type, cmd->error);
491 vg_ctrl_response_nodata(g, cmd, cmd->error);
492 return;
493 }
494
495 if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
496 vg_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
497 return;
498 }
499
500 g_debug("Creating fence id:%" PRId64 " type:%d",
501 cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
502 virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
503}
504
505static void
506virgl_write_fence(void *opaque, uint32_t fence)
507{
508 VuGpu *g = opaque;
509 struct virtio_gpu_ctrl_command *cmd, *tmp;
510
511 QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
512
513
514
515
516 if (cmd->cmd_hdr.fence_id > fence) {
517 continue;
518 }
519 g_debug("FENCE %" PRIu64, cmd->cmd_hdr.fence_id);
520 vg_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
521 QTAILQ_REMOVE(&g->fenceq, cmd, next);
522 g_free(cmd);
523 g->inflight--;
524 }
525}
526
527#if defined(VIRGL_RENDERER_CALLBACKS_VERSION) && \
528 VIRGL_RENDERER_CALLBACKS_VERSION >= 2
529static int
530virgl_get_drm_fd(void *opaque)
531{
532 VuGpu *g = opaque;
533
534 return g->drm_rnode_fd;
535}
536#endif
537
538static struct virgl_renderer_callbacks virgl_cbs = {
539#if defined(VIRGL_RENDERER_CALLBACKS_VERSION) && \
540 VIRGL_RENDERER_CALLBACKS_VERSION >= 2
541 .get_drm_fd = virgl_get_drm_fd,
542 .version = 2,
543#else
544 .version = 1,
545#endif
546 .write_fence = virgl_write_fence,
547};
548
549static void
550vg_virgl_poll(VuDev *dev, int condition, void *data)
551{
552 virgl_renderer_poll();
553}
554
555bool
556vg_virgl_init(VuGpu *g)
557{
558 int ret;
559
560 if (g->drm_rnode_fd && virgl_cbs.version == 1) {
561 g_warning("virgl will use the default rendernode");
562 }
563
564 ret = virgl_renderer_init(g,
565 VIRGL_RENDERER_USE_EGL |
566 VIRGL_RENDERER_THREAD_SYNC,
567 &virgl_cbs);
568 if (ret != 0) {
569 return false;
570 }
571
572 ret = virgl_renderer_get_poll_fd();
573 if (ret != -1) {
574 g->renderer_source =
575 vug_source_new(&g->dev, ret, G_IO_IN, vg_virgl_poll, g);
576 }
577
578 return true;
579}
580
