qemu/hw/char/lm32_uart.c
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   1/*
   2 *  QEMU model of the LatticeMico32 UART block.
   3 *
   4 *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 *
  19 *
  20 * Specification available at:
  21 *   http://www.latticesemi.com/documents/mico32uart.pdf
  22 */
  23
  24
  25#include "qemu/osdep.h"
  26#include "hw/hw.h"
  27#include "hw/sysbus.h"
  28#include "trace.h"
  29#include "chardev/char-fe.h"
  30#include "qemu/error-report.h"
  31#include "qemu/module.h"
  32
  33enum {
  34    R_RXTX = 0,
  35    R_IER,
  36    R_IIR,
  37    R_LCR,
  38    R_MCR,
  39    R_LSR,
  40    R_MSR,
  41    R_DIV,
  42    R_MAX
  43};
  44
  45enum {
  46    IER_RBRI = (1<<0),
  47    IER_THRI = (1<<1),
  48    IER_RLSI = (1<<2),
  49    IER_MSI  = (1<<3),
  50};
  51
  52enum {
  53    IIR_STAT = (1<<0),
  54    IIR_ID0  = (1<<1),
  55    IIR_ID1  = (1<<2),
  56};
  57
  58enum {
  59    LCR_WLS0 = (1<<0),
  60    LCR_WLS1 = (1<<1),
  61    LCR_STB  = (1<<2),
  62    LCR_PEN  = (1<<3),
  63    LCR_EPS  = (1<<4),
  64    LCR_SP   = (1<<5),
  65    LCR_SB   = (1<<6),
  66};
  67
  68enum {
  69    MCR_DTR  = (1<<0),
  70    MCR_RTS  = (1<<1),
  71};
  72
  73enum {
  74    LSR_DR   = (1<<0),
  75    LSR_OE   = (1<<1),
  76    LSR_PE   = (1<<2),
  77    LSR_FE   = (1<<3),
  78    LSR_BI   = (1<<4),
  79    LSR_THRE = (1<<5),
  80    LSR_TEMT = (1<<6),
  81};
  82
  83enum {
  84    MSR_DCTS = (1<<0),
  85    MSR_DDSR = (1<<1),
  86    MSR_TERI = (1<<2),
  87    MSR_DDCD = (1<<3),
  88    MSR_CTS  = (1<<4),
  89    MSR_DSR  = (1<<5),
  90    MSR_RI   = (1<<6),
  91    MSR_DCD  = (1<<7),
  92};
  93
  94#define TYPE_LM32_UART "lm32-uart"
  95#define LM32_UART(obj) OBJECT_CHECK(LM32UartState, (obj), TYPE_LM32_UART)
  96
  97struct LM32UartState {
  98    SysBusDevice parent_obj;
  99
 100    MemoryRegion iomem;
 101    CharBackend chr;
 102    qemu_irq irq;
 103
 104    uint32_t regs[R_MAX];
 105};
 106typedef struct LM32UartState LM32UartState;
 107
 108static void uart_update_irq(LM32UartState *s)
 109{
 110    unsigned int irq;
 111
 112    if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
 113            && (s->regs[R_IER] & IER_RLSI)) {
 114        irq = 1;
 115        s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
 116    } else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
 117        irq = 1;
 118        s->regs[R_IIR] = IIR_ID1;
 119    } else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
 120        irq = 1;
 121        s->regs[R_IIR] = IIR_ID0;
 122    } else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
 123        irq = 1;
 124        s->regs[R_IIR] = 0;
 125    } else {
 126        irq = 0;
 127        s->regs[R_IIR] = IIR_STAT;
 128    }
 129
 130    trace_lm32_uart_irq_state(irq);
 131    qemu_set_irq(s->irq, irq);
 132}
 133
 134static uint64_t uart_read(void *opaque, hwaddr addr,
 135                          unsigned size)
 136{
 137    LM32UartState *s = opaque;
 138    uint32_t r = 0;
 139
 140    addr >>= 2;
 141    switch (addr) {
 142    case R_RXTX:
 143        r = s->regs[R_RXTX];
 144        s->regs[R_LSR] &= ~LSR_DR;
 145        uart_update_irq(s);
 146        qemu_chr_fe_accept_input(&s->chr);
 147        break;
 148    case R_IIR:
 149    case R_LSR:
 150    case R_MSR:
 151        r = s->regs[addr];
 152        break;
 153    case R_IER:
 154    case R_LCR:
 155    case R_MCR:
 156    case R_DIV:
 157        error_report("lm32_uart: read access to write only register 0x"
 158                TARGET_FMT_plx, addr << 2);
 159        break;
 160    default:
 161        error_report("lm32_uart: read access to unknown register 0x"
 162                TARGET_FMT_plx, addr << 2);
 163        break;
 164    }
 165
 166    trace_lm32_uart_memory_read(addr << 2, r);
 167    return r;
 168}
 169
 170static void uart_write(void *opaque, hwaddr addr,
 171                       uint64_t value, unsigned size)
 172{
 173    LM32UartState *s = opaque;
 174    unsigned char ch = value;
 175
 176    trace_lm32_uart_memory_write(addr, value);
 177
 178    addr >>= 2;
 179    switch (addr) {
 180    case R_RXTX:
 181        /* XXX this blocks entire thread. Rewrite to use
 182         * qemu_chr_fe_write and background I/O callbacks */
 183        qemu_chr_fe_write_all(&s->chr, &ch, 1);
 184        break;
 185    case R_IER:
 186    case R_LCR:
 187    case R_MCR:
 188    case R_DIV:
 189        s->regs[addr] = value;
 190        break;
 191    case R_IIR:
 192    case R_LSR:
 193    case R_MSR:
 194        error_report("lm32_uart: write access to read only register 0x"
 195                TARGET_FMT_plx, addr << 2);
 196        break;
 197    default:
 198        error_report("lm32_uart: write access to unknown register 0x"
 199                TARGET_FMT_plx, addr << 2);
 200        break;
 201    }
 202    uart_update_irq(s);
 203}
 204
 205static const MemoryRegionOps uart_ops = {
 206    .read = uart_read,
 207    .write = uart_write,
 208    .endianness = DEVICE_NATIVE_ENDIAN,
 209    .valid = {
 210        .min_access_size = 4,
 211        .max_access_size = 4,
 212    },
 213};
 214
 215static void uart_rx(void *opaque, const uint8_t *buf, int size)
 216{
 217    LM32UartState *s = opaque;
 218
 219    if (s->regs[R_LSR] & LSR_DR) {
 220        s->regs[R_LSR] |= LSR_OE;
 221    }
 222
 223    s->regs[R_LSR] |= LSR_DR;
 224    s->regs[R_RXTX] = *buf;
 225
 226    uart_update_irq(s);
 227}
 228
 229static int uart_can_rx(void *opaque)
 230{
 231    LM32UartState *s = opaque;
 232
 233    return !(s->regs[R_LSR] & LSR_DR);
 234}
 235
 236static void uart_event(void *opaque, int event)
 237{
 238}
 239
 240static void uart_reset(DeviceState *d)
 241{
 242    LM32UartState *s = LM32_UART(d);
 243    int i;
 244
 245    for (i = 0; i < R_MAX; i++) {
 246        s->regs[i] = 0;
 247    }
 248
 249    /* defaults */
 250    s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
 251}
 252
 253static void lm32_uart_init(Object *obj)
 254{
 255    LM32UartState *s = LM32_UART(obj);
 256    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 257
 258    sysbus_init_irq(dev, &s->irq);
 259
 260    memory_region_init_io(&s->iomem, obj, &uart_ops, s,
 261                          "uart", R_MAX * 4);
 262    sysbus_init_mmio(dev, &s->iomem);
 263}
 264
 265static void lm32_uart_realize(DeviceState *dev, Error **errp)
 266{
 267    LM32UartState *s = LM32_UART(dev);
 268
 269    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
 270                             uart_event, NULL, s, NULL, true);
 271}
 272
 273static const VMStateDescription vmstate_lm32_uart = {
 274    .name = "lm32-uart",
 275    .version_id = 1,
 276    .minimum_version_id = 1,
 277    .fields = (VMStateField[]) {
 278        VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
 279        VMSTATE_END_OF_LIST()
 280    }
 281};
 282
 283static Property lm32_uart_properties[] = {
 284    DEFINE_PROP_CHR("chardev", LM32UartState, chr),
 285    DEFINE_PROP_END_OF_LIST(),
 286};
 287
 288static void lm32_uart_class_init(ObjectClass *klass, void *data)
 289{
 290    DeviceClass *dc = DEVICE_CLASS(klass);
 291
 292    dc->reset = uart_reset;
 293    dc->vmsd = &vmstate_lm32_uart;
 294    dc->props = lm32_uart_properties;
 295    dc->realize = lm32_uart_realize;
 296}
 297
 298static const TypeInfo lm32_uart_info = {
 299    .name          = TYPE_LM32_UART,
 300    .parent        = TYPE_SYS_BUS_DEVICE,
 301    .instance_size = sizeof(LM32UartState),
 302    .instance_init = lm32_uart_init,
 303    .class_init    = lm32_uart_class_init,
 304};
 305
 306static void lm32_uart_register_types(void)
 307{
 308    type_register_static(&lm32_uart_info);
 309}
 310
 311type_init(lm32_uart_register_types)
 312