1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#include "qemu/osdep.h"
21#include "qemu/units.h"
22#include "hw/hw.h"
23#include "qemu/error-report.h"
24#include "qemu/module.h"
25#include "ui/console.h"
26#include "ui/pixel_ops.h"
27#include "trace.h"
28#include "hw/sysbus.h"
29
30typedef struct G364State {
31
32 uint8_t *vram;
33 uint32_t vram_size;
34 qemu_irq irq;
35 MemoryRegion mem_vram;
36 MemoryRegion mem_ctrl;
37
38 uint8_t color_palette[256][3];
39 uint8_t cursor_palette[3][3];
40 uint16_t cursor[512];
41 uint32_t cursor_position;
42 uint32_t ctla;
43 uint32_t top_of_screen;
44 uint32_t width, height;
45
46 QemuConsole *con;
47 int depth;
48 int blanked;
49} G364State;
50
51#define REG_BOOT 0x000000
52#define REG_DISPLAY 0x000118
53#define REG_VDISPLAY 0x000150
54#define REG_CTLA 0x000300
55#define REG_TOP 0x000400
56#define REG_CURS_PAL 0x000508
57#define REG_CURS_POS 0x000638
58#define REG_CLR_PAL 0x000800
59#define REG_CURS_PAT 0x001000
60#define REG_RESET 0x100000
61
62#define CTLA_FORCE_BLANK 0x00000400
63#define CTLA_NO_CURSOR 0x00800000
64
65#define G364_PAGE_SIZE 4096
66
67static inline int check_dirty(G364State *s, DirtyBitmapSnapshot *snap, ram_addr_t page)
68{
69 return memory_region_snapshot_get_dirty(&s->mem_vram, snap, page, G364_PAGE_SIZE);
70}
71
72static void g364fb_draw_graphic8(G364State *s)
73{
74 DisplaySurface *surface = qemu_console_surface(s->con);
75 DirtyBitmapSnapshot *snap;
76 int i, w;
77 uint8_t *vram;
78 uint8_t *data_display, *dd;
79 ram_addr_t page;
80 int x, y;
81 int xmin, xmax;
82 int ymin, ymax;
83 int xcursor, ycursor;
84 unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
85
86 switch (surface_bits_per_pixel(surface)) {
87 case 8:
88 rgb_to_pixel = rgb_to_pixel8;
89 w = 1;
90 break;
91 case 15:
92 rgb_to_pixel = rgb_to_pixel15;
93 w = 2;
94 break;
95 case 16:
96 rgb_to_pixel = rgb_to_pixel16;
97 w = 2;
98 break;
99 case 32:
100 rgb_to_pixel = rgb_to_pixel32;
101 w = 4;
102 break;
103 default:
104 hw_error("g364: unknown host depth %d",
105 surface_bits_per_pixel(surface));
106 return;
107 }
108
109 page = 0;
110
111 x = y = 0;
112 xmin = s->width;
113 xmax = 0;
114 ymin = s->height;
115 ymax = 0;
116
117 if (!(s->ctla & CTLA_NO_CURSOR)) {
118 xcursor = s->cursor_position >> 12;
119 ycursor = s->cursor_position & 0xfff;
120 } else {
121 xcursor = ycursor = -65;
122 }
123
124 vram = s->vram + s->top_of_screen;
125
126 data_display = dd = surface_data(surface);
127 snap = memory_region_snapshot_and_clear_dirty(&s->mem_vram, 0, s->vram_size,
128 DIRTY_MEMORY_VGA);
129 while (y < s->height) {
130 if (check_dirty(s, snap, page)) {
131 if (y < ymin)
132 ymin = ymax = y;
133 if (x < xmin)
134 xmin = x;
135 for (i = 0; i < G364_PAGE_SIZE; i++) {
136 uint8_t index;
137 unsigned int color;
138 if (unlikely((y >= ycursor && y < ycursor + 64) &&
139 (x >= xcursor && x < xcursor + 64))) {
140
141 int xdiff = x - xcursor;
142 uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
143 int op = (curs >> ((xdiff & 7) * 2)) & 3;
144 if (likely(op == 0)) {
145
146 index = *vram;
147 color = (*rgb_to_pixel)(
148 s->color_palette[index][0],
149 s->color_palette[index][1],
150 s->color_palette[index][2]);
151 } else {
152
153 index = op - 1;
154 color = (*rgb_to_pixel)(
155 s->cursor_palette[index][0],
156 s->cursor_palette[index][1],
157 s->cursor_palette[index][2]);
158 }
159 } else {
160
161 index = *vram;
162 color = (*rgb_to_pixel)(
163 s->color_palette[index][0],
164 s->color_palette[index][1],
165 s->color_palette[index][2]);
166 }
167 memcpy(dd, &color, w);
168 dd += w;
169 x++;
170 vram++;
171 if (x == s->width) {
172 xmax = s->width - 1;
173 y++;
174 if (y == s->height) {
175 ymax = s->height - 1;
176 goto done;
177 }
178 data_display = dd = data_display + surface_stride(surface);
179 xmin = 0;
180 x = 0;
181 }
182 }
183 if (x > xmax)
184 xmax = x;
185 if (y > ymax)
186 ymax = y;
187 } else {
188 int dy;
189 if (xmax || ymax) {
190 dpy_gfx_update(s->con, xmin, ymin,
191 xmax - xmin + 1, ymax - ymin + 1);
192 xmin = s->width;
193 xmax = 0;
194 ymin = s->height;
195 ymax = 0;
196 }
197 x += G364_PAGE_SIZE;
198 dy = x / s->width;
199 x = x % s->width;
200 y += dy;
201 vram += G364_PAGE_SIZE;
202 data_display += dy * surface_stride(surface);
203 dd = data_display + x * w;
204 }
205 page += G364_PAGE_SIZE;
206 }
207
208done:
209 if (xmax || ymax) {
210 dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
211 }
212 g_free(snap);
213}
214
215static void g364fb_draw_blank(G364State *s)
216{
217 DisplaySurface *surface = qemu_console_surface(s->con);
218 int i, w;
219 uint8_t *d;
220
221 if (s->blanked) {
222
223 return;
224 }
225
226 w = s->width * surface_bytes_per_pixel(surface);
227 d = surface_data(surface);
228 for (i = 0; i < s->height; i++) {
229 memset(d, 0, w);
230 d += surface_stride(surface);
231 }
232
233 dpy_gfx_update_full(s->con);
234 s->blanked = 1;
235}
236
237static void g364fb_update_display(void *opaque)
238{
239 G364State *s = opaque;
240 DisplaySurface *surface = qemu_console_surface(s->con);
241
242 qemu_flush_coalesced_mmio_buffer();
243
244 if (s->width == 0 || s->height == 0)
245 return;
246
247 if (s->width != surface_width(surface) ||
248 s->height != surface_height(surface)) {
249 qemu_console_resize(s->con, s->width, s->height);
250 }
251
252 if (s->ctla & CTLA_FORCE_BLANK) {
253 g364fb_draw_blank(s);
254 } else if (s->depth == 8) {
255 g364fb_draw_graphic8(s);
256 } else {
257 error_report("g364: unknown guest depth %d", s->depth);
258 }
259
260 qemu_irq_raise(s->irq);
261}
262
263static inline void g364fb_invalidate_display(void *opaque)
264{
265 G364State *s = opaque;
266
267 s->blanked = 0;
268 memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
269}
270
271static void g364fb_reset(G364State *s)
272{
273 qemu_irq_lower(s->irq);
274
275 memset(s->color_palette, 0, sizeof(s->color_palette));
276 memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
277 memset(s->cursor, 0, sizeof(s->cursor));
278 s->cursor_position = 0;
279 s->ctla = 0;
280 s->top_of_screen = 0;
281 s->width = s->height = 0;
282 memset(s->vram, 0, s->vram_size);
283 g364fb_invalidate_display(s);
284}
285
286
287static uint64_t g364fb_ctrl_read(void *opaque,
288 hwaddr addr,
289 unsigned int size)
290{
291 G364State *s = opaque;
292 uint32_t val;
293
294 if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
295
296 int idx = (addr - REG_CURS_PAT) >> 3;
297 val = s->cursor[idx];
298 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
299
300 int idx = (addr - REG_CURS_PAL) >> 3;
301 val = ((uint32_t)s->cursor_palette[idx][0] << 16);
302 val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
303 val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
304 } else {
305 switch (addr) {
306 case REG_DISPLAY:
307 val = s->width / 4;
308 break;
309 case REG_VDISPLAY:
310 val = s->height * 2;
311 break;
312 case REG_CTLA:
313 val = s->ctla;
314 break;
315 default:
316 {
317 error_report("g364: invalid read at [" TARGET_FMT_plx "]",
318 addr);
319 val = 0;
320 break;
321 }
322 }
323 }
324
325 trace_g364fb_read(addr, val);
326
327 return val;
328}
329
330static void g364fb_update_depth(G364State *s)
331{
332 static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
333 s->depth = depths[(s->ctla & 0x00700000) >> 20];
334}
335
336static void g364_invalidate_cursor_position(G364State *s)
337{
338 DisplaySurface *surface = qemu_console_surface(s->con);
339 int ymin, ymax, start, end;
340
341
342 ymin = s->cursor_position & 0xfff;
343 ymax = MIN(s->height, ymin + 64);
344 start = ymin * surface_stride(surface);
345 end = (ymax + 1) * surface_stride(surface);
346
347 memory_region_set_dirty(&s->mem_vram, start, end - start);
348}
349
350static void g364fb_ctrl_write(void *opaque,
351 hwaddr addr,
352 uint64_t val,
353 unsigned int size)
354{
355 G364State *s = opaque;
356
357 trace_g364fb_write(addr, val);
358
359 if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
360
361 int idx = (addr - REG_CLR_PAL) >> 3;
362 s->color_palette[idx][0] = (val >> 16) & 0xff;
363 s->color_palette[idx][1] = (val >> 8) & 0xff;
364 s->color_palette[idx][2] = val & 0xff;
365 g364fb_invalidate_display(s);
366 } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
367
368 int idx = (addr - REG_CURS_PAT) >> 3;
369 s->cursor[idx] = val;
370 g364fb_invalidate_display(s);
371 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
372
373 int idx = (addr - REG_CURS_PAL) >> 3;
374 s->cursor_palette[idx][0] = (val >> 16) & 0xff;
375 s->cursor_palette[idx][1] = (val >> 8) & 0xff;
376 s->cursor_palette[idx][2] = val & 0xff;
377 g364fb_invalidate_display(s);
378 } else {
379 switch (addr) {
380 case REG_BOOT:
381 case 0x00108:
382 case 0x00110:
383 case 0x00120:
384 case 0x00128:
385 case 0x00130:
386 case 0x00138:
387 case 0x00140:
388 case 0x00148:
389 case 0x00158:
390 case 0x00160:
391 case 0x00168:
392 case 0x00170:
393 case 0x00200:
394
395 break;
396 case REG_TOP:
397 s->top_of_screen = val;
398 g364fb_invalidate_display(s);
399 break;
400 case REG_DISPLAY:
401 s->width = val * 4;
402 break;
403 case REG_VDISPLAY:
404 s->height = val / 2;
405 break;
406 case REG_CTLA:
407 s->ctla = val;
408 g364fb_update_depth(s);
409 g364fb_invalidate_display(s);
410 break;
411 case REG_CURS_POS:
412 g364_invalidate_cursor_position(s);
413 s->cursor_position = val;
414 g364_invalidate_cursor_position(s);
415 break;
416 case REG_RESET:
417 g364fb_reset(s);
418 break;
419 default:
420 error_report("g364: invalid write of 0x%" PRIx64
421 " at [" TARGET_FMT_plx "]", val, addr);
422 break;
423 }
424 }
425 qemu_irq_lower(s->irq);
426}
427
428static const MemoryRegionOps g364fb_ctrl_ops = {
429 .read = g364fb_ctrl_read,
430 .write = g364fb_ctrl_write,
431 .endianness = DEVICE_LITTLE_ENDIAN,
432 .impl.min_access_size = 4,
433 .impl.max_access_size = 4,
434};
435
436static int g364fb_post_load(void *opaque, int version_id)
437{
438 G364State *s = opaque;
439
440
441 g364fb_update_depth(s);
442 g364fb_invalidate_display(s);
443
444 return 0;
445}
446
447static const VMStateDescription vmstate_g364fb = {
448 .name = "g364fb",
449 .version_id = 1,
450 .minimum_version_id = 1,
451 .post_load = g364fb_post_load,
452 .fields = (VMStateField[]) {
453 VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, vram_size),
454 VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
455 VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
456 VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
457 VMSTATE_UINT32(cursor_position, G364State),
458 VMSTATE_UINT32(ctla, G364State),
459 VMSTATE_UINT32(top_of_screen, G364State),
460 VMSTATE_UINT32(width, G364State),
461 VMSTATE_UINT32(height, G364State),
462 VMSTATE_END_OF_LIST()
463 }
464};
465
466static const GraphicHwOps g364fb_ops = {
467 .invalidate = g364fb_invalidate_display,
468 .gfx_update = g364fb_update_display,
469};
470
471static void g364fb_init(DeviceState *dev, G364State *s)
472{
473 s->vram = g_malloc0(s->vram_size);
474
475 s->con = graphic_console_init(dev, 0, &g364fb_ops, s);
476
477 memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
478 memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram",
479 s->vram_size, s->vram);
480 vmstate_register_ram(&s->mem_vram, dev);
481 memory_region_set_log(&s->mem_vram, true, DIRTY_MEMORY_VGA);
482}
483
484#define TYPE_G364 "sysbus-g364"
485#define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364)
486
487typedef struct {
488 SysBusDevice parent_obj;
489
490 G364State g364;
491} G364SysBusState;
492
493static void g364fb_sysbus_realize(DeviceState *dev, Error **errp)
494{
495 G364SysBusState *sbs = G364(dev);
496 G364State *s = &sbs->g364;
497 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
498
499 g364fb_init(dev, s);
500 sysbus_init_irq(sbd, &s->irq);
501 sysbus_init_mmio(sbd, &s->mem_ctrl);
502 sysbus_init_mmio(sbd, &s->mem_vram);
503}
504
505static void g364fb_sysbus_reset(DeviceState *d)
506{
507 G364SysBusState *s = G364(d);
508
509 g364fb_reset(&s->g364);
510}
511
512static Property g364fb_sysbus_properties[] = {
513 DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, 8 * MiB),
514 DEFINE_PROP_END_OF_LIST(),
515};
516
517static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
518{
519 DeviceClass *dc = DEVICE_CLASS(klass);
520
521 dc->realize = g364fb_sysbus_realize;
522 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
523 dc->desc = "G364 framebuffer";
524 dc->reset = g364fb_sysbus_reset;
525 dc->vmsd = &vmstate_g364fb;
526 dc->props = g364fb_sysbus_properties;
527}
528
529static const TypeInfo g364fb_sysbus_info = {
530 .name = TYPE_G364,
531 .parent = TYPE_SYS_BUS_DEVICE,
532 .instance_size = sizeof(G364SysBusState),
533 .class_init = g364fb_sysbus_class_init,
534};
535
536static void g364fb_register_types(void)
537{
538 type_register_static(&g364fb_sysbus_info);
539}
540
541type_init(g364fb_register_types)
542
