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11#include "qemu/osdep.h"
12#include "hw/hw.h"
13#include "hw/arm/pxa.h"
14#include "hw/sysbus.h"
15#include "qapi/error.h"
16#include "qemu/module.h"
17
18#define PXA255_DMA_NUM_CHANNELS 16
19#define PXA27X_DMA_NUM_CHANNELS 32
20
21#define PXA2XX_DMA_NUM_REQUESTS 75
22
23typedef struct {
24 uint32_t descr;
25 uint32_t src;
26 uint32_t dest;
27 uint32_t cmd;
28 uint32_t state;
29 int request;
30} PXA2xxDMAChannel;
31
32#define TYPE_PXA2XX_DMA "pxa2xx-dma"
33#define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA)
34
35typedef struct PXA2xxDMAState {
36 SysBusDevice parent_obj;
37
38 MemoryRegion iomem;
39 qemu_irq irq;
40
41 uint32_t stopintr;
42 uint32_t eorintr;
43 uint32_t rasintr;
44 uint32_t startintr;
45 uint32_t endintr;
46
47 uint32_t align;
48 uint32_t pio;
49
50 int channels;
51 PXA2xxDMAChannel *chan;
52
53 uint8_t req[PXA2XX_DMA_NUM_REQUESTS];
54
55
56 int running;
57} PXA2xxDMAState;
58
59#define DCSR0 0x0000
60#define DCSR31 0x007c
61#define DALGN 0x00a0
62#define DPCSR 0x00a4
63#define DRQSR0 0x00e0
64#define DRQSR1 0x00e4
65#define DRQSR2 0x00e8
66#define DINT 0x00f0
67#define DRCMR0 0x0100
68#define DRCMR63 0x01fc
69#define D_CH0 0x0200
70#define DRCMR64 0x1100
71#define DRCMR74 0x1128
72
73
74#define DDADR 0x00
75#define DSADR 0x01
76#define DTADR 0x02
77#define DCMD 0x03
78
79
80#define DRCMR_CHLNUM 0x1f
81#define DRCMR_MAPVLD (1 << 7)
82#define DDADR_STOP (1 << 0)
83#define DDADR_BREN (1 << 1)
84#define DCMD_LEN 0x1fff
85#define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1))
86#define DCMD_SIZE(x) (4 << (((x) >> 16) & 3))
87#define DCMD_FLYBYT (1 << 19)
88#define DCMD_FLYBYS (1 << 20)
89#define DCMD_ENDIRQEN (1 << 21)
90#define DCMD_STARTIRQEN (1 << 22)
91#define DCMD_CMPEN (1 << 25)
92#define DCMD_FLOWTRG (1 << 28)
93#define DCMD_FLOWSRC (1 << 29)
94#define DCMD_INCTRGADDR (1 << 30)
95#define DCMD_INCSRCADDR (1 << 31)
96#define DCSR_BUSERRINTR (1 << 0)
97#define DCSR_STARTINTR (1 << 1)
98#define DCSR_ENDINTR (1 << 2)
99#define DCSR_STOPINTR (1 << 3)
100#define DCSR_RASINTR (1 << 4)
101#define DCSR_REQPEND (1 << 8)
102#define DCSR_EORINT (1 << 9)
103#define DCSR_CMPST (1 << 10)
104#define DCSR_MASKRUN (1 << 22)
105#define DCSR_RASIRQEN (1 << 23)
106#define DCSR_CLRCMPST (1 << 24)
107#define DCSR_SETCMPST (1 << 25)
108#define DCSR_EORSTOPEN (1 << 26)
109#define DCSR_EORJMPEN (1 << 27)
110#define DCSR_EORIRQEN (1 << 28)
111#define DCSR_STOPIRQEN (1 << 29)
112#define DCSR_NODESCFETCH (1 << 30)
113#define DCSR_RUN (1 << 31)
114
115static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
116{
117 if (ch >= 0) {
118 if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
119 (s->chan[ch].state & DCSR_STOPINTR))
120 s->stopintr |= 1 << ch;
121 else
122 s->stopintr &= ~(1 << ch);
123
124 if ((s->chan[ch].state & DCSR_EORIRQEN) &&
125 (s->chan[ch].state & DCSR_EORINT))
126 s->eorintr |= 1 << ch;
127 else
128 s->eorintr &= ~(1 << ch);
129
130 if ((s->chan[ch].state & DCSR_RASIRQEN) &&
131 (s->chan[ch].state & DCSR_RASINTR))
132 s->rasintr |= 1 << ch;
133 else
134 s->rasintr &= ~(1 << ch);
135
136 if (s->chan[ch].state & DCSR_STARTINTR)
137 s->startintr |= 1 << ch;
138 else
139 s->startintr &= ~(1 << ch);
140
141 if (s->chan[ch].state & DCSR_ENDINTR)
142 s->endintr |= 1 << ch;
143 else
144 s->endintr &= ~(1 << ch);
145 }
146
147 if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr)
148 qemu_irq_raise(s->irq);
149 else
150 qemu_irq_lower(s->irq);
151}
152
153static inline void pxa2xx_dma_descriptor_fetch(
154 PXA2xxDMAState *s, int ch)
155{
156 uint32_t desc[4];
157 hwaddr daddr = s->chan[ch].descr & ~0xf;
158 if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
159 daddr += 32;
160
161 cpu_physical_memory_read(daddr, desc, 16);
162 s->chan[ch].descr = desc[DDADR];
163 s->chan[ch].src = desc[DSADR];
164 s->chan[ch].dest = desc[DTADR];
165 s->chan[ch].cmd = desc[DCMD];
166
167 if (s->chan[ch].cmd & DCMD_FLOWSRC)
168 s->chan[ch].src &= ~3;
169 if (s->chan[ch].cmd & DCMD_FLOWTRG)
170 s->chan[ch].dest &= ~3;
171
172 if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT))
173 printf("%s: unsupported mode in channel %i\n", __func__, ch);
174
175 if (s->chan[ch].cmd & DCMD_STARTIRQEN)
176 s->chan[ch].state |= DCSR_STARTINTR;
177}
178
179static void pxa2xx_dma_run(PXA2xxDMAState *s)
180{
181 int c, srcinc, destinc;
182 uint32_t n, size;
183 uint32_t width;
184 uint32_t length;
185 uint8_t buffer[32];
186 PXA2xxDMAChannel *ch;
187
188 if (s->running ++)
189 return;
190
191 while (s->running) {
192 s->running = 1;
193 for (c = 0; c < s->channels; c ++) {
194 ch = &s->chan[c];
195
196 while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
197
198 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request)
199 break;
200
201 length = ch->cmd & DCMD_LEN;
202 size = DCMD_SIZE(ch->cmd);
203 width = DCMD_WIDTH(ch->cmd);
204
205 srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
206 destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;
207
208 while (length) {
209 size = MIN(length, size);
210
211 for (n = 0; n < size; n += width) {
212 cpu_physical_memory_read(ch->src, buffer + n, width);
213 ch->src += srcinc;
214 }
215
216 for (n = 0; n < size; n += width) {
217 cpu_physical_memory_write(ch->dest, buffer + n, width);
218 ch->dest += destinc;
219 }
220
221 length -= size;
222
223 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) &&
224 !ch->request) {
225 ch->state |= DCSR_EORINT;
226 if (ch->state & DCSR_EORSTOPEN)
227 ch->state |= DCSR_STOPINTR;
228 if ((ch->state & DCSR_EORJMPEN) &&
229 !(ch->state & DCSR_NODESCFETCH))
230 pxa2xx_dma_descriptor_fetch(s, c);
231 break;
232 }
233 }
234
235 ch->cmd = (ch->cmd & ~DCMD_LEN) | length;
236
237
238 if (!length) {
239 if (ch->cmd & DCMD_ENDIRQEN)
240 ch->state |= DCSR_ENDINTR;
241
242 if ((ch->state & DCSR_NODESCFETCH) ||
243 (ch->descr & DDADR_STOP) ||
244 (ch->state & DCSR_EORSTOPEN)) {
245 ch->state |= DCSR_STOPINTR;
246 ch->state &= ~DCSR_RUN;
247
248 break;
249 }
250
251 ch->state |= DCSR_STOPINTR;
252 break;
253 }
254 }
255 }
256
257 s->running --;
258 }
259}
260
261static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
262 unsigned size)
263{
264 PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
265 unsigned int channel;
266
267 if (size != 4) {
268 hw_error("%s: Bad access width\n", __func__);
269 return 5;
270 }
271
272 switch (offset) {
273 case DRCMR64 ... DRCMR74:
274 offset -= DRCMR64 - DRCMR0 - (64 << 2);
275
276 case DRCMR0 ... DRCMR63:
277 channel = (offset - DRCMR0) >> 2;
278 return s->req[channel];
279
280 case DRQSR0:
281 case DRQSR1:
282 case DRQSR2:
283 return 0;
284
285 case DCSR0 ... DCSR31:
286 channel = offset >> 2;
287 if (s->chan[channel].request)
288 return s->chan[channel].state | DCSR_REQPEND;
289 return s->chan[channel].state;
290
291 case DINT:
292 return s->stopintr | s->eorintr | s->rasintr |
293 s->startintr | s->endintr;
294
295 case DALGN:
296 return s->align;
297
298 case DPCSR:
299 return s->pio;
300 }
301
302 if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
303 channel = (offset - D_CH0) >> 4;
304 switch ((offset & 0x0f) >> 2) {
305 case DDADR:
306 return s->chan[channel].descr;
307 case DSADR:
308 return s->chan[channel].src;
309 case DTADR:
310 return s->chan[channel].dest;
311 case DCMD:
312 return s->chan[channel].cmd;
313 }
314 }
315
316 hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
317 return 7;
318}
319
320static void pxa2xx_dma_write(void *opaque, hwaddr offset,
321 uint64_t value, unsigned size)
322{
323 PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
324 unsigned int channel;
325
326 if (size != 4) {
327 hw_error("%s: Bad access width\n", __func__);
328 return;
329 }
330
331 switch (offset) {
332 case DRCMR64 ... DRCMR74:
333 offset -= DRCMR64 - DRCMR0 - (64 << 2);
334
335 case DRCMR0 ... DRCMR63:
336 channel = (offset - DRCMR0) >> 2;
337
338 if (value & DRCMR_MAPVLD)
339 if ((value & DRCMR_CHLNUM) > s->channels)
340 hw_error("%s: Bad DMA channel %i\n",
341 __func__, (unsigned)value & DRCMR_CHLNUM);
342
343 s->req[channel] = value;
344 break;
345
346 case DRQSR0:
347 case DRQSR1:
348 case DRQSR2:
349
350 break;
351
352 case DCSR0 ... DCSR31:
353 channel = offset >> 2;
354 s->chan[channel].state &= 0x0000071f & ~(value &
355 (DCSR_EORINT | DCSR_ENDINTR |
356 DCSR_STARTINTR | DCSR_BUSERRINTR));
357 s->chan[channel].state |= value & 0xfc800000;
358
359 if (s->chan[channel].state & DCSR_STOPIRQEN)
360 s->chan[channel].state &= ~DCSR_STOPINTR;
361
362 if (value & DCSR_NODESCFETCH) {
363
364 if (value & DCSR_RUN) {
365 s->chan[channel].state &= ~DCSR_STOPINTR;
366 pxa2xx_dma_run(s);
367 }
368 } else {
369
370 if (value & DCSR_RUN) {
371 s->chan[channel].state &= ~DCSR_STOPINTR;
372 pxa2xx_dma_descriptor_fetch(s, channel);
373 pxa2xx_dma_run(s);
374 }
375 }
376
377
378 if (!(value & (DCSR_RUN | DCSR_MASKRUN)))
379 s->chan[channel].state |= DCSR_STOPINTR;
380
381 if (value & DCSR_CLRCMPST)
382 s->chan[channel].state &= ~DCSR_CMPST;
383 if (value & DCSR_SETCMPST)
384 s->chan[channel].state |= DCSR_CMPST;
385
386 pxa2xx_dma_update(s, channel);
387 break;
388
389 case DALGN:
390 s->align = value;
391 break;
392
393 case DPCSR:
394 s->pio = value & 0x80000001;
395 break;
396
397 default:
398 if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
399 channel = (offset - D_CH0) >> 4;
400 switch ((offset & 0x0f) >> 2) {
401 case DDADR:
402 s->chan[channel].descr = value;
403 break;
404 case DSADR:
405 s->chan[channel].src = value;
406 break;
407 case DTADR:
408 s->chan[channel].dest = value;
409 break;
410 case DCMD:
411 s->chan[channel].cmd = value;
412 break;
413 default:
414 goto fail;
415 }
416
417 break;
418 }
419 fail:
420 hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset);
421 }
422}
423
424static const MemoryRegionOps pxa2xx_dma_ops = {
425 .read = pxa2xx_dma_read,
426 .write = pxa2xx_dma_write,
427 .endianness = DEVICE_NATIVE_ENDIAN,
428};
429
430static void pxa2xx_dma_request(void *opaque, int req_num, int on)
431{
432 PXA2xxDMAState *s = opaque;
433 int ch;
434 if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
435 hw_error("%s: Bad DMA request %i\n", __func__, req_num);
436
437 if (!(s->req[req_num] & DRCMR_MAPVLD))
438 return;
439 ch = s->req[req_num] & DRCMR_CHLNUM;
440
441 if (!s->chan[ch].request && on)
442 s->chan[ch].state |= DCSR_RASINTR;
443 else
444 s->chan[ch].state &= ~DCSR_RASINTR;
445 if (s->chan[ch].request && !on)
446 s->chan[ch].state |= DCSR_EORINT;
447
448 s->chan[ch].request = on;
449 if (on) {
450 pxa2xx_dma_run(s);
451 pxa2xx_dma_update(s, ch);
452 }
453}
454
455static void pxa2xx_dma_init(Object *obj)
456{
457 DeviceState *dev = DEVICE(obj);
458 PXA2xxDMAState *s = PXA2XX_DMA(obj);
459 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
460
461 memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
462
463 qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
464
465 memory_region_init_io(&s->iomem, obj, &pxa2xx_dma_ops, s,
466 "pxa2xx.dma", 0x00010000);
467 sysbus_init_mmio(sbd, &s->iomem);
468 sysbus_init_irq(sbd, &s->irq);
469}
470
471static void pxa2xx_dma_realize(DeviceState *dev, Error **errp)
472{
473 PXA2xxDMAState *s = PXA2XX_DMA(dev);
474 int i;
475
476 if (s->channels <= 0) {
477 error_setg(errp, "channels value invalid");
478 return;
479 }
480
481 s->chan = g_new0(PXA2xxDMAChannel, s->channels);
482
483 for (i = 0; i < s->channels; i ++)
484 s->chan[i].state = DCSR_STOPINTR;
485}
486
487DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
488{
489 DeviceState *dev;
490
491 dev = qdev_create(NULL, "pxa2xx-dma");
492 qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
493 qdev_init_nofail(dev);
494
495 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
496 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
497
498 return dev;
499}
500
501DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
502{
503 DeviceState *dev;
504
505 dev = qdev_create(NULL, "pxa2xx-dma");
506 qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
507 qdev_init_nofail(dev);
508
509 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
510 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
511
512 return dev;
513}
514
515static bool is_version_0(void *opaque, int version_id)
516{
517 return version_id == 0;
518}
519
520static VMStateDescription vmstate_pxa2xx_dma_chan = {
521 .name = "pxa2xx_dma_chan",
522 .version_id = 1,
523 .minimum_version_id = 1,
524 .fields = (VMStateField[]) {
525 VMSTATE_UINT32(descr, PXA2xxDMAChannel),
526 VMSTATE_UINT32(src, PXA2xxDMAChannel),
527 VMSTATE_UINT32(dest, PXA2xxDMAChannel),
528 VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
529 VMSTATE_UINT32(state, PXA2xxDMAChannel),
530 VMSTATE_INT32(request, PXA2xxDMAChannel),
531 VMSTATE_END_OF_LIST(),
532 },
533};
534
535static VMStateDescription vmstate_pxa2xx_dma = {
536 .name = "pxa2xx_dma",
537 .version_id = 1,
538 .minimum_version_id = 0,
539 .fields = (VMStateField[]) {
540 VMSTATE_UNUSED_TEST(is_version_0, 4),
541 VMSTATE_UINT32(stopintr, PXA2xxDMAState),
542 VMSTATE_UINT32(eorintr, PXA2xxDMAState),
543 VMSTATE_UINT32(rasintr, PXA2xxDMAState),
544 VMSTATE_UINT32(startintr, PXA2xxDMAState),
545 VMSTATE_UINT32(endintr, PXA2xxDMAState),
546 VMSTATE_UINT32(align, PXA2xxDMAState),
547 VMSTATE_UINT32(pio, PXA2xxDMAState),
548 VMSTATE_BUFFER(req, PXA2xxDMAState),
549 VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
550 vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
551 VMSTATE_END_OF_LIST(),
552 },
553};
554
555static Property pxa2xx_dma_properties[] = {
556 DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
557 DEFINE_PROP_END_OF_LIST(),
558};
559
560static void pxa2xx_dma_class_init(ObjectClass *klass, void *data)
561{
562 DeviceClass *dc = DEVICE_CLASS(klass);
563
564 dc->desc = "PXA2xx DMA controller";
565 dc->vmsd = &vmstate_pxa2xx_dma;
566 dc->props = pxa2xx_dma_properties;
567 dc->realize = pxa2xx_dma_realize;
568}
569
570static const TypeInfo pxa2xx_dma_info = {
571 .name = TYPE_PXA2XX_DMA,
572 .parent = TYPE_SYS_BUS_DEVICE,
573 .instance_size = sizeof(PXA2xxDMAState),
574 .instance_init = pxa2xx_dma_init,
575 .class_init = pxa2xx_dma_class_init,
576};
577
578static void pxa2xx_dma_register_types(void)
579{
580 type_register_static(&pxa2xx_dma_info);
581}
582
583type_init(pxa2xx_dma_register_types)
584
