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28#include "qemu/osdep.h"
29#include "hw/hw.h"
30#include "hw/sparc/sparc32_dma.h"
31#include "hw/sparc/sun4m_iommu.h"
32#include "hw/sysbus.h"
33#include "sysemu/dma.h"
34#include "qapi/error.h"
35#include "qemu/module.h"
36#include "trace.h"
37
38
39
40
41
42
43
44
45
46#define DMA_SIZE (4 * sizeof(uint32_t))
47
48
49#define DMA_MASK (DMA_SIZE - 1)
50
51#define DMA_ETH_SIZE (8 * sizeof(uint32_t))
52#define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
53
54#define DMA_VER 0xa0000000
55#define DMA_INTR 1
56#define DMA_INTREN 0x10
57#define DMA_WRITE_MEM 0x100
58#define DMA_EN 0x200
59#define DMA_LOADED 0x04000000
60#define DMA_DRAIN_FIFO 0x40
61#define DMA_RESET 0x80
62
63
64#define DMA_CSR_RO_MASK 0xfe000007
65
66enum {
67 GPIO_RESET = 0,
68 GPIO_DMA,
69};
70
71
72void ledma_memory_read(void *opaque, hwaddr addr,
73 uint8_t *buf, int len, int do_bswap)
74{
75 DMADeviceState *s = opaque;
76 IOMMUState *is = (IOMMUState *)s->iommu;
77 int i;
78
79 addr |= s->dmaregs[3];
80 trace_ledma_memory_read(addr, len);
81 if (do_bswap) {
82 dma_memory_read(&is->iommu_as, addr, buf, len);
83 } else {
84 addr &= ~1;
85 len &= ~1;
86 dma_memory_read(&is->iommu_as, addr, buf, len);
87 for(i = 0; i < len; i += 2) {
88 bswap16s((uint16_t *)(buf + i));
89 }
90 }
91}
92
93void ledma_memory_write(void *opaque, hwaddr addr,
94 uint8_t *buf, int len, int do_bswap)
95{
96 DMADeviceState *s = opaque;
97 IOMMUState *is = (IOMMUState *)s->iommu;
98 int l, i;
99 uint16_t tmp_buf[32];
100
101 addr |= s->dmaregs[3];
102 trace_ledma_memory_write(addr, len);
103 if (do_bswap) {
104 dma_memory_write(&is->iommu_as, addr, buf, len);
105 } else {
106 addr &= ~1;
107 len &= ~1;
108 while (len > 0) {
109 l = len;
110 if (l > sizeof(tmp_buf))
111 l = sizeof(tmp_buf);
112 for(i = 0; i < l; i += 2) {
113 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
114 }
115 dma_memory_write(&is->iommu_as, addr, tmp_buf, l);
116 len -= l;
117 buf += l;
118 addr += l;
119 }
120 }
121}
122
123static void dma_set_irq(void *opaque, int irq, int level)
124{
125 DMADeviceState *s = opaque;
126 if (level) {
127 s->dmaregs[0] |= DMA_INTR;
128 if (s->dmaregs[0] & DMA_INTREN) {
129 trace_sparc32_dma_set_irq_raise();
130 qemu_irq_raise(s->irq);
131 }
132 } else {
133 if (s->dmaregs[0] & DMA_INTR) {
134 s->dmaregs[0] &= ~DMA_INTR;
135 if (s->dmaregs[0] & DMA_INTREN) {
136 trace_sparc32_dma_set_irq_lower();
137 qemu_irq_lower(s->irq);
138 }
139 }
140 }
141}
142
143void espdma_memory_read(void *opaque, uint8_t *buf, int len)
144{
145 DMADeviceState *s = opaque;
146 IOMMUState *is = (IOMMUState *)s->iommu;
147
148 trace_espdma_memory_read(s->dmaregs[1], len);
149 dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len);
150 s->dmaregs[1] += len;
151}
152
153void espdma_memory_write(void *opaque, uint8_t *buf, int len)
154{
155 DMADeviceState *s = opaque;
156 IOMMUState *is = (IOMMUState *)s->iommu;
157
158 trace_espdma_memory_write(s->dmaregs[1], len);
159 dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len);
160 s->dmaregs[1] += len;
161}
162
163static uint64_t dma_mem_read(void *opaque, hwaddr addr,
164 unsigned size)
165{
166 DMADeviceState *s = opaque;
167 uint32_t saddr;
168
169 saddr = (addr & DMA_MASK) >> 2;
170 trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
171 return s->dmaregs[saddr];
172}
173
174static void dma_mem_write(void *opaque, hwaddr addr,
175 uint64_t val, unsigned size)
176{
177 DMADeviceState *s = opaque;
178 uint32_t saddr;
179
180 saddr = (addr & DMA_MASK) >> 2;
181 trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
182 switch (saddr) {
183 case 0:
184 if (val & DMA_INTREN) {
185 if (s->dmaregs[0] & DMA_INTR) {
186 trace_sparc32_dma_set_irq_raise();
187 qemu_irq_raise(s->irq);
188 }
189 } else {
190 if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
191 trace_sparc32_dma_set_irq_lower();
192 qemu_irq_lower(s->irq);
193 }
194 }
195 if (val & DMA_RESET) {
196 qemu_irq_raise(s->gpio[GPIO_RESET]);
197 qemu_irq_lower(s->gpio[GPIO_RESET]);
198 } else if (val & DMA_DRAIN_FIFO) {
199 val &= ~DMA_DRAIN_FIFO;
200 } else if (val == 0)
201 val = DMA_DRAIN_FIFO;
202
203 if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
204 trace_sparc32_dma_enable_raise();
205 qemu_irq_raise(s->gpio[GPIO_DMA]);
206 } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
207 trace_sparc32_dma_enable_lower();
208 qemu_irq_lower(s->gpio[GPIO_DMA]);
209 }
210
211 val &= ~DMA_CSR_RO_MASK;
212 val |= DMA_VER;
213 s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
214 break;
215 case 1:
216 s->dmaregs[0] |= DMA_LOADED;
217
218 default:
219 s->dmaregs[saddr] = val;
220 break;
221 }
222}
223
224static const MemoryRegionOps dma_mem_ops = {
225 .read = dma_mem_read,
226 .write = dma_mem_write,
227 .endianness = DEVICE_NATIVE_ENDIAN,
228 .valid = {
229 .min_access_size = 4,
230 .max_access_size = 4,
231 },
232};
233
234static void sparc32_dma_device_reset(DeviceState *d)
235{
236 DMADeviceState *s = SPARC32_DMA_DEVICE(d);
237
238 memset(s->dmaregs, 0, DMA_SIZE);
239 s->dmaregs[0] = DMA_VER;
240}
241
242static const VMStateDescription vmstate_sparc32_dma_device = {
243 .name ="sparc32_dma",
244 .version_id = 2,
245 .minimum_version_id = 2,
246 .fields = (VMStateField[]) {
247 VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),
248 VMSTATE_END_OF_LIST()
249 }
250};
251
252static void sparc32_dma_device_init(Object *obj)
253{
254 DeviceState *dev = DEVICE(obj);
255 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
256 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
257
258 sysbus_init_irq(sbd, &s->irq);
259
260 sysbus_init_mmio(sbd, &s->iomem);
261
262 object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU,
263 (Object **) &s->iommu,
264 qdev_prop_allow_set_link_before_realize,
265 0, NULL);
266
267 qdev_init_gpio_in(dev, dma_set_irq, 1);
268 qdev_init_gpio_out(dev, s->gpio, 2);
269}
270
271static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
272{
273 DeviceClass *dc = DEVICE_CLASS(klass);
274
275 dc->reset = sparc32_dma_device_reset;
276 dc->vmsd = &vmstate_sparc32_dma_device;
277}
278
279static const TypeInfo sparc32_dma_device_info = {
280 .name = TYPE_SPARC32_DMA_DEVICE,
281 .parent = TYPE_SYS_BUS_DEVICE,
282 .abstract = true,
283 .instance_size = sizeof(DMADeviceState),
284 .instance_init = sparc32_dma_device_init,
285 .class_init = sparc32_dma_device_class_init,
286};
287
288static void sparc32_espdma_device_init(Object *obj)
289{
290 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
291
292 memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
293 "espdma-mmio", DMA_SIZE);
294}
295
296static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
297{
298 DeviceState *d;
299 SysBusESPState *sysbus;
300 ESPState *esp;
301
302 d = qdev_create(NULL, TYPE_ESP);
303 object_property_add_child(OBJECT(dev), "esp", OBJECT(d), errp);
304 sysbus = ESP_STATE(d);
305 esp = &sysbus->esp;
306 esp->dma_memory_read = espdma_memory_read;
307 esp->dma_memory_write = espdma_memory_write;
308 esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
309 sysbus->it_shift = 2;
310 esp->dma_enabled = 1;
311 qdev_init_nofail(d);
312}
313
314static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
315{
316 DeviceClass *dc = DEVICE_CLASS(klass);
317
318 dc->realize = sparc32_espdma_device_realize;
319}
320
321static const TypeInfo sparc32_espdma_device_info = {
322 .name = TYPE_SPARC32_ESPDMA_DEVICE,
323 .parent = TYPE_SPARC32_DMA_DEVICE,
324 .instance_size = sizeof(ESPDMADeviceState),
325 .instance_init = sparc32_espdma_device_init,
326 .class_init = sparc32_espdma_device_class_init,
327};
328
329static void sparc32_ledma_device_init(Object *obj)
330{
331 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
332
333 memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
334 "ledma-mmio", DMA_SIZE);
335}
336
337static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
338{
339 DeviceState *d;
340 NICInfo *nd = &nd_table[0];
341
342 qemu_check_nic_model(nd, TYPE_LANCE);
343
344 d = qdev_create(NULL, TYPE_LANCE);
345 object_property_add_child(OBJECT(dev), "lance", OBJECT(d), errp);
346 qdev_set_nic_properties(d, nd);
347 qdev_prop_set_ptr(d, "dma", dev);
348 qdev_init_nofail(d);
349}
350
351static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
352{
353 DeviceClass *dc = DEVICE_CLASS(klass);
354
355 dc->realize = sparc32_ledma_device_realize;
356}
357
358static const TypeInfo sparc32_ledma_device_info = {
359 .name = TYPE_SPARC32_LEDMA_DEVICE,
360 .parent = TYPE_SPARC32_DMA_DEVICE,
361 .instance_size = sizeof(LEDMADeviceState),
362 .instance_init = sparc32_ledma_device_init,
363 .class_init = sparc32_ledma_device_class_init,
364};
365
366static void sparc32_dma_realize(DeviceState *dev, Error **errp)
367{
368 SPARC32DMAState *s = SPARC32_DMA(dev);
369 DeviceState *espdma, *esp, *ledma, *lance;
370 SysBusDevice *sbd;
371 Object *iommu;
372
373 iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL);
374 if (!iommu) {
375 error_setg(errp, "unable to locate sun4m IOMMU device");
376 return;
377 }
378
379 espdma = qdev_create(NULL, TYPE_SPARC32_ESPDMA_DEVICE);
380 object_property_set_link(OBJECT(espdma), iommu, "iommu", errp);
381 object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma), errp);
382 qdev_init_nofail(espdma);
383
384 esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
385 sbd = SYS_BUS_DEVICE(esp);
386 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0));
387 qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0));
388 qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1));
389
390 sbd = SYS_BUS_DEVICE(espdma);
391 memory_region_add_subregion(&s->dmamem, 0x0,
392 sysbus_mmio_get_region(sbd, 0));
393
394 ledma = qdev_create(NULL, TYPE_SPARC32_LEDMA_DEVICE);
395 object_property_set_link(OBJECT(ledma), iommu, "iommu", errp);
396 object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma), errp);
397 qdev_init_nofail(ledma);
398
399 lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
400 sbd = SYS_BUS_DEVICE(lance);
401 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0));
402 qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0));
403
404 sbd = SYS_BUS_DEVICE(ledma);
405 memory_region_add_subregion(&s->dmamem, 0x10,
406 sysbus_mmio_get_region(sbd, 0));
407
408
409 memory_region_init_alias(&s->ledma_alias, OBJECT(dev), "ledma-alias",
410 sysbus_mmio_get_region(sbd, 0), 0x4, 0x4);
411 memory_region_add_subregion(&s->dmamem, 0x20, &s->ledma_alias);
412}
413
414static void sparc32_dma_init(Object *obj)
415{
416 SPARC32DMAState *s = SPARC32_DMA(obj);
417 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
418
419 memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
420 sysbus_init_mmio(sbd, &s->dmamem);
421}
422
423static void sparc32_dma_class_init(ObjectClass *klass, void *data)
424{
425 DeviceClass *dc = DEVICE_CLASS(klass);
426
427 dc->realize = sparc32_dma_realize;
428}
429
430static const TypeInfo sparc32_dma_info = {
431 .name = TYPE_SPARC32_DMA,
432 .parent = TYPE_SYS_BUS_DEVICE,
433 .instance_size = sizeof(SPARC32DMAState),
434 .instance_init = sparc32_dma_init,
435 .class_init = sparc32_dma_class_init,
436};
437
438
439static void sparc32_dma_register_types(void)
440{
441 type_register_static(&sparc32_dma_device_info);
442 type_register_static(&sparc32_espdma_device_info);
443 type_register_static(&sparc32_ledma_device_info);
444 type_register_static(&sparc32_dma_info);
445}
446
447type_init(sparc32_dma_register_types)
448
