LXR qemu/hw/i386/intel_iommu

   1/*
   2 * QEMU emulation of an Intel IOMMU (VT-d)
   3 *   (DMA Remapping device)
   4 *
   5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
   6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17
  18 * You should have received a copy of the GNU General Public License along
  19 * with this program; if not, see <http://www.gnu.org/licenses/>.
  20 *
  21 * Lots of defines copied from kernel/include/linux/intel-iommu.h:
  22 *   Copyright (C) 2006-2008 Intel Corporation
  23 *   Author: Ashok Raj <ashok.raj@intel.com>
  24 *   Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  25 *
  26 */
  27
  28#ifndef HW_I386_INTEL_IOMMU_INTERNAL_H
  29#define HW_I386_INTEL_IOMMU_INTERNAL_H
  30#include "hw/i386/intel_iommu.h"
  31
  32/*
  33 * Intel IOMMU register specification
  34 */
  35#define DMAR_VER_REG            0x0  /* Arch version supported by this IOMMU */
  36#define DMAR_CAP_REG            0x8  /* Hardware supported capabilities */
  37#define DMAR_CAP_REG_HI         0xc  /* High 32-bit of DMAR_CAP_REG */
  38#define DMAR_ECAP_REG           0x10 /* Extended capabilities supported */
  39#define DMAR_ECAP_REG_HI        0X14
  40#define DMAR_GCMD_REG           0x18 /* Global command */
  41#define DMAR_GSTS_REG           0x1c /* Global status */
  42#define DMAR_RTADDR_REG         0x20 /* Root entry table */
  43#define DMAR_RTADDR_REG_HI      0X24
  44#define DMAR_CCMD_REG           0x28 /* Context command */
  45#define DMAR_CCMD_REG_HI        0x2c
  46#define DMAR_FSTS_REG           0x34 /* Fault status */
  47#define DMAR_FECTL_REG          0x38 /* Fault control */
  48#define DMAR_FEDATA_REG         0x3c /* Fault event interrupt data */
  49#define DMAR_FEADDR_REG         0x40 /* Fault event interrupt addr */
  50#define DMAR_FEUADDR_REG        0x44 /* Upper address */
  51#define DMAR_AFLOG_REG          0x58 /* Advanced fault control */
  52#define DMAR_AFLOG_REG_HI       0X5c
  53#define DMAR_PMEN_REG           0x64 /* Enable protected memory region */
  54#define DMAR_PLMBASE_REG        0x68 /* PMRR low addr */
  55#define DMAR_PLMLIMIT_REG       0x6c /* PMRR low limit */
  56#define DMAR_PHMBASE_REG        0x70 /* PMRR high base addr */
  57#define DMAR_PHMBASE_REG_HI     0X74
  58#define DMAR_PHMLIMIT_REG       0x78 /* PMRR high limit */
  59#define DMAR_PHMLIMIT_REG_HI    0x7c
  60#define DMAR_IQH_REG            0x80 /* Invalidation queue head */
  61#define DMAR_IQH_REG_HI         0X84
  62#define DMAR_IQT_REG            0x88 /* Invalidation queue tail */
  63#define DMAR_IQT_REG_HI         0X8c
  64#define DMAR_IQA_REG            0x90 /* Invalidation queue addr */
  65#define DMAR_IQA_REG_HI         0x94
  66#define DMAR_ICS_REG            0x9c /* Invalidation complete status */
  67#define DMAR_IRTA_REG           0xb8 /* Interrupt remapping table addr */
  68#define DMAR_IRTA_REG_HI        0xbc
  69#define DMAR_IECTL_REG          0xa0 /* Invalidation event control */
  70#define DMAR_IEDATA_REG         0xa4 /* Invalidation event data */
  71#define DMAR_IEADDR_REG         0xa8 /* Invalidation event address */
  72#define DMAR_IEUADDR_REG        0xac /* Invalidation event address */
  73#define DMAR_PQH_REG            0xc0 /* Page request queue head */
  74#define DMAR_PQH_REG_HI         0xc4
  75#define DMAR_PQT_REG            0xc8 /* Page request queue tail*/
  76#define DMAR_PQT_REG_HI         0xcc
  77#define DMAR_PQA_REG            0xd0 /* Page request queue address */
  78#define DMAR_PQA_REG_HI         0xd4
  79#define DMAR_PRS_REG            0xdc /* Page request status */
  80#define DMAR_PECTL_REG          0xe0 /* Page request event control */
  81#define DMAR_PEDATA_REG         0xe4 /* Page request event data */
  82#define DMAR_PEADDR_REG         0xe8 /* Page request event address */
  83#define DMAR_PEUADDR_REG        0xec /* Page event upper address */
  84#define DMAR_MTRRCAP_REG        0x100 /* MTRR capability */
  85#define DMAR_MTRRCAP_REG_HI     0x104
  86#define DMAR_MTRRDEF_REG        0x108 /* MTRR default type */
  87#define DMAR_MTRRDEF_REG_HI     0x10c
  88
  89/* IOTLB registers */
  90#define DMAR_IOTLB_REG_OFFSET   0xf0 /* Offset to the IOTLB registers */
  91#define DMAR_IVA_REG            DMAR_IOTLB_REG_OFFSET /* Invalidate address */
  92#define DMAR_IVA_REG_HI         (DMAR_IVA_REG + 4)
  93/* IOTLB invalidate register */
  94#define DMAR_IOTLB_REG          (DMAR_IOTLB_REG_OFFSET + 0x8)
  95#define DMAR_IOTLB_REG_HI       (DMAR_IOTLB_REG + 4)
  96
  97/* FRCD */
  98#define DMAR_FRCD_REG_OFFSET    0x220 /* Offset to the fault recording regs */
  99/* NOTICE: If you change the DMAR_FRCD_REG_NR, please remember to change the
 100 * DMAR_REG_SIZE in include/hw/i386/intel_iommu.h.
 101 * #define DMAR_REG_SIZE   (DMAR_FRCD_REG_OFFSET + 16 * DMAR_FRCD_REG_NR)
 102 */
 103#define DMAR_FRCD_REG_NR        1ULL /* Num of fault recording regs */
 104
 105#define DMAR_FRCD_REG_0_0       0x220 /* The 0th fault recording regs */
 106#define DMAR_FRCD_REG_0_1       0x224
 107#define DMAR_FRCD_REG_0_2       0x228
 108#define DMAR_FRCD_REG_0_3       0x22c
 109
 110/* Interrupt Address Range */
 111#define VTD_INTERRUPT_ADDR_FIRST    0xfee00000ULL
 112#define VTD_INTERRUPT_ADDR_LAST     0xfeefffffULL
 113#define VTD_INTERRUPT_ADDR_SIZE     (VTD_INTERRUPT_ADDR_LAST - \
 114                                     VTD_INTERRUPT_ADDR_FIRST + 1)
 115
 116/* The shift of source_id in the key of IOTLB hash table */
 117#define VTD_IOTLB_SID_SHIFT         36
 118#define VTD_IOTLB_LVL_SHIFT         52
 119#define VTD_IOTLB_MAX_SIZE          1024    /* Max size of the hash table */
 120
 121/* IOTLB_REG */
 122#define VTD_TLB_GLOBAL_FLUSH        (1ULL << 60) /* Global invalidation */
 123#define VTD_TLB_DSI_FLUSH           (2ULL << 60) /* Domain-selective */
 124#define VTD_TLB_PSI_FLUSH           (3ULL << 60) /* Page-selective */
 125#define VTD_TLB_FLUSH_GRANU_MASK    (3ULL << 60)
 126#define VTD_TLB_GLOBAL_FLUSH_A      (1ULL << 57)
 127#define VTD_TLB_DSI_FLUSH_A         (2ULL << 57)
 128#define VTD_TLB_PSI_FLUSH_A         (3ULL << 57)
 129#define VTD_TLB_FLUSH_GRANU_MASK_A  (3ULL << 57)
 130#define VTD_TLB_IVT                 (1ULL << 63)
 131#define VTD_TLB_DID(val)            (((val) >> 32) & VTD_DOMAIN_ID_MASK)
 132
 133/* IVA_REG */
 134#define VTD_IVA_ADDR(val)       ((val) & ~0xfffULL)
 135#define VTD_IVA_AM(val)         ((val) & 0x3fULL)
 136
 137/* GCMD_REG */
 138#define VTD_GCMD_TE                 (1UL << 31)
 139#define VTD_GCMD_SRTP               (1UL << 30)
 140#define VTD_GCMD_SFL                (1UL << 29)
 141#define VTD_GCMD_EAFL               (1UL << 28)
 142#define VTD_GCMD_WBF                (1UL << 27)
 143#define VTD_GCMD_QIE                (1UL << 26)
 144#define VTD_GCMD_IRE                (1UL << 25)
 145#define VTD_GCMD_SIRTP              (1UL << 24)
 146#define VTD_GCMD_CFI                (1UL << 23)
 147
 148/* GSTS_REG */
 149#define VTD_GSTS_TES                (1UL << 31)
 150#define VTD_GSTS_RTPS               (1UL << 30)
 151#define VTD_GSTS_FLS                (1UL << 29)
 152#define VTD_GSTS_AFLS               (1UL << 28)
 153#define VTD_GSTS_WBFS               (1UL << 27)
 154#define VTD_GSTS_QIES               (1UL << 26)
 155#define VTD_GSTS_IRES               (1UL << 25)
 156#define VTD_GSTS_IRTPS              (1UL << 24)
 157#define VTD_GSTS_CFIS               (1UL << 23)
 158
 159/* CCMD_REG */
 160#define VTD_CCMD_ICC                (1ULL << 63)
 161#define VTD_CCMD_GLOBAL_INVL        (1ULL << 61)
 162#define VTD_CCMD_DOMAIN_INVL        (2ULL << 61)
 163#define VTD_CCMD_DEVICE_INVL        (3ULL << 61)
 164#define VTD_CCMD_CIRG_MASK          (3ULL << 61)
 165#define VTD_CCMD_GLOBAL_INVL_A      (1ULL << 59)
 166#define VTD_CCMD_DOMAIN_INVL_A      (2ULL << 59)
 167#define VTD_CCMD_DEVICE_INVL_A      (3ULL << 59)
 168#define VTD_CCMD_CAIG_MASK          (3ULL << 59)
 169#define VTD_CCMD_DID(val)           ((val) & VTD_DOMAIN_ID_MASK)
 170#define VTD_CCMD_SID(val)           (((val) >> 16) & 0xffffULL)
 171#define VTD_CCMD_FM(val)            (((val) >> 32) & 3ULL)
 172
 173/* RTADDR_REG */
 174#define VTD_RTADDR_SMT              (1ULL << 10)
 175#define VTD_RTADDR_ADDR_MASK(aw)    (VTD_HAW_MASK(aw) ^ 0xfffULL)
 176
 177/* IRTA_REG */
 178#define VTD_IRTA_ADDR_MASK(aw)      (VTD_HAW_MASK(aw) ^ 0xfffULL)
 179#define VTD_IRTA_EIME               (1ULL << 11)
 180#define VTD_IRTA_SIZE_MASK          (0xfULL)
 181
 182/* ECAP_REG */
 183/* (offset >> 4) << 8 */
 184#define VTD_ECAP_IRO                (DMAR_IOTLB_REG_OFFSET << 4)
 185#define VTD_ECAP_QI                 (1ULL << 1)
 186#define VTD_ECAP_DT                 (1ULL << 2)
 187/* Interrupt Remapping support */
 188#define VTD_ECAP_IR                 (1ULL << 3)
 189#define VTD_ECAP_EIM                (1ULL << 4)
 190#define VTD_ECAP_PT                 (1ULL << 6)
 191#define VTD_ECAP_MHMV               (15ULL << 20)
 192#define VTD_ECAP_SRS                (1ULL << 31)
 193#define VTD_ECAP_SMTS               (1ULL << 43)
 194#define VTD_ECAP_SLTS               (1ULL << 46)
 195
 196/* CAP_REG */
 197/* (offset >> 4) << 24 */
 198#define VTD_CAP_FRO                 (DMAR_FRCD_REG_OFFSET << 20)
 199#define VTD_CAP_NFR                 ((DMAR_FRCD_REG_NR - 1) << 40)
 200#define VTD_DOMAIN_ID_SHIFT         16  /* 16-bit domain id for 64K domains */
 201#define VTD_DOMAIN_ID_MASK          ((1UL << VTD_DOMAIN_ID_SHIFT) - 1)
 202#define VTD_CAP_ND                  (((VTD_DOMAIN_ID_SHIFT - 4) / 2) & 7ULL)
 203#define VTD_ADDRESS_SIZE(aw)        (1ULL << (aw))
 204#define VTD_CAP_MGAW(aw)            ((((aw) - 1) & 0x3fULL) << 16)
 205#define VTD_MAMV                    18ULL
 206#define VTD_CAP_MAMV                (VTD_MAMV << 48)
 207#define VTD_CAP_PSI                 (1ULL << 39)
 208#define VTD_CAP_SLLPS               ((1ULL << 34) | (1ULL << 35))
 209#define VTD_CAP_DRAIN_WRITE         (1ULL << 54)
 210#define VTD_CAP_DRAIN_READ          (1ULL << 55)
 211#define VTD_CAP_DRAIN               (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WRITE)
 212#define VTD_CAP_CM                  (1ULL << 7)
 213
 214/* Supported Adjusted Guest Address Widths */
 215#define VTD_CAP_SAGAW_SHIFT         8
 216#define VTD_CAP_SAGAW_MASK          (0x1fULL << VTD_CAP_SAGAW_SHIFT)
 217 /* 39-bit AGAW, 3-level page-table */
 218#define VTD_CAP_SAGAW_39bit         (0x2ULL << VTD_CAP_SAGAW_SHIFT)
 219 /* 48-bit AGAW, 4-level page-table */
 220#define VTD_CAP_SAGAW_48bit         (0x4ULL << VTD_CAP_SAGAW_SHIFT)
 221
 222/* IQT_REG */
 223#define VTD_IQT_QT(dw_bit, val)     (dw_bit ? (((val) >> 5) & 0x3fffULL) : \
 224                                     (((val) >> 4) & 0x7fffULL))
 225#define VTD_IQT_QT_256_RSV_BIT      0x10
 226
 227/* IQA_REG */
 228#define VTD_IQA_IQA_MASK(aw)        (VTD_HAW_MASK(aw) ^ 0xfffULL)
 229#define VTD_IQA_QS                  0x7ULL
 230#define VTD_IQA_DW_MASK             0x800
 231
 232/* IQH_REG */
 233#define VTD_IQH_QH_SHIFT            4
 234#define VTD_IQH_QH_MASK             0x7fff0ULL
 235
 236/* ICS_REG */
 237#define VTD_ICS_IWC                 1UL
 238
 239/* IECTL_REG */
 240#define VTD_IECTL_IM                (1UL << 31)
 241#define VTD_IECTL_IP                (1UL << 30)
 242
 243/* FSTS_REG */
 244#define VTD_FSTS_FRI_MASK       0xff00UL
 245#define VTD_FSTS_FRI(val)       ((((uint32_t)(val)) << 8) & VTD_FSTS_FRI_MASK)
 246#define VTD_FSTS_IQE            (1UL << 4)
 247#define VTD_FSTS_PPF            (1UL << 1)
 248#define VTD_FSTS_PFO            1UL
 249
 250/* FECTL_REG */
 251#define VTD_FECTL_IM            (1UL << 31)
 252#define VTD_FECTL_IP            (1UL << 30)
 253
 254/* Fault Recording Register */
 255/* For the high 64-bit of 128-bit */
 256#define VTD_FRCD_F              (1ULL << 63)
 257#define VTD_FRCD_T              (1ULL << 62)
 258#define VTD_FRCD_FR(val)        (((val) & 0xffULL) << 32)
 259#define VTD_FRCD_SID_MASK       0xffffULL
 260#define VTD_FRCD_SID(val)       ((val) & VTD_FRCD_SID_MASK)
 261/* For the low 64-bit of 128-bit */
 262#define VTD_FRCD_FI(val)        ((val) & ~0xfffULL)
 263
 264/* DMA Remapping Fault Conditions */
 265typedef enum VTDFaultReason {
 266    VTD_FR_RESERVED = 0,        /* Reserved for Advanced Fault logging */
 267    VTD_FR_ROOT_ENTRY_P = 1,    /* The Present(P) field of root-entry is 0 */
 268    VTD_FR_CONTEXT_ENTRY_P,     /* The Present(P) field of context-entry is 0 */
 269    VTD_FR_CONTEXT_ENTRY_INV,   /* Invalid programming of a context-entry */
 270    VTD_FR_ADDR_BEYOND_MGAW,    /* Input-address above (2^x-1) */
 271    VTD_FR_WRITE,               /* No write permission */
 272    VTD_FR_READ,                /* No read permission */
 273    /* Fail to access a second-level paging entry (not SL_PML4E) */
 274    VTD_FR_PAGING_ENTRY_INV,
 275    VTD_FR_ROOT_TABLE_INV,      /* Fail to access a root-entry */
 276    VTD_FR_CONTEXT_TABLE_INV,   /* Fail to access a context-entry */
 277    /* Non-zero reserved field in a present root-entry */
 278    VTD_FR_ROOT_ENTRY_RSVD,
 279    /* Non-zero reserved field in a present context-entry */
 280    VTD_FR_CONTEXT_ENTRY_RSVD,
 281    /* Non-zero reserved field in a second-level paging entry with at lease one
 282     * Read(R) and Write(W) or Execute(E) field is Set.
 283     */
 284    VTD_FR_PAGING_ENTRY_RSVD,
 285    /* Translation request or translated request explicitly blocked dut to the
 286     * programming of the Translation Type (T) field in the present
 287     * context-entry.
 288     */
 289    VTD_FR_CONTEXT_ENTRY_TT,
 290
 291    /* Interrupt remapping transition faults */
 292    VTD_FR_IR_REQ_RSVD = 0x20, /* One or more IR request reserved
 293                                * fields set */
 294    VTD_FR_IR_INDEX_OVER = 0x21, /* Index value greater than max */
 295    VTD_FR_IR_ENTRY_P = 0x22,    /* Present (P) not set in IRTE */
 296    VTD_FR_IR_ROOT_INVAL = 0x23, /* IR Root table invalid */
 297    VTD_FR_IR_IRTE_RSVD = 0x24,  /* IRTE Rsvd field non-zero with
 298                                  * Present flag set */
 299    VTD_FR_IR_REQ_COMPAT = 0x25, /* Encountered compatible IR
 300                                  * request while disabled */
 301    VTD_FR_IR_SID_ERR = 0x26,   /* Invalid Source-ID */
 302
 303    VTD_FR_PASID_TABLE_INV = 0x58,  /*Invalid PASID table entry */
 304
 305    /* This is not a normal fault reason. We use this to indicate some faults
 306     * that are not referenced by the VT-d specification.
 307     * Fault event with such reason should not be recorded.
 308     */
 309    VTD_FR_RESERVED_ERR,
 310    VTD_FR_MAX,                 /* Guard */
 311} VTDFaultReason;
 312
 313#define VTD_CONTEXT_CACHE_GEN_MAX       0xffffffffUL
 314
 315/* Interrupt Entry Cache Invalidation Descriptor: VT-d 6.5.2.7. */
 316struct VTDInvDescIEC {
 317    uint32_t type:4;            /* Should always be 0x4 */
 318    uint32_t granularity:1;     /* If set, it's global IR invalidation */
 319    uint32_t resved_1:22;
 320    uint32_t index_mask:5;      /* 2^N for continuous int invalidation */
 321    uint32_t index:16;          /* Start index to invalidate */
 322    uint32_t reserved_2:16;
 323};
 324typedef struct VTDInvDescIEC VTDInvDescIEC;
 325
 326/* Queued Invalidation Descriptor */
 327union VTDInvDesc {
 328    struct {
 329        uint64_t lo;
 330        uint64_t hi;
 331    };
 332    struct {
 333        uint64_t val[4];
 334    };
 335    union {
 336        VTDInvDescIEC iec;
 337    };
 338};
 339typedef union VTDInvDesc VTDInvDesc;
 340
 341/* Masks for struct VTDInvDesc */
 342#define VTD_INV_DESC_TYPE               0xf
 343#define VTD_INV_DESC_CC                 0x1 /* Context-cache Invalidate Desc */
 344#define VTD_INV_DESC_IOTLB              0x2
 345#define VTD_INV_DESC_DEVICE             0x3
 346#define VTD_INV_DESC_IEC                0x4 /* Interrupt Entry Cache
 347                                               Invalidate Descriptor */
 348#define VTD_INV_DESC_WAIT               0x5 /* Invalidation Wait Descriptor */
 349#define VTD_INV_DESC_PIOTLB             0x6 /* PASID-IOTLB Invalidate Desc */
 350#define VTD_INV_DESC_PC                 0x7 /* PASID-cache Invalidate Desc */
 351#define VTD_INV_DESC_NONE               0   /* Not an Invalidate Descriptor */
 352
 353/* Masks for Invalidation Wait Descriptor*/
 354#define VTD_INV_DESC_WAIT_SW            (1ULL << 5)
 355#define VTD_INV_DESC_WAIT_IF            (1ULL << 4)
 356#define VTD_INV_DESC_WAIT_FN            (1ULL << 6)
 357#define VTD_INV_DESC_WAIT_DATA_SHIFT    32
 358#define VTD_INV_DESC_WAIT_RSVD_LO       0Xffffff80ULL
 359#define VTD_INV_DESC_WAIT_RSVD_HI       3ULL
 360
 361/* Masks for Context-cache Invalidation Descriptor */
 362#define VTD_INV_DESC_CC_G               (3ULL << 4)
 363#define VTD_INV_DESC_CC_GLOBAL          (1ULL << 4)
 364#define VTD_INV_DESC_CC_DOMAIN          (2ULL << 4)
 365#define VTD_INV_DESC_CC_DEVICE          (3ULL << 4)
 366#define VTD_INV_DESC_CC_DID(val)        (((val) >> 16) & VTD_DOMAIN_ID_MASK)
 367#define VTD_INV_DESC_CC_SID(val)        (((val) >> 32) & 0xffffUL)
 368#define VTD_INV_DESC_CC_FM(val)         (((val) >> 48) & 3UL)
 369#define VTD_INV_DESC_CC_RSVD            0xfffc00000000ffc0ULL
 370
 371/* Masks for IOTLB Invalidate Descriptor */
 372#define VTD_INV_DESC_IOTLB_G            (3ULL << 4)
 373#define VTD_INV_DESC_IOTLB_GLOBAL       (1ULL << 4)
 374#define VTD_INV_DESC_IOTLB_DOMAIN       (2ULL << 4)
 375#define VTD_INV_DESC_IOTLB_PAGE         (3ULL << 4)
 376#define VTD_INV_DESC_IOTLB_DID(val)     (((val) >> 16) & VTD_DOMAIN_ID_MASK)
 377#define VTD_INV_DESC_IOTLB_ADDR(val)    ((val) & ~0xfffULL)
 378#define VTD_INV_DESC_IOTLB_AM(val)      ((val) & 0x3fULL)
 379#define VTD_INV_DESC_IOTLB_RSVD_LO      0xffffffff0000ff00ULL
 380#define VTD_INV_DESC_IOTLB_RSVD_HI      0xf80ULL
 381
 382/* Mask for Device IOTLB Invalidate Descriptor */
 383#define VTD_INV_DESC_DEVICE_IOTLB_ADDR(val) ((val) & 0xfffffffffffff000ULL)
 384#define VTD_INV_DESC_DEVICE_IOTLB_SIZE(val) ((val) & 0x1)
 385#define VTD_INV_DESC_DEVICE_IOTLB_SID(val) (((val) >> 32) & 0xFFFFULL)
 386#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI 0xffeULL
 387#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
 388
 389/* Rsvd field masks for spte */
 390#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
 391        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 392#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
 393        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 394#define VTD_SPTE_PAGE_L3_RSVD_MASK(aw) \
 395        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 396#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
 397        (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 398#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
 399        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 400#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
 401        (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 402#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
 403        (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 404#define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
 405        (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 406
 407/* Information about page-selective IOTLB invalidate */
 408struct VTDIOTLBPageInvInfo {
 409    uint16_t domain_id;
 410    uint64_t addr;
 411    uint8_t mask;
 412};
 413typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo;
 414
 415/* Pagesize of VTD paging structures, including root and context tables */
 416#define VTD_PAGE_SHIFT              12
 417#define VTD_PAGE_SIZE               (1ULL << VTD_PAGE_SHIFT)
 418
 419#define VTD_PAGE_SHIFT_4K           12
 420#define VTD_PAGE_MASK_4K            (~((1ULL << VTD_PAGE_SHIFT_4K) - 1))
 421#define VTD_PAGE_SHIFT_2M           21
 422#define VTD_PAGE_MASK_2M            (~((1ULL << VTD_PAGE_SHIFT_2M) - 1))
 423#define VTD_PAGE_SHIFT_1G           30
 424#define VTD_PAGE_MASK_1G            (~((1ULL << VTD_PAGE_SHIFT_1G) - 1))
 425
 426struct VTDRootEntry {
 427    uint64_t lo;
 428    uint64_t hi;
 429};
 430typedef struct VTDRootEntry VTDRootEntry;
 431
 432/* Masks for struct VTDRootEntry */
 433#define VTD_ROOT_ENTRY_P            1ULL
 434#define VTD_ROOT_ENTRY_CTP          (~0xfffULL)
 435
 436#define VTD_ROOT_ENTRY_NR           (VTD_PAGE_SIZE / sizeof(VTDRootEntry))
 437#define VTD_ROOT_ENTRY_RSVD(aw)     (0xffeULL | ~VTD_HAW_MASK(aw))
 438
 439#define VTD_DEVFN_CHECK_MASK        0x80
 440
 441/* Masks for struct VTDContextEntry */
 442/* lo */
 443#define VTD_CONTEXT_ENTRY_P         (1ULL << 0)
 444#define VTD_CONTEXT_ENTRY_FPD       (1ULL << 1) /* Fault Processing Disable */
 445#define VTD_CONTEXT_ENTRY_TT        (3ULL << 2) /* Translation Type */
 446#define VTD_CONTEXT_TT_MULTI_LEVEL  0
 447#define VTD_CONTEXT_TT_DEV_IOTLB    (1ULL << 2)
 448#define VTD_CONTEXT_TT_PASS_THROUGH (2ULL << 2)
 449/* Second Level Page Translation Pointer*/
 450#define VTD_CONTEXT_ENTRY_SLPTPTR   (~0xfffULL)
 451#define VTD_CONTEXT_ENTRY_RSVD_LO(aw) (0xff0ULL | ~VTD_HAW_MASK(aw))
 452/* hi */
 453#define VTD_CONTEXT_ENTRY_AW        7ULL /* Adjusted guest-address-width */
 454#define VTD_CONTEXT_ENTRY_DID(val)  (((val) >> 8) & VTD_DOMAIN_ID_MASK)
 455#define VTD_CONTEXT_ENTRY_RSVD_HI   0xffffffffff000080ULL
 456
 457#define VTD_CONTEXT_ENTRY_NR        (VTD_PAGE_SIZE / sizeof(VTDContextEntry))
 458
 459#define VTD_CTX_ENTRY_LEGACY_SIZE     16
 460#define VTD_CTX_ENTRY_SCALABLE_SIZE   32
 461
 462#define VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK 0xfffff
 463#define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw)  (0x1e0ULL | ~VTD_HAW_MASK(aw))
 464#define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1      0xffffffffffe00000ULL
 465
 466/* PASID Table Related Definitions */
 467#define VTD_PASID_DIR_BASE_ADDR_MASK  (~0xfffULL)
 468#define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL)
 469#define VTD_PASID_DIR_ENTRY_SIZE      8
 470#define VTD_PASID_ENTRY_SIZE          64
 471#define VTD_PASID_DIR_BITS_MASK       (0x3fffULL)
 472#define VTD_PASID_DIR_INDEX(pasid)    (((pasid) >> 6) & VTD_PASID_DIR_BITS_MASK)
 473#define VTD_PASID_DIR_FPD             (1ULL << 1) /* Fault Processing Disable */
 474#define VTD_PASID_TABLE_BITS_MASK     (0x3fULL)
 475#define VTD_PASID_TABLE_INDEX(pasid)  ((pasid) & VTD_PASID_TABLE_BITS_MASK)
 476#define VTD_PASID_ENTRY_FPD           (1ULL << 1) /* Fault Processing Disable */
 477
 478/* PASID Granular Translation Type Mask */
 479#define VTD_SM_PASID_ENTRY_PGTT        (7ULL << 6)
 480#define VTD_SM_PASID_ENTRY_FLT         (1ULL << 6)
 481#define VTD_SM_PASID_ENTRY_SLT         (2ULL << 6)
 482#define VTD_SM_PASID_ENTRY_NESTED      (3ULL << 6)
 483#define VTD_SM_PASID_ENTRY_PT          (4ULL << 6)
 484
 485#define VTD_SM_PASID_ENTRY_AW          7ULL /* Adjusted guest-address-width */
 486#define VTD_SM_PASID_ENTRY_DID(val)    ((val) & VTD_DOMAIN_ID_MASK)
 487
 488/* Second Level Page Translation Pointer*/
 489#define VTD_SM_PASID_ENTRY_SLPTPTR     (~0xfffULL)
 490
 491/* Paging Structure common */
 492#define VTD_SL_PT_PAGE_SIZE_MASK    (1ULL << 7)
 493/* Bits to decide the offset for each level */
 494#define VTD_SL_LEVEL_BITS           9
 495
 496/* Second Level Paging Structure */
 497#define VTD_SL_PML4_LEVEL           4
 498#define VTD_SL_PDP_LEVEL            3
 499#define VTD_SL_PD_LEVEL             2
 500#define VTD_SL_PT_LEVEL             1
 501#define VTD_SL_PT_ENTRY_NR          512
 502
 503/* Masks for Second Level Paging Entry */
 504#define VTD_SL_RW_MASK              3ULL
 505#define VTD_SL_R                    1ULL
 506#define VTD_SL_W                    (1ULL << 1)
 507#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
 508#define VTD_SL_IGN_COM              0xbff0000000000000ULL
 509
 510#endif
 511