1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21#include "qemu/osdep.h"
22#include "hw/sysbus.h"
23#include "qemu/log.h"
24#include "qemu/module.h"
25
26
27#define CACHE_ID 0x410000c8
28
29#define TYPE_ARM_L2X0 "l2x0"
30#define ARM_L2X0(obj) OBJECT_CHECK(L2x0State, (obj), TYPE_ARM_L2X0)
31
32typedef struct L2x0State {
33 SysBusDevice parent_obj;
34
35 MemoryRegion iomem;
36 uint32_t cache_type;
37 uint32_t ctrl;
38 uint32_t aux_ctrl;
39 uint32_t data_ctrl;
40 uint32_t tag_ctrl;
41 uint32_t filter_start;
42 uint32_t filter_end;
43} L2x0State;
44
45static const VMStateDescription vmstate_l2x0 = {
46 .name = "l2x0",
47 .version_id = 1,
48 .minimum_version_id = 1,
49 .fields = (VMStateField[]) {
50 VMSTATE_UINT32(ctrl, L2x0State),
51 VMSTATE_UINT32(aux_ctrl, L2x0State),
52 VMSTATE_UINT32(data_ctrl, L2x0State),
53 VMSTATE_UINT32(tag_ctrl, L2x0State),
54 VMSTATE_UINT32(filter_start, L2x0State),
55 VMSTATE_UINT32(filter_end, L2x0State),
56 VMSTATE_END_OF_LIST()
57 }
58};
59
60
61static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
62 unsigned size)
63{
64 uint32_t cache_data;
65 L2x0State *s = (L2x0State *)opaque;
66 offset &= 0xfff;
67 if (offset >= 0x730 && offset < 0x800) {
68 return 0;
69 }
70 switch (offset) {
71 case 0:
72 return CACHE_ID;
73 case 0x4:
74
75 cache_data = (s->aux_ctrl & (7 << 17)) >> 15;
76 cache_data |= (s->aux_ctrl & (1 << 16)) >> 16;
77 return s->cache_type |= (cache_data << 18) | (cache_data << 6);
78 case 0x100:
79 return s->ctrl;
80 case 0x104:
81 return s->aux_ctrl;
82 case 0x108:
83 return s->tag_ctrl;
84 case 0x10C:
85 return s->data_ctrl;
86 case 0xC00:
87 return s->filter_start;
88 case 0xC04:
89 return s->filter_end;
90 case 0xF40:
91 return 0;
92 case 0xF60:
93 return 0;
94 case 0xF80:
95 return 0;
96 default:
97 qemu_log_mask(LOG_GUEST_ERROR,
98 "l2x0_priv_read: Bad offset %x\n", (int)offset);
99 break;
100 }
101 return 0;
102}
103
104static void l2x0_priv_write(void *opaque, hwaddr offset,
105 uint64_t value, unsigned size)
106{
107 L2x0State *s = (L2x0State *)opaque;
108 offset &= 0xfff;
109 if (offset >= 0x730 && offset < 0x800) {
110
111 return;
112 }
113 switch (offset) {
114 case 0x100:
115 s->ctrl = value & 1;
116 break;
117 case 0x104:
118 s->aux_ctrl = value;
119 break;
120 case 0x108:
121 s->tag_ctrl = value;
122 break;
123 case 0x10C:
124 s->data_ctrl = value;
125 break;
126 case 0xC00:
127 s->filter_start = value;
128 break;
129 case 0xC04:
130 s->filter_end = value;
131 break;
132 case 0xF40:
133 return;
134 case 0xF60:
135 return;
136 case 0xF80:
137 return;
138 default:
139 qemu_log_mask(LOG_GUEST_ERROR,
140 "l2x0_priv_write: Bad offset %x\n", (int)offset);
141 break;
142 }
143}
144
145static void l2x0_priv_reset(DeviceState *dev)
146{
147 L2x0State *s = ARM_L2X0(dev);
148
149 s->ctrl = 0;
150 s->aux_ctrl = 0x02020000;
151 s->tag_ctrl = 0;
152 s->data_ctrl = 0;
153 s->filter_start = 0;
154 s->filter_end = 0;
155}
156
157static const MemoryRegionOps l2x0_mem_ops = {
158 .read = l2x0_priv_read,
159 .write = l2x0_priv_write,
160 .endianness = DEVICE_NATIVE_ENDIAN,
161 };
162
163static void l2x0_priv_init(Object *obj)
164{
165 L2x0State *s = ARM_L2X0(obj);
166 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
167
168 memory_region_init_io(&s->iomem, obj, &l2x0_mem_ops, s,
169 "l2x0_cc", 0x1000);
170 sysbus_init_mmio(dev, &s->iomem);
171}
172
173static Property l2x0_properties[] = {
174 DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100),
175 DEFINE_PROP_END_OF_LIST(),
176};
177
178static void l2x0_class_init(ObjectClass *klass, void *data)
179{
180 DeviceClass *dc = DEVICE_CLASS(klass);
181
182 dc->vmsd = &vmstate_l2x0;
183 dc->props = l2x0_properties;
184 dc->reset = l2x0_priv_reset;
185}
186
187static const TypeInfo l2x0_info = {
188 .name = TYPE_ARM_L2X0,
189 .parent = TYPE_SYS_BUS_DEVICE,
190 .instance_size = sizeof(L2x0State),
191 .instance_init = l2x0_priv_init,
192 .class_init = l2x0_class_init,
193};
194
195static void l2x0_register_types(void)
196{
197 type_register_static(&l2x0_info);
198}
199
200type_init(l2x0_register_types)
201