LXR qemu/hw/net/lance.c

   1/*
   2 * QEMU AMD PC-Net II (Am79C970A) emulation
   3 *
   4 * Copyright (c) 2004 Antony T Curtis
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25/* This software was written to be compatible with the specification:
  26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
  27 * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
  28 */
  29
  30/*
  31 * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
  32 * produced as NCR89C100. See
  33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  34 * and
  35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
  36 */
  37
  38#include "qemu/osdep.h"
  39#include "qemu/module.h"
  40#include "qemu/timer.h"
  41#include "hw/sparc/sparc32_dma.h"
  42#include "hw/net/lance.h"
  43#include "trace.h"
  44#include "sysemu/sysemu.h"
  45
  46
  47static void parent_lance_reset(void *opaque, int irq, int level)
  48{
  49    SysBusPCNetState *d = opaque;
  50    if (level)
  51        pcnet_h_reset(&d->state);
  52}
  53
  54static void lance_mem_write(void *opaque, hwaddr addr,
  55                            uint64_t val, unsigned size)
  56{
  57    SysBusPCNetState *d = opaque;
  58
  59    trace_lance_mem_writew(addr, val & 0xffff);
  60    pcnet_ioport_writew(&d->state, addr, val & 0xffff);
  61}
  62
  63static uint64_t lance_mem_read(void *opaque, hwaddr addr,
  64                               unsigned size)
  65{
  66    SysBusPCNetState *d = opaque;
  67    uint32_t val;
  68
  69    val = pcnet_ioport_readw(&d->state, addr);
  70    trace_lance_mem_readw(addr, val & 0xffff);
  71    return val & 0xffff;
  72}
  73
  74static const MemoryRegionOps lance_mem_ops = {
  75    .read = lance_mem_read,
  76    .write = lance_mem_write,
  77    .endianness = DEVICE_NATIVE_ENDIAN,
  78    .valid = {
  79        .min_access_size = 2,
  80        .max_access_size = 2,
  81    },
  82};
  83
  84static NetClientInfo net_lance_info = {
  85    .type = NET_CLIENT_DRIVER_NIC,
  86    .size = sizeof(NICState),
  87    .receive = pcnet_receive,
  88    .link_status_changed = pcnet_set_link_status,
  89};
  90
  91static const VMStateDescription vmstate_lance = {
  92    .name = "pcnet",
  93    .version_id = 3,
  94    .minimum_version_id = 2,
  95    .fields = (VMStateField[]) {
  96        VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState),
  97        VMSTATE_END_OF_LIST()
  98    }
  99};
 100
 101static void lance_realize(DeviceState *dev, Error **errp)
 102{
 103    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 104    SysBusPCNetState *d = SYSBUS_PCNET(dev);
 105    PCNetState *s = &d->state;
 106
 107    memory_region_init_io(&s->mmio, OBJECT(d), &lance_mem_ops, d,
 108                          "lance-mmio", 4);
 109
 110    qdev_init_gpio_in(dev, parent_lance_reset, 1);
 111
 112    sysbus_init_mmio(sbd, &s->mmio);
 113
 114    sysbus_init_irq(sbd, &s->irq);
 115
 116    s->phys_mem_read = ledma_memory_read;
 117    s->phys_mem_write = ledma_memory_write;
 118    pcnet_common_init(dev, s, &net_lance_info);
 119}
 120
 121static void lance_reset(DeviceState *dev)
 122{
 123    SysBusPCNetState *d = SYSBUS_PCNET(dev);
 124
 125    pcnet_h_reset(&d->state);
 126}
 127
 128static void lance_instance_init(Object *obj)
 129{
 130    SysBusPCNetState *d = SYSBUS_PCNET(obj);
 131    PCNetState *s = &d->state;
 132
 133    device_add_bootindex_property(obj, &s->conf.bootindex,
 134                                  "bootindex", "/ethernet-phy@0",
 135                                  DEVICE(obj), NULL);
 136}
 137
 138static Property lance_properties[] = {
 139    DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque),
 140    DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf),
 141    DEFINE_PROP_END_OF_LIST(),
 142};
 143
 144static void lance_class_init(ObjectClass *klass, void *data)
 145{
 146    DeviceClass *dc = DEVICE_CLASS(klass);
 147
 148    dc->realize = lance_realize;
 149    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 150    dc->fw_name = "ethernet";
 151    dc->reset = lance_reset;
 152    dc->vmsd = &vmstate_lance;
 153    dc->props = lance_properties;
 154    /* Reason: pointer property "dma" */
 155    dc->user_creatable = false;
 156}
 157
 158static const TypeInfo lance_info = {
 159    .name          = TYPE_LANCE,
 160    .parent        = TYPE_SYS_BUS_DEVICE,
 161    .instance_size = sizeof(SysBusPCNetState),
 162    .class_init    = lance_class_init,
 163    .instance_init = lance_instance_init,
 164};
 165
 166static void lance_register_types(void)
 167{
 168    type_register_static(&lance_info);
 169}
 170
 171type_init(lance_register_types)
 172