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21#include "qemu/osdep.h"
22#include "hw/sysbus.h"
23#include "qemu/module.h"
24#include "target/riscv/cpu.h"
25#include "hw/riscv/sifive_prci.h"
26
27static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
28{
29 SiFivePRCIState *s = opaque;
30 switch (addr) {
31 case SIFIVE_PRCI_HFROSCCFG:
32 return s->hfrosccfg;
33 case SIFIVE_PRCI_HFXOSCCFG:
34 return s->hfxosccfg;
35 case SIFIVE_PRCI_PLLCFG:
36 return s->pllcfg;
37 case SIFIVE_PRCI_PLLOUTDIV:
38 return s->plloutdiv;
39 }
40 hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);
41 return 0;
42}
43
44static void sifive_prci_write(void *opaque, hwaddr addr,
45 uint64_t val64, unsigned int size)
46{
47 SiFivePRCIState *s = opaque;
48 switch (addr) {
49 case SIFIVE_PRCI_HFROSCCFG:
50 s->hfrosccfg = (uint32_t) val64;
51
52 s->hfrosccfg |= SIFIVE_PRCI_HFROSCCFG_RDY;
53 break;
54 case SIFIVE_PRCI_HFXOSCCFG:
55 s->hfxosccfg = (uint32_t) val64;
56
57 s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY;
58 break;
59 case SIFIVE_PRCI_PLLCFG:
60 s->pllcfg = (uint32_t) val64;
61
62 s->pllcfg |= SIFIVE_PRCI_PLLCFG_LOCK;
63 break;
64 case SIFIVE_PRCI_PLLOUTDIV:
65 s->plloutdiv = (uint32_t) val64;
66 break;
67 default:
68 hw_error("%s: bad write: addr=0x%x v=0x%x\n",
69 __func__, (int)addr, (int)val64);
70 }
71}
72
73static const MemoryRegionOps sifive_prci_ops = {
74 .read = sifive_prci_read,
75 .write = sifive_prci_write,
76 .endianness = DEVICE_NATIVE_ENDIAN,
77 .valid = {
78 .min_access_size = 4,
79 .max_access_size = 4
80 }
81};
82
83static void sifive_prci_init(Object *obj)
84{
85 SiFivePRCIState *s = SIFIVE_PRCI(obj);
86
87 memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s,
88 TYPE_SIFIVE_PRCI, 0x8000);
89 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
90
91 s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
92 s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
93 s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS |
94 SIFIVE_PRCI_PLLCFG_LOCK);
95 s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1;
96
97}
98
99static const TypeInfo sifive_prci_info = {
100 .name = TYPE_SIFIVE_PRCI,
101 .parent = TYPE_SYS_BUS_DEVICE,
102 .instance_size = sizeof(SiFivePRCIState),
103 .instance_init = sifive_prci_init,
104};
105
106static void sifive_prci_register_types(void)
107{
108 type_register_static(&sifive_prci_info);
109}
110
111type_init(sifive_prci_register_types)
112
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115
116
117DeviceState *sifive_prci_create(hwaddr addr)
118{
119 DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI);
120 qdev_init_nofail(dev);
121 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
122 return dev;
123}
124