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25#include "qemu/osdep.h"
26#include "hw/timer/stm32f2xx_timer.h"
27#include "qemu/log.h"
28#include "qemu/module.h"
29
30#ifndef STM_TIMER_ERR_DEBUG
31#define STM_TIMER_ERR_DEBUG 0
32#endif
33
34#define DB_PRINT_L(lvl, fmt, args...) do { \
35 if (STM_TIMER_ERR_DEBUG >= lvl) { \
36 qemu_log("%s: " fmt, __func__, ## args); \
37 } \
38} while (0)
39
40#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
41
42static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now);
43
44static void stm32f2xx_timer_interrupt(void *opaque)
45{
46 STM32F2XXTimerState *s = opaque;
47
48 DB_PRINT("Interrupt\n");
49
50 if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) {
51 s->tim_sr |= 1;
52 qemu_irq_pulse(s->irq);
53 stm32f2xx_timer_set_alarm(s, s->hit_time);
54 }
55
56 if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) &&
57 !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) &&
58 s->tim_ccmr1 & TIM_CCMR1_OC2PE &&
59 s->tim_ccer & TIM_CCER_CC2E) {
60
61 DB_PRINT("PWM2 Duty Cycle: %d%%\n",
62 s->tim_ccr2 / (100 * (s->tim_psc + 1)));
63 }
64}
65
66static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)
67{
68 return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1);
69}
70
71static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now)
72{
73 uint64_t ticks;
74 int64_t now_ticks;
75
76 if (s->tim_arr == 0) {
77 return;
78 }
79
80 DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1);
81
82 now_ticks = stm32f2xx_ns_to_ticks(s, now);
83 ticks = s->tim_arr - (now_ticks - s->tick_offset);
84
85 DB_PRINT("Alarm set in %d ticks\n", (int) ticks);
86
87 s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1),
88 1000000000ULL, s->freq_hz);
89
90 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time);
91 DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time);
92}
93
94static void stm32f2xx_timer_reset(DeviceState *dev)
95{
96 STM32F2XXTimerState *s = STM32F2XXTIMER(dev);
97 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
98
99 s->tim_cr1 = 0;
100 s->tim_cr2 = 0;
101 s->tim_smcr = 0;
102 s->tim_dier = 0;
103 s->tim_sr = 0;
104 s->tim_egr = 0;
105 s->tim_ccmr1 = 0;
106 s->tim_ccmr2 = 0;
107 s->tim_ccer = 0;
108 s->tim_psc = 0;
109 s->tim_arr = 0;
110 s->tim_ccr1 = 0;
111 s->tim_ccr2 = 0;
112 s->tim_ccr3 = 0;
113 s->tim_ccr4 = 0;
114 s->tim_dcr = 0;
115 s->tim_dmar = 0;
116 s->tim_or = 0;
117
118 s->tick_offset = stm32f2xx_ns_to_ticks(s, now);
119}
120
121static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset,
122 unsigned size)
123{
124 STM32F2XXTimerState *s = opaque;
125
126 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset);
127
128 switch (offset) {
129 case TIM_CR1:
130 return s->tim_cr1;
131 case TIM_CR2:
132 return s->tim_cr2;
133 case TIM_SMCR:
134 return s->tim_smcr;
135 case TIM_DIER:
136 return s->tim_dier;
137 case TIM_SR:
138 return s->tim_sr;
139 case TIM_EGR:
140 return s->tim_egr;
141 case TIM_CCMR1:
142 return s->tim_ccmr1;
143 case TIM_CCMR2:
144 return s->tim_ccmr2;
145 case TIM_CCER:
146 return s->tim_ccer;
147 case TIM_CNT:
148 return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) -
149 s->tick_offset;
150 case TIM_PSC:
151 return s->tim_psc;
152 case TIM_ARR:
153 return s->tim_arr;
154 case TIM_CCR1:
155 return s->tim_ccr1;
156 case TIM_CCR2:
157 return s->tim_ccr2;
158 case TIM_CCR3:
159 return s->tim_ccr3;
160 case TIM_CCR4:
161 return s->tim_ccr4;
162 case TIM_DCR:
163 return s->tim_dcr;
164 case TIM_DMAR:
165 return s->tim_dmar;
166 case TIM_OR:
167 return s->tim_or;
168 default:
169 qemu_log_mask(LOG_GUEST_ERROR,
170 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
171 }
172
173 return 0;
174}
175
176static void stm32f2xx_timer_write(void *opaque, hwaddr offset,
177 uint64_t val64, unsigned size)
178{
179 STM32F2XXTimerState *s = opaque;
180 uint32_t value = val64;
181 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
182 uint32_t timer_val = 0;
183
184 DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset);
185
186 switch (offset) {
187 case TIM_CR1:
188 s->tim_cr1 = value;
189 return;
190 case TIM_CR2:
191 s->tim_cr2 = value;
192 return;
193 case TIM_SMCR:
194 s->tim_smcr = value;
195 return;
196 case TIM_DIER:
197 s->tim_dier = value;
198 return;
199 case TIM_SR:
200
201 s->tim_sr &= value;
202 return;
203 case TIM_EGR:
204 s->tim_egr = value;
205 if (s->tim_egr & TIM_EGR_UG) {
206 timer_val = 0;
207 break;
208 }
209 return;
210 case TIM_CCMR1:
211 s->tim_ccmr1 = value;
212 return;
213 case TIM_CCMR2:
214 s->tim_ccmr2 = value;
215 return;
216 case TIM_CCER:
217 s->tim_ccer = value;
218 return;
219 case TIM_PSC:
220 timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset;
221 s->tim_psc = value & 0xFFFF;
222 value = timer_val;
223 break;
224 case TIM_CNT:
225 timer_val = value;
226 break;
227 case TIM_ARR:
228 s->tim_arr = value;
229 stm32f2xx_timer_set_alarm(s, now);
230 return;
231 case TIM_CCR1:
232 s->tim_ccr1 = value;
233 return;
234 case TIM_CCR2:
235 s->tim_ccr2 = value;
236 return;
237 case TIM_CCR3:
238 s->tim_ccr3 = value;
239 return;
240 case TIM_CCR4:
241 s->tim_ccr4 = value;
242 return;
243 case TIM_DCR:
244 s->tim_dcr = value;
245 return;
246 case TIM_DMAR:
247 s->tim_dmar = value;
248 return;
249 case TIM_OR:
250 s->tim_or = value;
251 return;
252 default:
253 qemu_log_mask(LOG_GUEST_ERROR,
254 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
255 return;
256 }
257
258
259
260
261 s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val;
262 stm32f2xx_timer_set_alarm(s, now);
263}
264
265static const MemoryRegionOps stm32f2xx_timer_ops = {
266 .read = stm32f2xx_timer_read,
267 .write = stm32f2xx_timer_write,
268 .endianness = DEVICE_NATIVE_ENDIAN,
269};
270
271static const VMStateDescription vmstate_stm32f2xx_timer = {
272 .name = TYPE_STM32F2XX_TIMER,
273 .version_id = 1,
274 .minimum_version_id = 1,
275 .fields = (VMStateField[]) {
276 VMSTATE_INT64(tick_offset, STM32F2XXTimerState),
277 VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState),
278 VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState),
279 VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState),
280 VMSTATE_UINT32(tim_dier, STM32F2XXTimerState),
281 VMSTATE_UINT32(tim_sr, STM32F2XXTimerState),
282 VMSTATE_UINT32(tim_egr, STM32F2XXTimerState),
283 VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState),
284 VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState),
285 VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState),
286 VMSTATE_UINT32(tim_psc, STM32F2XXTimerState),
287 VMSTATE_UINT32(tim_arr, STM32F2XXTimerState),
288 VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState),
289 VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState),
290 VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState),
291 VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState),
292 VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState),
293 VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState),
294 VMSTATE_UINT32(tim_or, STM32F2XXTimerState),
295 VMSTATE_END_OF_LIST()
296 }
297};
298
299static Property stm32f2xx_timer_properties[] = {
300 DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState,
301 freq_hz, 1000000000),
302 DEFINE_PROP_END_OF_LIST(),
303};
304
305static void stm32f2xx_timer_init(Object *obj)
306{
307 STM32F2XXTimerState *s = STM32F2XXTIMER(obj);
308
309 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
310
311 memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
312 "stm32f2xx_timer", 0x400);
313 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
314
315 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
316}
317
318static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data)
319{
320 DeviceClass *dc = DEVICE_CLASS(klass);
321
322 dc->reset = stm32f2xx_timer_reset;
323 dc->props = stm32f2xx_timer_properties;
324 dc->vmsd = &vmstate_stm32f2xx_timer;
325}
326
327static const TypeInfo stm32f2xx_timer_info = {
328 .name = TYPE_STM32F2XX_TIMER,
329 .parent = TYPE_SYS_BUS_DEVICE,
330 .instance_size = sizeof(STM32F2XXTimerState),
331 .instance_init = stm32f2xx_timer_init,
332 .class_init = stm32f2xx_timer_class_init,
333};
334
335static void stm32f2xx_timer_register_types(void)
336{
337 type_register_static(&stm32f2xx_timer_info);
338}
339
340type_init(stm32f2xx_timer_register_types)
341
