LXR qemu/hw/timer/xlnx-zynqmp-rtc.c

   1/*
   2 * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
   3 *
   4 * Copyright (c) 2017 Xilinx Inc.
   5 *
   6 * Written-by: Alistair Francis <alistair.francis@xilinx.com>
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a copy
   9 * of this software and associated documentation files (the "Software"), to deal
  10 * in the Software without restriction, including without limitation the rights
  11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 * copies of the Software, and to permit persons to whom the Software is
  13 * furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice shall be included in
  16 * all copies or substantial portions of the Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 */
  26
  27#include "qemu/osdep.h"
  28#include "qemu-common.h"
  29#include "hw/sysbus.h"
  30#include "hw/register.h"
  31#include "qemu/bitops.h"
  32#include "qemu/log.h"
  33#include "qemu/module.h"
  34#include "hw/ptimer.h"
  35#include "qemu/cutils.h"
  36#include "sysemu/sysemu.h"
  37#include "trace.h"
  38#include "hw/timer/xlnx-zynqmp-rtc.h"
  39
  40#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG
  41#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0
  42#endif
  43
  44static void rtc_int_update_irq(XlnxZynqMPRTC *s)
  45{
  46    bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK];
  47    qemu_set_irq(s->irq_rtc_int, pending);
  48}
  49
  50static void addr_error_int_update_irq(XlnxZynqMPRTC *s)
  51{
  52    bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK];
  53    qemu_set_irq(s->irq_addr_error_int, pending);
  54}
  55
  56static uint32_t rtc_get_count(XlnxZynqMPRTC *s)
  57{
  58    int64_t now = qemu_clock_get_ns(rtc_clock);
  59    return s->tick_offset + now / NANOSECONDS_PER_SECOND;
  60}
  61
  62static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64)
  63{
  64    XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  65
  66    return rtc_get_count(s);
  67}
  68
  69static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64)
  70{
  71    XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  72    rtc_int_update_irq(s);
  73}
  74
  75static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64)
  76{
  77    XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  78
  79    s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64;
  80    rtc_int_update_irq(s);
  81    return 0;
  82}
  83
  84static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64)
  85{
  86    XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  87
  88    s->regs[R_RTC_INT_MASK] |= (uint32_t) val64;
  89    rtc_int_update_irq(s);
  90    return 0;
  91}
  92
  93static void addr_error_postw(RegisterInfo *reg, uint64_t val64)
  94{
  95    XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  96    addr_error_int_update_irq(s);
  97}
  98
  99static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
 100{
 101    XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
 102
 103    s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64;
 104    addr_error_int_update_irq(s);
 105    return 0;
 106}
 107
 108static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
 109{
 110    XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
 111
 112    s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64;
 113    addr_error_int_update_irq(s);
 114    return 0;
 115}
 116
 117static const RegisterAccessInfo rtc_regs_info[] = {
 118    {   .name = "SET_TIME_WRITE",  .addr = A_SET_TIME_WRITE,
 119        .unimp = MAKE_64BIT_MASK(0, 32),
 120    },{ .name = "SET_TIME_READ",  .addr = A_SET_TIME_READ,
 121        .ro = 0xffffffff,
 122        .post_read = current_time_postr,
 123    },{ .name = "CALIB_WRITE",  .addr = A_CALIB_WRITE,
 124        .unimp = MAKE_64BIT_MASK(0, 32),
 125    },{ .name = "CALIB_READ",  .addr = A_CALIB_READ,
 126        .ro = 0x1fffff,
 127    },{ .name = "CURRENT_TIME",  .addr = A_CURRENT_TIME,
 128        .ro = 0xffffffff,
 129        .post_read = current_time_postr,
 130    },{ .name = "CURRENT_TICK",  .addr = A_CURRENT_TICK,
 131        .ro = 0xffff,
 132    },{ .name = "ALARM",  .addr = A_ALARM,
 133    },{ .name = "RTC_INT_STATUS",  .addr = A_RTC_INT_STATUS,
 134        .w1c = 0x3,
 135        .post_write = rtc_int_status_postw,
 136    },{ .name = "RTC_INT_MASK",  .addr = A_RTC_INT_MASK,
 137        .reset = 0x3,
 138        .ro = 0x3,
 139    },{ .name = "RTC_INT_EN",  .addr = A_RTC_INT_EN,
 140        .pre_write = rtc_int_en_prew,
 141    },{ .name = "RTC_INT_DIS",  .addr = A_RTC_INT_DIS,
 142        .pre_write = rtc_int_dis_prew,
 143    },{ .name = "ADDR_ERROR",  .addr = A_ADDR_ERROR,
 144        .w1c = 0x1,
 145        .post_write = addr_error_postw,
 146    },{ .name = "ADDR_ERROR_INT_MASK",  .addr = A_ADDR_ERROR_INT_MASK,
 147        .reset = 0x1,
 148        .ro = 0x1,
 149    },{ .name = "ADDR_ERROR_INT_EN",  .addr = A_ADDR_ERROR_INT_EN,
 150        .pre_write = addr_error_int_en_prew,
 151    },{ .name = "ADDR_ERROR_INT_DIS",  .addr = A_ADDR_ERROR_INT_DIS,
 152        .pre_write = addr_error_int_dis_prew,
 153    },{ .name = "CONTROL",  .addr = A_CONTROL,
 154        .reset = 0x1000000,
 155        .rsvd = 0x70fffffe,
 156    },{ .name = "SAFETY_CHK",  .addr = A_SAFETY_CHK,
 157    }
 158};
 159
 160static void rtc_reset(DeviceState *dev)
 161{
 162    XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev);
 163    unsigned int i;
 164
 165    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
 166        register_reset(&s->regs_info[i]);
 167    }
 168
 169    rtc_int_update_irq(s);
 170    addr_error_int_update_irq(s);
 171}
 172
 173static const MemoryRegionOps rtc_ops = {
 174    .read = register_read_memory,
 175    .write = register_write_memory,
 176    .endianness = DEVICE_LITTLE_ENDIAN,
 177    .valid = {
 178        .min_access_size = 4,
 179        .max_access_size = 4,
 180    },
 181};
 182
 183static void rtc_init(Object *obj)
 184{
 185    XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj);
 186    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 187    RegisterInfoArray *reg_array;
 188    struct tm current_tm;
 189
 190    memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC,
 191                       XLNX_ZYNQMP_RTC_R_MAX * 4);
 192    reg_array =
 193        register_init_block32(DEVICE(obj), rtc_regs_info,
 194                              ARRAY_SIZE(rtc_regs_info),
 195                              s->regs_info, s->regs,
 196                              &rtc_ops,
 197                              XLNX_ZYNQMP_RTC_ERR_DEBUG,
 198                              XLNX_ZYNQMP_RTC_R_MAX * 4);
 199    memory_region_add_subregion(&s->iomem,
 200                                0x0,
 201                                &reg_array->mem);
 202    sysbus_init_mmio(sbd, &s->iomem);
 203    sysbus_init_irq(sbd, &s->irq_rtc_int);
 204    sysbus_init_irq(sbd, &s->irq_addr_error_int);
 205
 206    qemu_get_timedate(&current_tm, 0);
 207    s->tick_offset = mktimegm(&current_tm) -
 208        qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 209
 210    trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon,
 211                                  current_tm.tm_mday, current_tm.tm_hour,
 212                                  current_tm.tm_min, current_tm.tm_sec);
 213}
 214
 215static int rtc_pre_save(void *opaque)
 216{
 217    XlnxZynqMPRTC *s = opaque;
 218    int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 219
 220    /* Add the time at migration */
 221    s->tick_offset = s->tick_offset + now;
 222
 223    return 0;
 224}
 225
 226static int rtc_post_load(void *opaque, int version_id)
 227{
 228    XlnxZynqMPRTC *s = opaque;
 229    int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 230
 231    /* Subtract the time after migration. This combined with the pre_save
 232     * action results in us having subtracted the time that the guest was
 233     * stopped to the offset.
 234     */
 235    s->tick_offset = s->tick_offset - now;
 236
 237    return 0;
 238}
 239
 240static const VMStateDescription vmstate_rtc = {
 241    .name = TYPE_XLNX_ZYNQMP_RTC,
 242    .version_id = 1,
 243    .minimum_version_id = 1,
 244    .pre_save = rtc_pre_save,
 245    .post_load = rtc_post_load,
 246    .fields = (VMStateField[]) {
 247        VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX),
 248        VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC),
 249        VMSTATE_END_OF_LIST(),
 250    }
 251};
 252
 253static void rtc_class_init(ObjectClass *klass, void *data)
 254{
 255    DeviceClass *dc = DEVICE_CLASS(klass);
 256
 257    dc->reset = rtc_reset;
 258    dc->vmsd = &vmstate_rtc;
 259}
 260
 261static const TypeInfo rtc_info = {
 262    .name          = TYPE_XLNX_ZYNQMP_RTC,
 263    .parent        = TYPE_SYS_BUS_DEVICE,
 264    .instance_size = sizeof(XlnxZynqMPRTC),
 265    .class_init    = rtc_class_init,
 266    .instance_init = rtc_init,
 267};
 268
 269static void rtc_register_types(void)
 270{
 271    type_register_static(&rtc_info);
 272}
 273
 274type_init(rtc_register_types)
 275