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20#ifndef SH4_CPU_H
21#define SH4_CPU_H
22
23#include "cpu-qom.h"
24#include "exec/cpu-defs.h"
25
26#define ALIGNED_ONLY
27
28
29#define SH_CPU_SH7750 (1 << 0)
30#define SH_CPU_SH7750S (1 << 1)
31#define SH_CPU_SH7750R (1 << 2)
32#define SH_CPU_SH7751 (1 << 3)
33#define SH_CPU_SH7751R (1 << 4)
34#define SH_CPU_SH7785 (1 << 5)
35#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
36#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
37
38#define SR_MD 30
39#define SR_RB 29
40#define SR_BL 28
41#define SR_FD 15
42#define SR_M 9
43#define SR_Q 8
44#define SR_I3 7
45#define SR_I2 6
46#define SR_I1 5
47#define SR_I0 4
48#define SR_S 1
49#define SR_T 0
50
51#define FPSCR_MASK (0x003fffff)
52#define FPSCR_FR (1 << 21)
53#define FPSCR_SZ (1 << 20)
54#define FPSCR_PR (1 << 19)
55#define FPSCR_DN (1 << 18)
56#define FPSCR_CAUSE_MASK (0x3f << 12)
57#define FPSCR_CAUSE_SHIFT (12)
58#define FPSCR_CAUSE_E (1 << 17)
59#define FPSCR_CAUSE_V (1 << 16)
60#define FPSCR_CAUSE_Z (1 << 15)
61#define FPSCR_CAUSE_O (1 << 14)
62#define FPSCR_CAUSE_U (1 << 13)
63#define FPSCR_CAUSE_I (1 << 12)
64#define FPSCR_ENABLE_MASK (0x1f << 7)
65#define FPSCR_ENABLE_SHIFT (7)
66#define FPSCR_ENABLE_V (1 << 11)
67#define FPSCR_ENABLE_Z (1 << 10)
68#define FPSCR_ENABLE_O (1 << 9)
69#define FPSCR_ENABLE_U (1 << 8)
70#define FPSCR_ENABLE_I (1 << 7)
71#define FPSCR_FLAG_MASK (0x1f << 2)
72#define FPSCR_FLAG_SHIFT (2)
73#define FPSCR_FLAG_V (1 << 6)
74#define FPSCR_FLAG_Z (1 << 5)
75#define FPSCR_FLAG_O (1 << 4)
76#define FPSCR_FLAG_U (1 << 3)
77#define FPSCR_FLAG_I (1 << 2)
78#define FPSCR_RM_MASK (0x03 << 0)
79#define FPSCR_RM_NEAREST (0 << 0)
80#define FPSCR_RM_ZERO (1 << 0)
81
82#define DELAY_SLOT_MASK 0x7
83#define DELAY_SLOT (1 << 0)
84#define DELAY_SLOT_CONDITIONAL (1 << 1)
85#define DELAY_SLOT_RTE (1 << 2)
86
87#define TB_FLAG_PENDING_MOVCA (1 << 3)
88
89#define GUSA_SHIFT 4
90#ifdef CONFIG_USER_ONLY
91#define GUSA_EXCLUSIVE (1 << 12)
92#define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
93#else
94
95
96#define GUSA_EXCLUSIVE 0
97#define GUSA_MASK 0
98#endif
99
100#define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK)
101
102typedef struct tlb_t {
103 uint32_t vpn;
104 uint32_t ppn;
105 uint32_t size;
106 uint8_t asid;
107 uint8_t v:1;
108 uint8_t sz:2;
109 uint8_t sh:1;
110 uint8_t c:1;
111 uint8_t pr:2;
112 uint8_t d:1;
113 uint8_t wt:1;
114 uint8_t sa:3;
115 uint8_t tc:1;
116} tlb_t;
117
118#define UTLB_SIZE 64
119#define ITLB_SIZE 4
120
121#define TARGET_INSN_START_EXTRA_WORDS 1
122
123enum sh_features {
124 SH_FEATURE_SH4A = 1,
125 SH_FEATURE_BCR3_AND_BCR4 = 2,
126};
127
128typedef struct memory_content {
129 uint32_t address;
130 uint32_t value;
131 struct memory_content *next;
132} memory_content;
133
134typedef struct CPUSH4State {
135 uint32_t flags;
136 uint32_t gregs[24];
137 float32 fregs[32];
138 uint32_t sr;
139 uint32_t sr_m;
140 uint32_t sr_q;
141 uint32_t sr_t;
142 uint32_t ssr;
143 uint32_t spc;
144 uint32_t gbr;
145 uint32_t vbr;
146 uint32_t sgr;
147 uint32_t dbr;
148 uint32_t pc;
149 uint32_t delayed_pc;
150 uint32_t delayed_cond;
151 uint32_t mach;
152 uint32_t macl;
153 uint32_t pr;
154 uint32_t fpscr;
155 uint32_t fpul;
156
157
158 float_status fp_status;
159
160
161 uint32_t mmucr;
162 uint32_t pteh;
163 uint32_t ptel;
164 uint32_t ptea;
165 uint32_t ttb;
166 uint32_t tea;
167 uint32_t tra;
168 uint32_t expevt;
169 uint32_t intevt;
170
171 tlb_t itlb[ITLB_SIZE];
172 tlb_t utlb[UTLB_SIZE];
173
174
175 uint32_t lock_addr;
176 uint32_t lock_value;
177
178
179 struct {} end_reset_fields;
180
181
182 int id;
183
184
185 uint32_t features;
186
187 void *intc_handle;
188 int in_sleep;
189 memory_content *movcal_backup;
190 memory_content **movcal_backup_tail;
191} CPUSH4State;
192
193
194
195
196
197
198
199struct SuperHCPU {
200
201 CPUState parent_obj;
202
203
204 CPUNegativeOffsetState neg;
205 CPUSH4State env;
206};
207
208
209void superh_cpu_do_interrupt(CPUState *cpu);
210bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
211void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
212hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
213int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
214int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
215void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
216 MMUAccessType access_type,
217 int mmu_idx, uintptr_t retaddr);
218
219void sh4_translate_init(void);
220int cpu_sh4_signal_handler(int host_signum, void *pinfo,
221 void *puc);
222bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
223 MMUAccessType access_type, int mmu_idx,
224 bool probe, uintptr_t retaddr);
225
226void sh4_cpu_list(void);
227#if !defined(CONFIG_USER_ONLY)
228void cpu_sh4_invalidate_tlb(CPUSH4State *s);
229uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
230 hwaddr addr);
231void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
232 uint32_t mem_value);
233uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
234 hwaddr addr);
235void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
236 uint32_t mem_value);
237uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
238 hwaddr addr);
239void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
240 uint32_t mem_value);
241uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
242 hwaddr addr);
243void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
244 uint32_t mem_value);
245#endif
246
247int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
248
249void cpu_load_tlb(CPUSH4State * env);
250
251#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
252#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
253#define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
254
255#define cpu_signal_handler cpu_sh4_signal_handler
256#define cpu_list sh4_cpu_list
257
258
259#define MMU_MODE0_SUFFIX _kernel
260#define MMU_MODE1_SUFFIX _user
261#define MMU_USER_IDX 1
262static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
263{
264
265
266 if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
267 return 0;
268 } else {
269 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
270 }
271}
272
273typedef CPUSH4State CPUArchState;
274typedef SuperHCPU ArchCPU;
275
276#include "exec/cpu-all.h"
277
278
279enum {
280
281 ACCESS_PRIV = 0x01,
282
283 ACCESS_WRITE = 0x02,
284
285 ACCESS_CODE = 0x10,
286 ACCESS_INT = 0x20
287};
288
289
290#define MMUCR 0x1F000010
291#define MMUCR_AT (1<<0)
292#define MMUCR_TI (1<<2)
293#define MMUCR_SV (1<<8)
294#define MMUCR_URC_BITS (6)
295#define MMUCR_URC_OFFSET (10)
296#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
297#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
298static inline int cpu_mmucr_urc (uint32_t mmucr)
299{
300 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
301}
302
303
304#define PTEH_ASID_BITS (8)
305#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
306#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
307#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
308#define PTEH_VPN_BITS (22)
309#define PTEH_VPN_OFFSET (10)
310#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
311#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
312static inline int cpu_pteh_vpn (uint32_t pteh)
313{
314 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
315}
316
317
318#define PTEL_V (1 << 8)
319#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
320#define PTEL_C (1 << 3)
321#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
322#define PTEL_D (1 << 2)
323#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
324#define PTEL_SH (1 << 1)
325#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
326#define PTEL_WT (1 << 0)
327#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
328
329#define PTEL_SZ_HIGH_OFFSET (7)
330#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
331#define PTEL_SZ_LOW_OFFSET (4)
332#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
333static inline int cpu_ptel_sz (uint32_t ptel)
334{
335 int sz;
336 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
337 sz <<= 1;
338 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
339 return sz;
340}
341
342#define PTEL_PPN_BITS (19)
343#define PTEL_PPN_OFFSET (10)
344#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
345#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
346static inline int cpu_ptel_ppn (uint32_t ptel)
347{
348 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
349}
350
351#define PTEL_PR_BITS (2)
352#define PTEL_PR_OFFSET (5)
353#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
354#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
355static inline int cpu_ptel_pr (uint32_t ptel)
356{
357 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
358}
359
360
361#define PTEA_SA_BITS (3)
362#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
363#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
364#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
365#define PTEA_TC (1 << 3)
366#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
367
368static inline target_ulong cpu_read_sr(CPUSH4State *env)
369{
370 return env->sr | (env->sr_m << SR_M) |
371 (env->sr_q << SR_Q) |
372 (env->sr_t << SR_T);
373}
374
375static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
376{
377 env->sr_m = (sr >> SR_M) & 1;
378 env->sr_q = (sr >> SR_Q) & 1;
379 env->sr_t = (sr >> SR_T) & 1;
380 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
381}
382
383static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
384 target_ulong *cs_base, uint32_t *flags)
385{
386 *pc = env->pc;
387
388 *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
389 *flags = env->flags
390 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))
391 | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))
392 | (env->sr & (1u << SR_FD))
393 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0);
394}
395
396#endif
397