qemu/target/sparc/cpu.h
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   1#ifndef SPARC_CPU_H
   2#define SPARC_CPU_H
   3
   4#include "qemu/bswap.h"
   5#include "cpu-qom.h"
   6#include "exec/cpu-defs.h"
   7
   8#define ALIGNED_ONLY
   9
  10#if !defined(TARGET_SPARC64)
  11#define TARGET_DPREGS 16
  12#else
  13#define TARGET_DPREGS 32
  14#endif
  15
  16/*#define EXCP_INTERRUPT 0x100*/
  17
  18/* trap definitions */
  19#ifndef TARGET_SPARC64
  20#define TT_TFAULT   0x01
  21#define TT_ILL_INSN 0x02
  22#define TT_PRIV_INSN 0x03
  23#define TT_NFPU_INSN 0x04
  24#define TT_WIN_OVF  0x05
  25#define TT_WIN_UNF  0x06
  26#define TT_UNALIGNED 0x07
  27#define TT_FP_EXCP  0x08
  28#define TT_DFAULT   0x09
  29#define TT_TOVF     0x0a
  30#define TT_EXTINT   0x10
  31#define TT_CODE_ACCESS 0x21
  32#define TT_UNIMP_FLUSH 0x25
  33#define TT_DATA_ACCESS 0x29
  34#define TT_DIV_ZERO 0x2a
  35#define TT_NCP_INSN 0x24
  36#define TT_TRAP     0x80
  37#else
  38#define TT_POWER_ON_RESET 0x01
  39#define TT_TFAULT   0x08
  40#define TT_CODE_ACCESS 0x0a
  41#define TT_ILL_INSN 0x10
  42#define TT_UNIMP_FLUSH TT_ILL_INSN
  43#define TT_PRIV_INSN 0x11
  44#define TT_NFPU_INSN 0x20
  45#define TT_FP_EXCP  0x21
  46#define TT_TOVF     0x23
  47#define TT_CLRWIN   0x24
  48#define TT_DIV_ZERO 0x28
  49#define TT_DFAULT   0x30
  50#define TT_DATA_ACCESS 0x32
  51#define TT_UNALIGNED 0x34
  52#define TT_PRIV_ACT 0x37
  53#define TT_INSN_REAL_TRANSLATION_MISS 0x3e
  54#define TT_DATA_REAL_TRANSLATION_MISS 0x3f
  55#define TT_EXTINT   0x40
  56#define TT_IVEC     0x60
  57#define TT_TMISS    0x64
  58#define TT_DMISS    0x68
  59#define TT_DPROT    0x6c
  60#define TT_SPILL    0x80
  61#define TT_FILL     0xc0
  62#define TT_WOTHER   (1 << 5)
  63#define TT_TRAP     0x100
  64#define TT_HTRAP    0x180
  65#endif
  66
  67#define PSR_NEG_SHIFT 23
  68#define PSR_NEG   (1 << PSR_NEG_SHIFT)
  69#define PSR_ZERO_SHIFT 22
  70#define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
  71#define PSR_OVF_SHIFT 21
  72#define PSR_OVF   (1 << PSR_OVF_SHIFT)
  73#define PSR_CARRY_SHIFT 20
  74#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
  75#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
  76#if !defined(TARGET_SPARC64)
  77#define PSR_EF    (1<<12)
  78#define PSR_PIL   0xf00
  79#define PSR_S     (1<<7)
  80#define PSR_PS    (1<<6)
  81#define PSR_ET    (1<<5)
  82#define PSR_CWP   0x1f
  83#endif
  84
  85#define CC_SRC (env->cc_src)
  86#define CC_SRC2 (env->cc_src2)
  87#define CC_DST (env->cc_dst)
  88#define CC_OP  (env->cc_op)
  89
  90/* Even though lazy evaluation of CPU condition codes tends to be less
  91 * important on RISC systems where condition codes are only updated
  92 * when explicitly requested, SPARC uses it to update 32-bit and 64-bit
  93 * condition codes.
  94 */
  95enum {
  96    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
  97    CC_OP_FLAGS,   /* all cc are back in status register */
  98    CC_OP_DIV,     /* modify N, Z and V, C = 0*/
  99    CC_OP_ADD,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 100    CC_OP_ADDX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 101    CC_OP_TADD,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 102    CC_OP_TADDTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 103    CC_OP_SUB,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 104    CC_OP_SUBX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 105    CC_OP_TSUB,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 106    CC_OP_TSUBTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 107    CC_OP_LOGIC,   /* modify N and Z, C = V = 0, CC_DST = res */
 108    CC_OP_NB,
 109};
 110
 111/* Trap base register */
 112#define TBR_BASE_MASK 0xfffff000
 113
 114#if defined(TARGET_SPARC64)
 115#define PS_TCT   (1<<12) /* UA2007, impl.dep. trap on control transfer */
 116#define PS_IG    (1<<11) /* v9, zero on UA2007 */
 117#define PS_MG    (1<<10) /* v9, zero on UA2007 */
 118#define PS_CLE   (1<<9) /* UA2007 */
 119#define PS_TLE   (1<<8) /* UA2007 */
 120#define PS_RMO   (1<<7)
 121#define PS_RED   (1<<5) /* v9, zero on UA2007 */
 122#define PS_PEF   (1<<4) /* enable fpu */
 123#define PS_AM    (1<<3) /* address mask */
 124#define PS_PRIV  (1<<2)
 125#define PS_IE    (1<<1)
 126#define PS_AG    (1<<0) /* v9, zero on UA2007 */
 127
 128#define FPRS_FEF (1<<2)
 129
 130#define HS_PRIV  (1<<2)
 131#endif
 132
 133/* Fcc */
 134#define FSR_RD1        (1ULL << 31)
 135#define FSR_RD0        (1ULL << 30)
 136#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
 137#define FSR_RD_NEAREST 0
 138#define FSR_RD_ZERO    FSR_RD0
 139#define FSR_RD_POS     FSR_RD1
 140#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
 141
 142#define FSR_NVM   (1ULL << 27)
 143#define FSR_OFM   (1ULL << 26)
 144#define FSR_UFM   (1ULL << 25)
 145#define FSR_DZM   (1ULL << 24)
 146#define FSR_NXM   (1ULL << 23)
 147#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
 148
 149#define FSR_NVA   (1ULL << 9)
 150#define FSR_OFA   (1ULL << 8)
 151#define FSR_UFA   (1ULL << 7)
 152#define FSR_DZA   (1ULL << 6)
 153#define FSR_NXA   (1ULL << 5)
 154#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 155
 156#define FSR_NVC   (1ULL << 4)
 157#define FSR_OFC   (1ULL << 3)
 158#define FSR_UFC   (1ULL << 2)
 159#define FSR_DZC   (1ULL << 1)
 160#define FSR_NXC   (1ULL << 0)
 161#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
 162
 163#define FSR_FTT2   (1ULL << 16)
 164#define FSR_FTT1   (1ULL << 15)
 165#define FSR_FTT0   (1ULL << 14)
 166//gcc warns about constant overflow for ~FSR_FTT_MASK
 167//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
 168#ifdef TARGET_SPARC64
 169#define FSR_FTT_NMASK      0xfffffffffffe3fffULL
 170#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
 171#define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
 172#define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
 173#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
 174#else
 175#define FSR_FTT_NMASK      0xfffe3fffULL
 176#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
 177#define FSR_LDFSR_OLDMASK  0x000fc000ULL
 178#endif
 179#define FSR_LDFSR_MASK     0xcfc00fffULL
 180#define FSR_FTT_IEEE_EXCP (1ULL << 14)
 181#define FSR_FTT_UNIMPFPOP (3ULL << 14)
 182#define FSR_FTT_SEQ_ERROR (4ULL << 14)
 183#define FSR_FTT_INVAL_FPR (6ULL << 14)
 184
 185#define FSR_FCC1_SHIFT 11
 186#define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
 187#define FSR_FCC0_SHIFT 10
 188#define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)
 189
 190/* MMU */
 191#define MMU_E     (1<<0)
 192#define MMU_NF    (1<<1)
 193
 194#define PTE_ENTRYTYPE_MASK 3
 195#define PTE_ACCESS_MASK    0x1c
 196#define PTE_ACCESS_SHIFT   2
 197#define PTE_PPN_SHIFT      7
 198#define PTE_ADDR_MASK      0xffffff00
 199
 200#define PG_ACCESSED_BIT 5
 201#define PG_MODIFIED_BIT 6
 202#define PG_CACHE_BIT    7
 203
 204#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 205#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
 206#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
 207
 208/* 3 <= NWINDOWS <= 32. */
 209#define MIN_NWINDOWS 3
 210#define MAX_NWINDOWS 32
 211
 212#ifdef TARGET_SPARC64
 213typedef struct trap_state {
 214    uint64_t tpc;
 215    uint64_t tnpc;
 216    uint64_t tstate;
 217    uint32_t tt;
 218} trap_state;
 219#endif
 220#define TARGET_INSN_START_EXTRA_WORDS 1
 221
 222struct sparc_def_t {
 223    const char *name;
 224    target_ulong iu_version;
 225    uint32_t fpu_version;
 226    uint32_t mmu_version;
 227    uint32_t mmu_bm;
 228    uint32_t mmu_ctpr_mask;
 229    uint32_t mmu_cxr_mask;
 230    uint32_t mmu_sfsr_mask;
 231    uint32_t mmu_trcr_mask;
 232    uint32_t mxcc_version;
 233    uint32_t features;
 234    uint32_t nwindows;
 235    uint32_t maxtl;
 236};
 237
 238#define CPU_FEATURE_FLOAT        (1 << 0)
 239#define CPU_FEATURE_FLOAT128     (1 << 1)
 240#define CPU_FEATURE_SWAP         (1 << 2)
 241#define CPU_FEATURE_MUL          (1 << 3)
 242#define CPU_FEATURE_DIV          (1 << 4)
 243#define CPU_FEATURE_FLUSH        (1 << 5)
 244#define CPU_FEATURE_FSQRT        (1 << 6)
 245#define CPU_FEATURE_FMUL         (1 << 7)
 246#define CPU_FEATURE_VIS1         (1 << 8)
 247#define CPU_FEATURE_VIS2         (1 << 9)
 248#define CPU_FEATURE_FSMULD       (1 << 10)
 249#define CPU_FEATURE_HYPV         (1 << 11)
 250#define CPU_FEATURE_CMT          (1 << 12)
 251#define CPU_FEATURE_GL           (1 << 13)
 252#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
 253#define CPU_FEATURE_ASR17        (1 << 15)
 254#define CPU_FEATURE_CACHE_CTRL   (1 << 16)
 255#define CPU_FEATURE_POWERDOWN    (1 << 17)
 256#define CPU_FEATURE_CASA         (1 << 18)
 257
 258#ifndef TARGET_SPARC64
 259#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 260                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 261                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 262                              CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
 263#else
 264#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 265                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 266                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 267                              CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
 268                              CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
 269                              CPU_FEATURE_CASA)
 270enum {
 271    mmu_us_12, // Ultrasparc < III (64 entry TLB)
 272    mmu_us_3,  // Ultrasparc III (512 entry TLB)
 273    mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
 274    mmu_sun4v, // T1, T2
 275};
 276#endif
 277
 278#define TTE_VALID_BIT       (1ULL << 63)
 279#define TTE_NFO_BIT         (1ULL << 60)
 280#define TTE_USED_BIT        (1ULL << 41)
 281#define TTE_LOCKED_BIT      (1ULL <<  6)
 282#define TTE_SIDEEFFECT_BIT  (1ULL <<  3)
 283#define TTE_PRIV_BIT        (1ULL <<  2)
 284#define TTE_W_OK_BIT        (1ULL <<  1)
 285#define TTE_GLOBAL_BIT      (1ULL <<  0)
 286
 287#define TTE_NFO_BIT_UA2005  (1ULL << 62)
 288#define TTE_USED_BIT_UA2005 (1ULL << 47)
 289#define TTE_LOCKED_BIT_UA2005 (1ULL <<  61)
 290#define TTE_SIDEEFFECT_BIT_UA2005 (1ULL <<  11)
 291#define TTE_PRIV_BIT_UA2005 (1ULL <<  8)
 292#define TTE_W_OK_BIT_UA2005 (1ULL <<  6)
 293
 294#define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
 295#define TTE_IS_NFO(tte)     ((tte) & TTE_NFO_BIT)
 296#define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)
 297#define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
 298#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
 299#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
 300#define TTE_IS_PRIV(tte)    ((tte) & TTE_PRIV_BIT)
 301#define TTE_IS_W_OK(tte)    ((tte) & TTE_W_OK_BIT)
 302
 303#define TTE_IS_NFO_UA2005(tte)     ((tte) & TTE_NFO_BIT_UA2005)
 304#define TTE_IS_USED_UA2005(tte)    ((tte) & TTE_USED_BIT_UA2005)
 305#define TTE_IS_LOCKED_UA2005(tte)  ((tte) & TTE_LOCKED_BIT_UA2005)
 306#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
 307#define TTE_IS_PRIV_UA2005(tte)    ((tte) & TTE_PRIV_BIT_UA2005)
 308#define TTE_IS_W_OK_UA2005(tte)    ((tte) & TTE_W_OK_BIT_UA2005)
 309
 310#define TTE_IS_GLOBAL(tte)  ((tte) & TTE_GLOBAL_BIT)
 311
 312#define TTE_SET_USED(tte)   ((tte) |= TTE_USED_BIT)
 313#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
 314
 315#define TTE_PGSIZE(tte)     (((tte) >> 61) & 3ULL)
 316#define TTE_PGSIZE_UA2005(tte)     ((tte) & 7ULL)
 317#define TTE_PA(tte)         ((tte) & 0x1ffffffe000ULL)
 318
 319/* UltraSPARC T1 specific */
 320#define TLB_UST1_IS_REAL_BIT   (1ULL << 9)  /* Real translation entry */
 321#define TLB_UST1_IS_SUN4V_BIT  (1ULL << 10) /* sun4u/sun4v TTE format switch */
 322
 323#define SFSR_NF_BIT         (1ULL << 24)   /* JPS1 NoFault */
 324#define SFSR_TM_BIT         (1ULL << 15)   /* JPS1 TLB Miss */
 325#define SFSR_FT_VA_IMMU_BIT (1ULL << 13)   /* USIIi VA out of range (IMMU) */
 326#define SFSR_FT_VA_DMMU_BIT (1ULL << 12)   /* USIIi VA out of range (DMMU) */
 327#define SFSR_FT_NFO_BIT     (1ULL << 11)   /* NFO page access */
 328#define SFSR_FT_ILL_BIT     (1ULL << 10)   /* illegal LDA/STA ASI */
 329#define SFSR_FT_ATOMIC_BIT  (1ULL <<  9)   /* atomic op on noncacheable area */
 330#define SFSR_FT_NF_E_BIT    (1ULL <<  8)   /* NF access on side effect area */
 331#define SFSR_FT_PRIV_BIT    (1ULL <<  7)   /* privilege violation */
 332#define SFSR_PR_BIT         (1ULL <<  3)   /* privilege mode */
 333#define SFSR_WRITE_BIT      (1ULL <<  2)   /* write access mode */
 334#define SFSR_OW_BIT         (1ULL <<  1)   /* status overwritten */
 335#define SFSR_VALID_BIT      (1ULL <<  0)   /* status valid */
 336
 337#define SFSR_ASI_SHIFT      16             /* 23:16 ASI value */
 338#define SFSR_ASI_MASK       (0xffULL << SFSR_ASI_SHIFT)
 339#define SFSR_CT_PRIMARY     (0ULL <<  4)   /* 5:4 context type */
 340#define SFSR_CT_SECONDARY   (1ULL <<  4)
 341#define SFSR_CT_NUCLEUS     (2ULL <<  4)
 342#define SFSR_CT_NOTRANS     (3ULL <<  4)
 343#define SFSR_CT_MASK        (3ULL <<  4)
 344
 345/* Leon3 cache control */
 346
 347/* Cache control: emulate the behavior of cache control registers but without
 348   any effect on the emulated */
 349
 350#define CACHE_STATE_MASK 0x3
 351#define CACHE_DISABLED   0x0
 352#define CACHE_FROZEN     0x1
 353#define CACHE_ENABLED    0x3
 354
 355/* Cache Control register fields */
 356
 357#define CACHE_CTRL_IF (1 <<  4)  /* Instruction Cache Freeze on Interrupt */
 358#define CACHE_CTRL_DF (1 <<  5)  /* Data Cache Freeze on Interrupt */
 359#define CACHE_CTRL_DP (1 << 14)  /* Data cache flush pending */
 360#define CACHE_CTRL_IP (1 << 15)  /* Instruction cache flush pending */
 361#define CACHE_CTRL_IB (1 << 16)  /* Instruction burst fetch */
 362#define CACHE_CTRL_FI (1 << 21)  /* Flush Instruction cache (Write only) */
 363#define CACHE_CTRL_FD (1 << 22)  /* Flush Data cache (Write only) */
 364#define CACHE_CTRL_DS (1 << 23)  /* Data cache snoop enable */
 365
 366#define CONVERT_BIT(X, SRC, DST) \
 367         (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
 368
 369typedef struct SparcTLBEntry {
 370    uint64_t tag;
 371    uint64_t tte;
 372} SparcTLBEntry;
 373
 374struct CPUTimer
 375{
 376    const char *name;
 377    uint32_t    frequency;
 378    uint32_t    disabled;
 379    uint64_t    disabled_mask;
 380    uint32_t    npt;
 381    uint64_t    npt_mask;
 382    int64_t     clock_offset;
 383    QEMUTimer  *qtimer;
 384};
 385
 386typedef struct CPUTimer CPUTimer;
 387
 388typedef struct CPUSPARCState CPUSPARCState;
 389#if defined(TARGET_SPARC64)
 390typedef union {
 391   uint64_t mmuregs[16];
 392   struct {
 393    uint64_t tsb_tag_target;
 394    uint64_t mmu_primary_context;
 395    uint64_t mmu_secondary_context;
 396    uint64_t sfsr;
 397    uint64_t sfar;
 398    uint64_t tsb;
 399    uint64_t tag_access;
 400    uint64_t virtual_watchpoint;
 401    uint64_t physical_watchpoint;
 402    uint64_t sun4v_ctx_config[2];
 403    uint64_t sun4v_tsb_pointers[4];
 404   };
 405} SparcV9MMU;
 406#endif
 407struct CPUSPARCState {
 408    target_ulong gregs[8]; /* general registers */
 409    target_ulong *regwptr; /* pointer to current register window */
 410    target_ulong pc;       /* program counter */
 411    target_ulong npc;      /* next program counter */
 412    target_ulong y;        /* multiply/divide register */
 413
 414    /* emulator internal flags handling */
 415    target_ulong cc_src, cc_src2;
 416    target_ulong cc_dst;
 417    uint32_t cc_op;
 418
 419    target_ulong cond; /* conditional branch result (XXX: save it in a
 420                          temporary register when possible) */
 421
 422    uint32_t psr;      /* processor state register */
 423    target_ulong fsr;      /* FPU state register */
 424    CPU_DoubleU fpr[TARGET_DPREGS];  /* floating point registers */
 425    uint32_t cwp;      /* index of current register window (extracted
 426                          from PSR) */
 427#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 428    uint32_t wim;      /* window invalid mask */
 429#endif
 430    target_ulong tbr;  /* trap base register */
 431#if !defined(TARGET_SPARC64)
 432    int      psrs;     /* supervisor mode (extracted from PSR) */
 433    int      psrps;    /* previous supervisor mode */
 434    int      psret;    /* enable traps */
 435#endif
 436    uint32_t psrpil;   /* interrupt blocking level */
 437    uint32_t pil_in;   /* incoming interrupt level bitmap */
 438#if !defined(TARGET_SPARC64)
 439    int      psref;    /* enable fpu */
 440#endif
 441    int interrupt_index;
 442    /* NOTE: we allow 8 more registers to handle wrapping */
 443    target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 444
 445    /* Fields up to this point are cleared by a CPU reset */
 446    struct {} end_reset_fields;
 447
 448    /* Fields from here on are preserved across CPU reset. */
 449    target_ulong version;
 450    uint32_t nwindows;
 451
 452    /* MMU regs */
 453#if defined(TARGET_SPARC64)
 454    uint64_t lsu;
 455#define DMMU_E 0x8
 456#define IMMU_E 0x4
 457    SparcV9MMU immu;
 458    SparcV9MMU dmmu;
 459    SparcTLBEntry itlb[64];
 460    SparcTLBEntry dtlb[64];
 461    uint32_t mmu_version;
 462#else
 463    uint32_t mmuregs[32];
 464    uint64_t mxccdata[4];
 465    uint64_t mxccregs[8];
 466    uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
 467    uint64_t mmubpaction;
 468    uint64_t mmubpregs[4];
 469    uint64_t prom_addr;
 470#endif
 471    /* temporary float registers */
 472    float128 qt0, qt1;
 473    float_status fp_status;
 474#if defined(TARGET_SPARC64)
 475#define MAXTL_MAX 8
 476#define MAXTL_MASK (MAXTL_MAX - 1)
 477    trap_state ts[MAXTL_MAX];
 478    uint32_t xcc;               /* Extended integer condition codes */
 479    uint32_t asi;
 480    uint32_t pstate;
 481    uint32_t tl;
 482    uint32_t maxtl;
 483    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
 484    uint64_t agregs[8]; /* alternate general registers */
 485    uint64_t bgregs[8]; /* backup for normal global registers */
 486    uint64_t igregs[8]; /* interrupt general registers */
 487    uint64_t mgregs[8]; /* mmu general registers */
 488    uint64_t glregs[8 * MAXTL_MAX];
 489    uint64_t fprs;
 490    uint64_t tick_cmpr, stick_cmpr;
 491    CPUTimer *tick, *stick;
 492#define TICK_NPT_MASK        0x8000000000000000ULL
 493#define TICK_INT_DIS         0x8000000000000000ULL
 494    uint64_t gsr;
 495    uint32_t gl; // UA2005
 496    /* UA 2005 hyperprivileged registers */
 497    uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
 498    uint64_t scratch[8];
 499    CPUTimer *hstick; // UA 2005
 500    /* Interrupt vector registers */
 501    uint64_t ivec_status;
 502    uint64_t ivec_data[3];
 503    uint32_t softint;
 504#define SOFTINT_TIMER   1
 505#define SOFTINT_STIMER  (1 << 16)
 506#define SOFTINT_INTRMASK (0xFFFE)
 507#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
 508#endif
 509    sparc_def_t def;
 510
 511    void *irq_manager;
 512    void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
 513
 514    /* Leon3 cache control */
 515    uint32_t cache_control;
 516};
 517
 518/**
 519 * SPARCCPU:
 520 * @env: #CPUSPARCState
 521 *
 522 * A SPARC CPU.
 523 */
 524struct SPARCCPU {
 525    /*< private >*/
 526    CPUState parent_obj;
 527    /*< public >*/
 528
 529    CPUNegativeOffsetState neg;
 530    CPUSPARCState env;
 531};
 532
 533
 534#ifndef CONFIG_USER_ONLY
 535extern const struct VMStateDescription vmstate_sparc_cpu;
 536#endif
 537
 538void sparc_cpu_do_interrupt(CPUState *cpu);
 539void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 540hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 541int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 542int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 543void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 544                                                 MMUAccessType access_type,
 545                                                 int mmu_idx,
 546                                                 uintptr_t retaddr);
 547void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN;
 548
 549#ifndef NO_CPU_IO_DEFS
 550/* cpu_init.c */
 551void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
 552void sparc_cpu_list(void);
 553/* mmu_helper.c */
 554bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 555                        MMUAccessType access_type, int mmu_idx,
 556                        bool probe, uintptr_t retaddr);
 557target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
 558void dump_mmu(CPUSPARCState *env);
 559
 560#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 561int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 562                              uint8_t *buf, int len, bool is_write);
 563#endif
 564
 565
 566/* translate.c */
 567void sparc_tcg_init(void);
 568
 569/* cpu-exec.c */
 570
 571/* win_helper.c */
 572target_ulong cpu_get_psr(CPUSPARCState *env1);
 573void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
 574void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
 575#ifdef TARGET_SPARC64
 576target_ulong cpu_get_ccr(CPUSPARCState *env1);
 577void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
 578target_ulong cpu_get_cwp64(CPUSPARCState *env1);
 579void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
 580void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
 581void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl);
 582#endif
 583int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
 584int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
 585void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
 586
 587/* int_helper.c */
 588void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
 589
 590/* sun4m.c, sun4u.c */
 591void cpu_check_irqs(CPUSPARCState *env);
 592
 593/* leon3.c */
 594void leon3_irq_ack(void *irq_manager, int intno);
 595
 596#if defined (TARGET_SPARC64)
 597
 598static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
 599{
 600    return (x & mask) == (y & mask);
 601}
 602
 603#define MMU_CONTEXT_BITS 13
 604#define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
 605
 606static inline int tlb_compare_context(const SparcTLBEntry *tlb,
 607                                      uint64_t context)
 608{
 609    return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
 610}
 611
 612#endif
 613#endif
 614
 615/* cpu-exec.c */
 616#if !defined(CONFIG_USER_ONLY)
 617void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 618                                 bool is_write, bool is_exec, int is_asi,
 619                                 unsigned size);
 620#if defined(TARGET_SPARC64)
 621hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
 622                                           int mmu_idx);
 623#endif
 624#endif
 625int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 626
 627#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
 628#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
 629#define CPU_RESOLVING_TYPE TYPE_SPARC_CPU
 630
 631#define cpu_signal_handler cpu_sparc_signal_handler
 632#define cpu_list sparc_cpu_list
 633
 634/* MMU modes definitions */
 635#if defined (TARGET_SPARC64)
 636#define MMU_USER_IDX   0
 637#define MMU_USER_SECONDARY_IDX   1
 638#define MMU_KERNEL_IDX 2
 639#define MMU_KERNEL_SECONDARY_IDX 3
 640#define MMU_NUCLEUS_IDX 4
 641#define MMU_PHYS_IDX   5
 642#else
 643#define MMU_USER_IDX   0
 644#define MMU_KERNEL_IDX 1
 645#define MMU_PHYS_IDX   2
 646#endif
 647
 648#if defined (TARGET_SPARC64)
 649static inline int cpu_has_hypervisor(CPUSPARCState *env1)
 650{
 651    return env1->def.features & CPU_FEATURE_HYPV;
 652}
 653
 654static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
 655{
 656    return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
 657}
 658
 659static inline int cpu_supervisor_mode(CPUSPARCState *env1)
 660{
 661    return env1->pstate & PS_PRIV;
 662}
 663#else
 664static inline int cpu_supervisor_mode(CPUSPARCState *env1)
 665{
 666    return env1->psrs;
 667}
 668#endif
 669
 670static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
 671{
 672#if defined(CONFIG_USER_ONLY)
 673    return MMU_USER_IDX;
 674#elif !defined(TARGET_SPARC64)
 675    if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
 676        return MMU_PHYS_IDX;
 677    } else {
 678        return env->psrs;
 679    }
 680#else
 681    /* IMMU or DMMU disabled.  */
 682    if (ifetch
 683        ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
 684        : (env->lsu & DMMU_E) == 0) {
 685        return MMU_PHYS_IDX;
 686    } else if (cpu_hypervisor_mode(env)) {
 687        return MMU_PHYS_IDX;
 688    } else if (env->tl > 0) {
 689        return MMU_NUCLEUS_IDX;
 690    } else if (cpu_supervisor_mode(env)) {
 691        return MMU_KERNEL_IDX;
 692    } else {
 693        return MMU_USER_IDX;
 694    }
 695#endif
 696}
 697
 698static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
 699{
 700#if !defined (TARGET_SPARC64)
 701    if (env1->psret != 0)
 702        return 1;
 703#else
 704    if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) {
 705        return 1;
 706    }
 707#endif
 708
 709    return 0;
 710}
 711
 712static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
 713{
 714#if !defined(TARGET_SPARC64)
 715    /* level 15 is non-maskable on sparc v8 */
 716    return pil == 15 || pil > env1->psrpil;
 717#else
 718    return pil > env1->psrpil;
 719#endif
 720}
 721
 722typedef CPUSPARCState CPUArchState;
 723typedef SPARCCPU ArchCPU;
 724
 725#include "exec/cpu-all.h"
 726
 727#ifdef TARGET_SPARC64
 728/* sun4u.c */
 729void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
 730uint64_t cpu_tick_get_count(CPUTimer *timer);
 731void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
 732trap_state* cpu_tsptr(CPUSPARCState* env);
 733#endif
 734
 735#define TB_FLAG_MMU_MASK     7
 736#define TB_FLAG_FPU_ENABLED  (1 << 4)
 737#define TB_FLAG_AM_ENABLED   (1 << 5)
 738#define TB_FLAG_SUPER        (1 << 6)
 739#define TB_FLAG_HYPER        (1 << 7)
 740#define TB_FLAG_ASI_SHIFT    24
 741
 742static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
 743                                        target_ulong *cs_base, uint32_t *pflags)
 744{
 745    uint32_t flags;
 746    *pc = env->pc;
 747    *cs_base = env->npc;
 748    flags = cpu_mmu_index(env, false);
 749#ifndef CONFIG_USER_ONLY
 750    if (cpu_supervisor_mode(env)) {
 751        flags |= TB_FLAG_SUPER;
 752    }
 753#endif
 754#ifdef TARGET_SPARC64
 755#ifndef CONFIG_USER_ONLY
 756    if (cpu_hypervisor_mode(env)) {
 757        flags |= TB_FLAG_HYPER;
 758    }
 759#endif
 760    if (env->pstate & PS_AM) {
 761        flags |= TB_FLAG_AM_ENABLED;
 762    }
 763    if ((env->def.features & CPU_FEATURE_FLOAT)
 764        && (env->pstate & PS_PEF)
 765        && (env->fprs & FPRS_FEF)) {
 766        flags |= TB_FLAG_FPU_ENABLED;
 767    }
 768    flags |= env->asi << TB_FLAG_ASI_SHIFT;
 769#else
 770    if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
 771        flags |= TB_FLAG_FPU_ENABLED;
 772    }
 773#endif
 774    *pflags = flags;
 775}
 776
 777static inline bool tb_fpu_enabled(int tb_flags)
 778{
 779#if defined(CONFIG_USER_ONLY)
 780    return true;
 781#else
 782    return tb_flags & TB_FLAG_FPU_ENABLED;
 783#endif
 784}
 785
 786static inline bool tb_am_enabled(int tb_flags)
 787{
 788#ifndef TARGET_SPARC64
 789    return false;
 790#else
 791    return tb_flags & TB_FLAG_AM_ENABLED;
 792#endif
 793}
 794
 795#endif
 796
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