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25#include "qemu/osdep.h"
26
27#include "libqtest.h"
28#include "libqos/ahci.h"
29#include "libqos/pci-pc.h"
30
31#include "qemu-common.h"
32#include "qemu/host-utils.h"
33
34#include "hw/pci/pci_ids.h"
35#include "hw/pci/pci_regs.h"
36
37typedef struct AHCICommandProp {
38 uint8_t cmd;
39 bool data;
40 bool pio;
41 bool dma;
42 bool lba28;
43 bool lba48;
44 bool read;
45 bool write;
46 bool atapi;
47 bool ncq;
48 uint64_t size;
49 uint32_t interrupts;
50} AHCICommandProp;
51
52AHCICommandProp ahci_command_properties[] = {
53 { .cmd = CMD_READ_PIO, .data = true, .pio = true,
54 .lba28 = true, .read = true },
55 { .cmd = CMD_WRITE_PIO, .data = true, .pio = true,
56 .lba28 = true, .write = true },
57 { .cmd = CMD_READ_PIO_EXT, .data = true, .pio = true,
58 .lba48 = true, .read = true },
59 { .cmd = CMD_WRITE_PIO_EXT, .data = true, .pio = true,
60 .lba48 = true, .write = true },
61 { .cmd = CMD_READ_DMA, .data = true, .dma = true,
62 .lba28 = true, .read = true },
63 { .cmd = CMD_WRITE_DMA, .data = true, .dma = true,
64 .lba28 = true, .write = true },
65 { .cmd = CMD_READ_DMA_EXT, .data = true, .dma = true,
66 .lba48 = true, .read = true },
67 { .cmd = CMD_WRITE_DMA_EXT, .data = true, .dma = true,
68 .lba48 = true, .write = true },
69 { .cmd = CMD_IDENTIFY, .data = true, .pio = true,
70 .size = 512, .read = true },
71 { .cmd = READ_FPDMA_QUEUED, .data = true, .dma = true,
72 .lba48 = true, .read = true, .ncq = true },
73 { .cmd = WRITE_FPDMA_QUEUED, .data = true, .dma = true,
74 .lba48 = true, .write = true, .ncq = true },
75 { .cmd = CMD_READ_MAX, .lba28 = true },
76 { .cmd = CMD_READ_MAX_EXT, .lba48 = true },
77 { .cmd = CMD_FLUSH_CACHE, .data = false },
78 { .cmd = CMD_PACKET, .data = true, .size = 16,
79 .atapi = true, .pio = true },
80 { .cmd = CMD_PACKET_ID, .data = true, .pio = true,
81 .size = 512, .read = true }
82};
83
84struct AHCICommand {
85
86 uint8_t name;
87 uint8_t port;
88 uint8_t slot;
89 uint8_t errors;
90 uint32_t interrupts;
91 uint64_t xbytes;
92 uint32_t prd_size;
93 uint32_t sector_size;
94 uint64_t buffer;
95 AHCICommandProp *props;
96
97 AHCICommandHeader header;
98 RegH2DFIS fis;
99 unsigned char *atapi_cmd;
100};
101
102
103
104
105uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes)
106{
107 g_assert(ahci);
108 g_assert(ahci->parent);
109 return qmalloc(ahci->parent, bytes);
110}
111
112void ahci_free(AHCIQState *ahci, uint64_t addr)
113{
114 g_assert(ahci);
115 g_assert(ahci->parent);
116 qfree(ahci->parent, addr);
117}
118
119bool is_atapi(AHCIQState *ahci, uint8_t port)
120{
121 return ahci_px_rreg(ahci, port, AHCI_PX_SIG) == AHCI_SIGNATURE_CDROM;
122}
123
124
125
126
127QPCIDevice *get_ahci_device(QTestState *qts, uint32_t *fingerprint)
128{
129 QPCIDevice *ahci;
130 uint32_t ahci_fingerprint;
131 QPCIBus *pcibus;
132
133 pcibus = qpci_new_pc(qts, NULL);
134
135
136 ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
137 g_assert(ahci != NULL);
138
139 ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
140
141 switch (ahci_fingerprint) {
142 case AHCI_INTEL_ICH9:
143 break;
144 default:
145
146 g_assert_not_reached();
147 }
148
149 if (fingerprint) {
150 *fingerprint = ahci_fingerprint;
151 }
152 return ahci;
153}
154
155void free_ahci_device(QPCIDevice *dev)
156{
157 QPCIBus *pcibus = dev ? dev->bus : NULL;
158
159
160 g_free(dev);
161 qpci_free_pc(pcibus);
162}
163
164
165void ahci_clean_mem(AHCIQState *ahci)
166{
167 uint8_t port, slot;
168
169 for (port = 0; port < 32; ++port) {
170 if (ahci->port[port].fb) {
171 ahci_free(ahci, ahci->port[port].fb);
172 ahci->port[port].fb = 0;
173 }
174 if (ahci->port[port].clb) {
175 for (slot = 0; slot < 32; slot++) {
176 ahci_destroy_command(ahci, port, slot);
177 }
178 ahci_free(ahci, ahci->port[port].clb);
179 ahci->port[port].clb = 0;
180 }
181 }
182}
183
184
185
186
187
188
189void ahci_pci_enable(AHCIQState *ahci)
190{
191 uint8_t reg;
192
193 start_ahci_device(ahci);
194
195 switch (ahci->fingerprint) {
196 case AHCI_INTEL_ICH9:
197
198
199 reg = qpci_config_readb(ahci->dev, 0x92);
200 reg |= 0x3F;
201 qpci_config_writeb(ahci->dev, 0x92, reg);
202
203 ASSERT_BIT_SET(qpci_config_readb(ahci->dev, 0x92), 0x3F);
204 break;
205 }
206
207}
208
209
210
211
212void start_ahci_device(AHCIQState *ahci)
213{
214
215 ahci->hba_bar = qpci_iomap(ahci->dev, 5, &ahci->barsize);
216
217
218 qpci_device_enable(ahci->dev);
219}
220
221
222
223
224
225
226void ahci_hba_enable(AHCIQState *ahci)
227{
228
229
230
231
232
233
234
235
236
237 uint32_t reg, ports_impl;
238 uint16_t i;
239 uint8_t num_cmd_slots;
240
241 g_assert(ahci != NULL);
242
243
244 ahci_set(ahci, AHCI_GHC, AHCI_GHC_AE);
245 reg = ahci_rreg(ahci, AHCI_GHC);
246 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
247
248
249 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
250 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
251
252
253 num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
254 g_test_message("Number of Command Slots: %u", num_cmd_slots);
255
256
257 ports_impl = ahci_rreg(ahci, AHCI_PI);
258
259 for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
260 if (!(ports_impl & 0x01)) {
261 continue;
262 }
263
264 g_test_message("Initializing port %u", i);
265
266 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
267 if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
268 AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
269 g_test_message("port is idle");
270 } else {
271 g_test_message("port needs to be idled");
272 ahci_px_clr(ahci, i, AHCI_PX_CMD,
273 (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
274
275 usleep(500000);
276 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
277 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
278 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
279 g_test_message("port is now idle");
280
281
282 }
283
284
285
286 ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20);
287 qtest_memset(ahci->parent->qts, ahci->port[i].clb, 0x00,
288 num_cmd_slots * 0x20);
289 g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb);
290 ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb);
291 g_assert_cmphex(ahci->port[i].clb, ==,
292 ahci_px_rreg(ahci, i, AHCI_PX_CLB));
293
294
295 ahci->port[i].fb = ahci_alloc(ahci, 0x100);
296 qtest_memset(ahci->parent->qts, ahci->port[i].fb, 0x00, 0x100);
297 g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb);
298 ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb);
299 g_assert_cmphex(ahci->port[i].fb, ==,
300 ahci_px_rreg(ahci, i, AHCI_PX_FB));
301
302
303 ahci_px_wreg(ahci, i, AHCI_PX_SERR, 0xFFFFFFFF);
304 ahci_px_wreg(ahci, i, AHCI_PX_IS, 0xFFFFFFFF);
305 ahci_wreg(ahci, AHCI_IS, (1 << i));
306
307
308 reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
309 g_assert_cmphex(reg, ==, 0);
310
311 reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
312 g_assert_cmphex(reg, ==, 0);
313
314 reg = ahci_rreg(ahci, AHCI_IS);
315 ASSERT_BIT_CLEAR(reg, (1 << i));
316
317
318 ahci_px_wreg(ahci, i, AHCI_PX_IE, 0xFFFFFFFF);
319 reg = ahci_px_rreg(ahci, i, AHCI_PX_IE);
320 g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
321
322
323 ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
324 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
325 ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
326
327
328
329
330 reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
331 if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
332 ahci_px_set(ahci, i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
333 }
334
335 reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
336 if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
337 reg = ahci_px_rreg(ahci, i, AHCI_PX_SSTS);
338 if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
339
340 ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
341 ASSERT_BIT_SET(ahci_px_rreg(ahci, i, AHCI_PX_CMD),
342 AHCI_PX_CMD_CR);
343 g_test_message("Started Device %u", i);
344 } else if ((reg & AHCI_PX_SSTS_DET)) {
345
346 g_assert_not_reached();
347 }
348 }
349 }
350
351
352 ahci_set(ahci, AHCI_GHC, AHCI_GHC_IE);
353 reg = ahci_rreg(ahci, AHCI_GHC);
354 ASSERT_BIT_SET(reg, AHCI_GHC_IE);
355
356 ahci->enabled = true;
357
358
359
360}
361
362
363
364
365unsigned ahci_port_select(AHCIQState *ahci)
366{
367 uint32_t ports, reg;
368 unsigned i;
369
370 ports = ahci_rreg(ahci, AHCI_PI);
371 for (i = 0; i < 32; ports >>= 1, ++i) {
372 if (ports == 0) {
373 i = 32;
374 }
375
376 if (!(ports & 0x01)) {
377 continue;
378 }
379
380 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
381 if (BITSET(reg, AHCI_PX_CMD_ST)) {
382 break;
383 }
384 }
385 g_assert(i < 32);
386 return i;
387}
388
389
390
391
392void ahci_port_clear(AHCIQState *ahci, uint8_t port)
393{
394 uint32_t reg;
395
396
397 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
398 ahci_px_wreg(ahci, port, AHCI_PX_IS, reg);
399 g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
400
401
402 qtest_memset(ahci->parent->qts, ahci->port[port].fb, 0x00, 0x100);
403}
404
405
406
407
408void ahci_port_check_error(AHCIQState *ahci, uint8_t port,
409 uint32_t imask, uint8_t emask)
410{
411 uint32_t reg;
412
413
414 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
415 reg &= ~imask;
416 reg >>= 23;
417 g_assert_cmphex(reg, ==, 0);
418
419
420 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
421 g_assert_cmphex(reg, ==, 0);
422
423
424 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
425 if (!emask) {
426 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
427 } else {
428 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
429 }
430 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR & (~emask << 8));
431 ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (emask << 8));
432}
433
434void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port,
435 uint32_t intr_mask)
436{
437 uint32_t reg;
438
439
440 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
441 ASSERT_BIT_SET(reg, intr_mask);
442
443
444 ahci_px_wreg(ahci, port, AHCI_PX_IS, intr_mask);
445 g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
446}
447
448void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot)
449{
450 uint32_t reg;
451
452
453 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
454 ASSERT_BIT_CLEAR(reg, (1 << slot));
455
456
457 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
458 ASSERT_BIT_CLEAR(reg, (1 << slot));
459
460
461 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
462 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
463 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_DRQ);
464}
465
466void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot)
467{
468 RegD2HFIS *d2h = g_malloc0(0x20);
469 uint32_t reg;
470
471 qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20);
472 g_assert_cmphex(d2h->fis_type, ==, 0x34);
473
474 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
475 g_assert_cmphex((reg & AHCI_PX_TFD_ERR) >> 8, ==, d2h->error);
476 g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, d2h->status);
477
478 g_free(d2h);
479}
480
481void ahci_port_check_pio_sanity(AHCIQState *ahci, AHCICommand *cmd)
482{
483 PIOSetupFIS *pio = g_malloc0(0x20);
484 uint8_t port = cmd->port;
485
486
487
488
489 qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x20, pio, 0x20);
490 g_assert_cmphex(pio->fis_type, ==, 0x5f);
491
492
493
494
495
496
497 if (cmd->props->atapi && (cmd->xbytes == 0 || cmd->props->dma)) {
498 g_assert(le16_to_cpu(pio->tx_count) == 12 ||
499 le16_to_cpu(pio->tx_count) == 16);
500 } else {
501
502
503
504 size_t pio_len = ((cmd->xbytes % cmd->sector_size) ?
505 (cmd->xbytes % cmd->sector_size) : cmd->sector_size);
506 g_assert_cmphex(le16_to_cpu(pio->tx_count), ==, pio_len);
507 }
508 g_free(pio);
509}
510
511void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd)
512{
513 AHCICommandHeader cmdh;
514
515 ahci_get_command_header(ahci, cmd->port, cmd->slot, &cmdh);
516
517 if (!cmd->props->ncq) {
518 g_assert_cmphex(cmd->xbytes, ==, cmdh.prdbc);
519 }
520}
521
522
523void ahci_get_command_header(AHCIQState *ahci, uint8_t port,
524 uint8_t slot, AHCICommandHeader *cmd)
525{
526 uint64_t ba = ahci->port[port].clb;
527 ba += slot * sizeof(AHCICommandHeader);
528 qtest_memread(ahci->parent->qts, ba, cmd, sizeof(AHCICommandHeader));
529
530 cmd->flags = le16_to_cpu(cmd->flags);
531 cmd->prdtl = le16_to_cpu(cmd->prdtl);
532 cmd->prdbc = le32_to_cpu(cmd->prdbc);
533 cmd->ctba = le64_to_cpu(cmd->ctba);
534}
535
536
537void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
538 uint8_t slot, AHCICommandHeader *cmd)
539{
540 AHCICommandHeader tmp = { .flags = 0 };
541 uint64_t ba = ahci->port[port].clb;
542 ba += slot * sizeof(AHCICommandHeader);
543
544 tmp.flags = cpu_to_le16(cmd->flags);
545 tmp.prdtl = cpu_to_le16(cmd->prdtl);
546 tmp.prdbc = cpu_to_le32(cmd->prdbc);
547 tmp.ctba = cpu_to_le64(cmd->ctba);
548
549 qtest_memwrite(ahci->parent->qts, ba, &tmp, sizeof(AHCICommandHeader));
550}
551
552void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot)
553{
554 AHCICommandHeader cmd;
555
556
557 ahci_get_command_header(ahci, port, slot, &cmd);
558 if (cmd.ctba == 0) {
559
560 goto tidy;
561 }
562
563
564 ahci_free(ahci, cmd.ctba);
565
566 tidy:
567
568 memset(&cmd, 0x00, sizeof(cmd));
569 ahci_set_command_header(ahci, port, slot, &cmd);
570 ahci->port[port].ctba[slot] = 0;
571 ahci->port[port].prdtl[slot] = 0;
572}
573
574void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd)
575{
576 RegH2DFIS tmp = cmd->fis;
577 uint64_t addr = cmd->header.ctba;
578
579
580
581
582
583 if (!cmd->props->ncq) {
584 tmp.count = cpu_to_le16(tmp.count);
585 }
586
587 qtest_memwrite(ahci->parent->qts, addr, &tmp, sizeof(tmp));
588}
589
590unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port)
591{
592 unsigned i;
593 unsigned j;
594 uint32_t reg;
595
596 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
597
598
599 for (i = 0; i < 32; ++i) {
600 j = ((ahci->port[port].next + i) % 32);
601 if (reg & (1 << j)) {
602 continue;
603 }
604 ahci_destroy_command(ahci, port, j);
605 ahci->port[port].next = (j + 1) % 32;
606 return j;
607 }
608
609 g_test_message("All command slots were busy.");
610 g_assert_not_reached();
611}
612
613inline unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd)
614{
615
616 g_assert_cmphex(bytes_per_prd, <=, 4096 * 1024);
617 g_assert_cmphex(bytes_per_prd & 0x01, ==, 0x00);
618 return (bytes + bytes_per_prd - 1) / bytes_per_prd;
619}
620
621const AHCIOpts default_opts = { .size = 0 };
622
623
624
625
626
627
628
629
630
631
632
633
634void ahci_exec(AHCIQState *ahci, uint8_t port,
635 uint8_t op, const AHCIOpts *opts_in)
636{
637 AHCICommand *cmd;
638 int rc;
639 AHCIOpts *opts;
640
641 opts = g_memdup((opts_in == NULL ? &default_opts : opts_in),
642 sizeof(AHCIOpts));
643
644
645 if (opts->size && !opts->buffer) {
646 opts->buffer = ahci_alloc(ahci, opts->size);
647 g_assert(opts->buffer);
648 qtest_memset(ahci->parent->qts, opts->buffer, 0x00, opts->size);
649 }
650
651
652 if (opts->atapi) {
653 uint16_t bcl = opts->set_bcl ? opts->bcl : ATAPI_SECTOR_SIZE;
654 cmd = ahci_atapi_command_create(op, bcl, opts->atapi_dma);
655 } else {
656 cmd = ahci_command_create(op);
657 }
658 ahci_command_adjust(cmd, opts->lba, opts->buffer,
659 opts->size, opts->prd_size);
660
661 if (opts->pre_cb) {
662 rc = opts->pre_cb(ahci, cmd, opts);
663 g_assert_cmpint(rc, ==, 0);
664 }
665
666
667 ahci_command_commit(ahci, cmd, port);
668 ahci_command_issue_async(ahci, cmd);
669 if (opts->error) {
670 qtest_qmp_eventwait(ahci->parent->qts, "STOP");
671 }
672 if (opts->mid_cb) {
673 rc = opts->mid_cb(ahci, cmd, opts);
674 g_assert_cmpint(rc, ==, 0);
675 }
676 if (opts->error) {
677 qtest_qmp_send(ahci->parent->qts, "{'execute':'cont' }");
678 qtest_qmp_eventwait(ahci->parent->qts, "RESUME");
679 }
680
681
682 ahci_command_wait(ahci, cmd);
683 ahci_command_verify(ahci, cmd);
684 if (opts->post_cb) {
685 rc = opts->post_cb(ahci, cmd, opts);
686 g_assert_cmpint(rc, ==, 0);
687 }
688 ahci_command_free(cmd);
689 if (opts->buffer != opts_in->buffer) {
690 ahci_free(ahci, opts->buffer);
691 }
692 g_free(opts);
693}
694
695
696AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,
697 uint8_t ide_cmd, uint64_t buffer,
698 size_t bufsize, uint64_t sector)
699{
700 AHCICommand *cmd;
701
702 cmd = ahci_command_create(ide_cmd);
703 ahci_command_adjust(cmd, sector, buffer, bufsize, 0);
704 ahci_command_commit(ahci, cmd, port);
705 ahci_command_issue_async(ahci, cmd);
706 qtest_qmp_eventwait(ahci->parent->qts, "STOP");
707
708 return cmd;
709}
710
711
712void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd)
713{
714
715 qtest_qmp_send(ahci->parent->qts, "{'execute':'cont' }");
716 qtest_qmp_eventwait(ahci->parent->qts, "RESUME");
717 ahci_command_wait(ahci, cmd);
718 ahci_command_verify(ahci, cmd);
719 ahci_command_free(cmd);
720}
721
722
723void ahci_guest_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
724 uint64_t buffer, size_t bufsize, uint64_t sector)
725{
726 AHCICommand *cmd;
727 cmd = ahci_command_create(ide_cmd);
728 ahci_command_set_buffer(cmd, buffer);
729 ahci_command_set_size(cmd, bufsize);
730 if (sector) {
731 ahci_command_set_offset(cmd, sector);
732 }
733 ahci_command_commit(ahci, cmd, port);
734 ahci_command_issue(ahci, cmd);
735 ahci_command_verify(ahci, cmd);
736 ahci_command_free(cmd);
737}
738
739static AHCICommandProp *ahci_command_find(uint8_t command_name)
740{
741 int i;
742
743 for (i = 0; i < ARRAY_SIZE(ahci_command_properties); i++) {
744 if (ahci_command_properties[i].cmd == command_name) {
745 return &ahci_command_properties[i];
746 }
747 }
748
749 return NULL;
750}
751
752
753void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
754 void *buffer, size_t bufsize, uint64_t sector)
755{
756 uint64_t ptr;
757 AHCICommandProp *props;
758
759 props = ahci_command_find(ide_cmd);
760 g_assert(props);
761 ptr = ahci_alloc(ahci, bufsize);
762 g_assert(!bufsize || ptr);
763 qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize);
764
765 if (bufsize && props->write) {
766 qtest_bufwrite(ahci->parent->qts, ptr, buffer, bufsize);
767 }
768
769 ahci_guest_io(ahci, port, ide_cmd, ptr, bufsize, sector);
770
771 if (bufsize && props->read) {
772 qtest_bufread(ahci->parent->qts, ptr, buffer, bufsize);
773 }
774
775 ahci_free(ahci, ptr);
776}
777
778
779
780
781
782static void command_header_init(AHCICommand *cmd)
783{
784 AHCICommandHeader *hdr = &cmd->header;
785 AHCICommandProp *props = cmd->props;
786
787 hdr->flags = 5;
788 hdr->flags |= CMDH_CLR_BSY;
789 if (props->write) {
790 hdr->flags |= CMDH_WRITE;
791 }
792 if (props->atapi) {
793 hdr->flags |= CMDH_ATAPI;
794 }
795
796 hdr->prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
797 hdr->prdbc = 0;
798 hdr->ctba = 0;
799}
800
801static void command_table_init(AHCICommand *cmd)
802{
803 RegH2DFIS *fis = &(cmd->fis);
804 uint16_t sect_count = (cmd->xbytes / cmd->sector_size);
805
806 fis->fis_type = REG_H2D_FIS;
807 fis->flags = REG_H2D_FIS_CMD;
808 fis->command = cmd->name;
809
810 if (cmd->props->ncq) {
811 NCQFIS *ncqfis = (NCQFIS *)fis;
812
813
814 ncqfis->sector_low = sect_count & 0xFF;
815 ncqfis->sector_hi = (sect_count >> 8) & 0xFF;
816 ncqfis->device = NCQ_DEVICE_MAGIC;
817
818 ncqfis->tag = 0;
819 ncqfis->prio = 0;
820
821 } else {
822 fis->feature_low = 0x00;
823 fis->feature_high = 0x00;
824 if (cmd->props->lba28 || cmd->props->lba48) {
825 fis->device = ATA_DEVICE_LBA;
826 }
827 fis->count = (cmd->xbytes / cmd->sector_size);
828 }
829 fis->icc = 0x00;
830 fis->control = 0x00;
831 memset(fis->aux, 0x00, ARRAY_SIZE(fis->aux));
832}
833
834void ahci_command_enable_atapi_dma(AHCICommand *cmd)
835{
836 RegH2DFIS *fis = &(cmd->fis);
837 g_assert(cmd->props->atapi);
838 fis->feature_low |= 0x01;
839
840 g_assert(cmd->props->pio);
841 cmd->props->dma = true;
842
843
844}
845
846AHCICommand *ahci_command_create(uint8_t command_name)
847{
848 AHCICommandProp *props = ahci_command_find(command_name);
849 AHCICommand *cmd;
850
851 g_assert(props);
852 cmd = g_new0(AHCICommand, 1);
853 g_assert(!(props->dma && props->pio) || props->atapi);
854 g_assert(!(props->lba28 && props->lba48));
855 g_assert(!(props->read && props->write));
856 g_assert(!props->size || props->data);
857 g_assert(!props->ncq || props->lba48);
858
859
860 cmd->props = g_memdup(props, sizeof(AHCICommandProp));
861 cmd->name = command_name;
862 cmd->xbytes = props->size;
863 cmd->prd_size = 4096;
864 cmd->buffer = 0xabad1dea;
865 cmd->sector_size = props->atapi ? ATAPI_SECTOR_SIZE : AHCI_SECTOR_SIZE;
866
867 if (!cmd->props->ncq) {
868 cmd->interrupts = AHCI_PX_IS_DHRS;
869 }
870
871
872
873
874 cmd->interrupts |= props->ncq ? AHCI_PX_IS_SDBS : 0;
875
876 command_header_init(cmd);
877 command_table_init(cmd);
878
879 return cmd;
880}
881
882AHCICommand *ahci_atapi_command_create(uint8_t scsi_cmd, uint16_t bcl, bool dma)
883{
884 AHCICommand *cmd = ahci_command_create(CMD_PACKET);
885 cmd->atapi_cmd = g_malloc0(16);
886 cmd->atapi_cmd[0] = scsi_cmd;
887 stw_le_p(&cmd->fis.lba_lo[1], bcl);
888 if (dma) {
889 ahci_command_enable_atapi_dma(cmd);
890 } else {
891 cmd->interrupts |= bcl ? AHCI_PX_IS_PSS : 0;
892 }
893 return cmd;
894}
895
896void ahci_atapi_test_ready(AHCIQState *ahci, uint8_t port,
897 bool ready, uint8_t expected_sense)
898{
899 AHCICommand *cmd = ahci_atapi_command_create(CMD_ATAPI_TEST_UNIT_READY, 0, false);
900 ahci_command_set_size(cmd, 0);
901 if (!ready) {
902 cmd->interrupts |= AHCI_PX_IS_TFES;
903 cmd->errors |= expected_sense << 4;
904 }
905 ahci_command_commit(ahci, cmd, port);
906 ahci_command_issue(ahci, cmd);
907 ahci_command_verify(ahci, cmd);
908 ahci_command_free(cmd);
909}
910
911static int copy_buffer(AHCIQState *ahci, AHCICommand *cmd,
912 const AHCIOpts *opts)
913{
914 unsigned char *rx = opts->opaque;
915 qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size);
916 return 0;
917}
918
919void ahci_atapi_get_sense(AHCIQState *ahci, uint8_t port,
920 uint8_t *sense, uint8_t *asc)
921{
922 unsigned char *rx;
923 AHCIOpts opts = {
924 .size = 18,
925 .atapi = true,
926 .post_cb = copy_buffer,
927 };
928 rx = g_malloc(18);
929 opts.opaque = rx;
930
931 ahci_exec(ahci, port, CMD_ATAPI_REQUEST_SENSE, &opts);
932
933 *sense = rx[2];
934 *asc = rx[12];
935
936 g_free(rx);
937}
938
939void ahci_atapi_eject(AHCIQState *ahci, uint8_t port)
940{
941 AHCICommand *cmd = ahci_atapi_command_create(CMD_ATAPI_START_STOP_UNIT, 0, false);
942 ahci_command_set_size(cmd, 0);
943
944 cmd->atapi_cmd[4] = 0x02;
945 ahci_command_commit(ahci, cmd, port);
946 ahci_command_issue(ahci, cmd);
947 ahci_command_verify(ahci, cmd);
948 ahci_command_free(cmd);
949}
950
951void ahci_atapi_load(AHCIQState *ahci, uint8_t port)
952{
953 AHCICommand *cmd = ahci_atapi_command_create(CMD_ATAPI_START_STOP_UNIT, 0, false);
954 ahci_command_set_size(cmd, 0);
955
956 cmd->atapi_cmd[4] = 0x03;
957 ahci_command_commit(ahci, cmd, port);
958 ahci_command_issue(ahci, cmd);
959 ahci_command_verify(ahci, cmd);
960 ahci_command_free(cmd);
961}
962
963void ahci_command_free(AHCICommand *cmd)
964{
965 g_free(cmd->atapi_cmd);
966 g_free(cmd->props);
967 g_free(cmd);
968}
969
970void ahci_command_set_flags(AHCICommand *cmd, uint16_t cmdh_flags)
971{
972 cmd->header.flags |= cmdh_flags;
973}
974
975void ahci_command_clr_flags(AHCICommand *cmd, uint16_t cmdh_flags)
976{
977 cmd->header.flags &= ~cmdh_flags;
978}
979
980static void ahci_atapi_command_set_offset(AHCICommand *cmd, uint64_t lba)
981{
982 unsigned char *cbd = cmd->atapi_cmd;
983 g_assert(cbd);
984
985 switch (cbd[0]) {
986 case CMD_ATAPI_READ_10:
987 case CMD_ATAPI_READ_CD:
988 g_assert_cmpuint(lba, <=, UINT32_MAX);
989 stl_be_p(&cbd[2], lba);
990 break;
991 case CMD_ATAPI_REQUEST_SENSE:
992 case CMD_ATAPI_TEST_UNIT_READY:
993 case CMD_ATAPI_START_STOP_UNIT:
994 g_assert_cmpuint(lba, ==, 0x00);
995 break;
996 default:
997
998
999 fprintf(stderr, "The Libqos AHCI driver does not support the "
1000 "set_offset operation for ATAPI command 0x%02x, "
1001 "please add support.\n",
1002 cbd[0]);
1003 g_assert_not_reached();
1004 }
1005}
1006
1007void ahci_command_set_offset(AHCICommand *cmd, uint64_t lba_sect)
1008{
1009 RegH2DFIS *fis = &(cmd->fis);
1010
1011 if (cmd->props->atapi) {
1012 ahci_atapi_command_set_offset(cmd, lba_sect);
1013 return;
1014 } else if (!cmd->props->data && !lba_sect) {
1015
1016 return;
1017 } else if (cmd->props->lba28) {
1018 g_assert_cmphex(lba_sect, <=, 0xFFFFFFF);
1019 } else if (cmd->props->lba48 || cmd->props->ncq) {
1020 g_assert_cmphex(lba_sect, <=, 0xFFFFFFFFFFFF);
1021 } else {
1022
1023 g_assert_not_reached();
1024 }
1025
1026
1027 fis->lba_lo[0] = (lba_sect & 0xFF);
1028 fis->lba_lo[1] = (lba_sect >> 8) & 0xFF;
1029 fis->lba_lo[2] = (lba_sect >> 16) & 0xFF;
1030 if (cmd->props->lba28) {
1031 fis->device = (fis->device & 0xF0) | ((lba_sect >> 24) & 0x0F);
1032 }
1033 fis->lba_hi[0] = (lba_sect >> 24) & 0xFF;
1034 fis->lba_hi[1] = (lba_sect >> 32) & 0xFF;
1035 fis->lba_hi[2] = (lba_sect >> 40) & 0xFF;
1036}
1037
1038void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer)
1039{
1040 cmd->buffer = buffer;
1041}
1042
1043static void ahci_atapi_set_size(AHCICommand *cmd, uint64_t xbytes)
1044{
1045 unsigned char *cbd = cmd->atapi_cmd;
1046 uint64_t nsectors = xbytes / ATAPI_SECTOR_SIZE;
1047 uint32_t tmp;
1048 g_assert(cbd);
1049
1050 switch (cbd[0]) {
1051 case CMD_ATAPI_READ_10:
1052 g_assert_cmpuint(nsectors, <=, UINT16_MAX);
1053 stw_be_p(&cbd[7], nsectors);
1054 break;
1055 case CMD_ATAPI_READ_CD:
1056
1057 g_assert_cmpuint(nsectors, <, 1ULL << 24);
1058 tmp = nsectors;
1059 cbd[6] = (tmp & 0xFF0000) >> 16;
1060 cbd[7] = (tmp & 0xFF00) >> 8;
1061 cbd[8] = (tmp & 0xFF);
1062 break;
1063 case CMD_ATAPI_REQUEST_SENSE:
1064 g_assert_cmpuint(xbytes, <=, UINT8_MAX);
1065 cbd[4] = (uint8_t)xbytes;
1066 break;
1067 case CMD_ATAPI_TEST_UNIT_READY:
1068 case CMD_ATAPI_START_STOP_UNIT:
1069 g_assert_cmpuint(xbytes, ==, 0);
1070 break;
1071 default:
1072
1073
1074 fprintf(stderr, "The Libqos AHCI driver does not support the set_size "
1075 "operation for ATAPI command 0x%02x, please add support.\n",
1076 cbd[0]);
1077 g_assert_not_reached();
1078 }
1079}
1080
1081void ahci_command_set_sizes(AHCICommand *cmd, uint64_t xbytes,
1082 unsigned prd_size)
1083{
1084 uint16_t sect_count;
1085
1086
1087 g_assert_cmphex(prd_size, <=, 4096 * 1024);
1088 g_assert_cmphex(prd_size & 0x01, ==, 0x00);
1089 if (prd_size) {
1090 cmd->prd_size = prd_size;
1091 }
1092 cmd->xbytes = xbytes;
1093 sect_count = (cmd->xbytes / cmd->sector_size);
1094
1095 if (cmd->props->ncq) {
1096 NCQFIS *nfis = (NCQFIS *)&(cmd->fis);
1097 nfis->sector_low = sect_count & 0xFF;
1098 nfis->sector_hi = (sect_count >> 8) & 0xFF;
1099 } else if (cmd->props->atapi) {
1100 ahci_atapi_set_size(cmd, xbytes);
1101 } else {
1102
1103
1104
1105 if (cmd->props->pio && sect_count > (cmd->props->read ? 0 : 1)) {
1106 cmd->interrupts |= AHCI_PX_IS_PSS;
1107 }
1108 cmd->fis.count = sect_count;
1109 }
1110 cmd->header.prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
1111}
1112
1113void ahci_command_set_size(AHCICommand *cmd, uint64_t xbytes)
1114{
1115 ahci_command_set_sizes(cmd, xbytes, cmd->prd_size);
1116}
1117
1118void ahci_command_set_prd_size(AHCICommand *cmd, unsigned prd_size)
1119{
1120 ahci_command_set_sizes(cmd, cmd->xbytes, prd_size);
1121}
1122
1123void ahci_command_adjust(AHCICommand *cmd, uint64_t offset, uint64_t buffer,
1124 uint64_t xbytes, unsigned prd_size)
1125{
1126 ahci_command_set_sizes(cmd, xbytes, prd_size);
1127 ahci_command_set_buffer(cmd, buffer);
1128 ahci_command_set_offset(cmd, offset);
1129}
1130
1131void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)
1132{
1133 uint16_t i, prdtl;
1134 uint64_t table_size, table_ptr, remaining;
1135 PRD prd;
1136
1137
1138 cmd->port = port;
1139 cmd->slot = ahci_pick_cmd(ahci, port);
1140
1141 if (cmd->props->ncq) {
1142 NCQFIS *nfis = (NCQFIS *)&cmd->fis;
1143 nfis->tag = (cmd->slot << 3) & 0xFC;
1144 }
1145
1146
1147 prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
1148 table_size = CMD_TBL_SIZ(prdtl);
1149 table_ptr = ahci_alloc(ahci, table_size);
1150 g_assert(table_ptr);
1151
1152 g_assert((table_ptr & 0x7F) == 0x00);
1153 cmd->header.ctba = table_ptr;
1154
1155
1156 ahci_set_command_header(ahci, port, cmd->slot, &(cmd->header));
1157
1158 ahci_write_fis(ahci, cmd);
1159
1160 if (cmd->props->atapi) {
1161 qtest_memwrite(ahci->parent->qts, table_ptr + 0x40, cmd->atapi_cmd, 16);
1162 }
1163
1164
1165 g_assert_cmphex(prdtl, ==, cmd->header.prdtl);
1166 remaining = cmd->xbytes;
1167 for (i = 0; i < prdtl; ++i) {
1168 prd.dba = cpu_to_le64(cmd->buffer + (cmd->prd_size * i));
1169 prd.res = 0;
1170 if (remaining > cmd->prd_size) {
1171
1172 prd.dbc = cpu_to_le32(cmd->prd_size - 1);
1173 remaining -= cmd->prd_size;
1174 } else {
1175
1176 prd.dbc = cpu_to_le32(remaining - 1);
1177 remaining = 0;
1178 }
1179 prd.dbc |= cpu_to_le32(0x80000000);
1180
1181
1182 qtest_memwrite(ahci->parent->qts, table_ptr + 0x80 + (i * sizeof(PRD)),
1183 &prd, sizeof(PRD));
1184 }
1185
1186
1187 ahci->port[port].ctba[cmd->slot] = table_ptr;
1188 ahci->port[port].prdtl[cmd->slot] = prdtl;
1189}
1190
1191void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd)
1192{
1193 if (cmd->props->ncq) {
1194 ahci_px_wreg(ahci, cmd->port, AHCI_PX_SACT, (1 << cmd->slot));
1195 }
1196
1197 ahci_px_wreg(ahci, cmd->port, AHCI_PX_CI, (1 << cmd->slot));
1198}
1199
1200void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd)
1201{
1202
1203
1204
1205
1206#define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK)))
1207
1208 while (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) ||
1209 RSET(AHCI_PX_CI, 1 << cmd->slot) ||
1210 (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot))) {
1211 usleep(50);
1212 }
1213
1214}
1215
1216void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd)
1217{
1218 ahci_command_issue_async(ahci, cmd);
1219 ahci_command_wait(ahci, cmd);
1220}
1221
1222void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd)
1223{
1224 uint8_t slot = cmd->slot;
1225 uint8_t port = cmd->port;
1226
1227 ahci_port_check_error(ahci, port, cmd->interrupts, cmd->errors);
1228 ahci_port_check_interrupts(ahci, port, cmd->interrupts);
1229 ahci_port_check_nonbusy(ahci, port, slot);
1230 ahci_port_check_cmd_sanity(ahci, cmd);
1231 if (cmd->interrupts & AHCI_PX_IS_DHRS) {
1232 ahci_port_check_d2h_sanity(ahci, port, slot);
1233 }
1234 if (cmd->props->pio) {
1235 ahci_port_check_pio_sanity(ahci, cmd);
1236 }
1237}
1238
1239uint8_t ahci_command_slot(AHCICommand *cmd)
1240{
1241 return cmd->slot;
1242}
1243