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25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qapi/error.h"
28#include "exec/address-spaces.h"
29#include "hw/char/serial.h"
30#include "hw/boards.h"
31#include "hw/arm/msf2-soc.h"
32#include "hw/misc/unimp.h"
33
34#define MSF2_TIMER_BASE 0x40004000
35#define MSF2_SYSREG_BASE 0x40038000
36
37#define ENVM_BASE_ADDRESS 0x60000000
38
39#define SRAM_BASE_ADDRESS 0x20000000
40
41#define MSF2_ENVM_MAX_SIZE (512 * KiB)
42
43
44
45
46
47
48#define MSF2_ESRAM_MAX_SIZE (80 * KiB)
49
50static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
51static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
52
53static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
54static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
55static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
56
57static void do_sys_reset(void *opaque, int n, int level)
58{
59 if (level) {
60 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
61 }
62}
63
64static void m2sxxx_soc_initfn(Object *obj)
65{
66 MSF2State *s = MSF2_SOC(obj);
67 int i;
68
69 sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
70 TYPE_ARMV7M);
71
72 sysbus_init_child_obj(obj, "sysreg", &s->sysreg, sizeof(s->sysreg),
73 TYPE_MSF2_SYSREG);
74
75 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
76 TYPE_MSS_TIMER);
77
78 for (i = 0; i < MSF2_NUM_SPIS; i++) {
79 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
80 TYPE_MSS_SPI);
81 }
82}
83
84static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
85{
86 MSF2State *s = MSF2_SOC(dev_soc);
87 DeviceState *dev, *armv7m;
88 SysBusDevice *busdev;
89 Error *err = NULL;
90 int i;
91
92 MemoryRegion *system_memory = get_system_memory();
93 MemoryRegion *nvm = g_new(MemoryRegion, 1);
94 MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
95 MemoryRegion *sram = g_new(MemoryRegion, 1);
96
97 memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
98 &error_fatal);
99
100
101
102
103
104
105 memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
106 nvm, 0, s->envm_size);
107
108 memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
109 memory_region_add_subregion(system_memory, 0, nvm_alias);
110
111 memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
112 &error_fatal);
113 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
114
115 armv7m = DEVICE(&s->armv7m);
116 qdev_prop_set_uint32(armv7m, "num-irq", 81);
117 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
118 qdev_prop_set_bit(armv7m, "enable-bitband", true);
119 object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
120 "memory", &error_abort);
121 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
122 if (err != NULL) {
123 error_propagate(errp, err);
124 return;
125 }
126
127 if (!s->m3clk) {
128 error_setg(errp, "Invalid m3clk value");
129 error_append_hint(errp, "m3clk can not be zero\n");
130 return;
131 }
132
133 qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
134 qemu_allocate_irq(&do_sys_reset, NULL, 0));
135
136 system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
137
138 for (i = 0; i < MSF2_NUM_UARTS; i++) {
139 if (serial_hd(i)) {
140 serial_mm_init(get_system_memory(), uart_addr[i], 2,
141 qdev_get_gpio_in(armv7m, uart_irq[i]),
142 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
143 }
144 }
145
146 dev = DEVICE(&s->timer);
147
148 qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
149 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
150 if (err != NULL) {
151 error_propagate(errp, err);
152 return;
153 }
154 busdev = SYS_BUS_DEVICE(dev);
155 sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
156 sysbus_connect_irq(busdev, 0,
157 qdev_get_gpio_in(armv7m, timer_irq[0]));
158 sysbus_connect_irq(busdev, 1,
159 qdev_get_gpio_in(armv7m, timer_irq[1]));
160
161 dev = DEVICE(&s->sysreg);
162 qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
163 qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
164 object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
165 if (err != NULL) {
166 error_propagate(errp, err);
167 return;
168 }
169 busdev = SYS_BUS_DEVICE(dev);
170 sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
171
172 for (i = 0; i < MSF2_NUM_SPIS; i++) {
173 gchar *bus_name;
174
175 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
176 if (err != NULL) {
177 error_propagate(errp, err);
178 return;
179 }
180
181 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
182 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
183 qdev_get_gpio_in(armv7m, spi_irq[i]));
184
185
186 bus_name = g_strdup_printf("spi%d", i);
187 object_property_add_alias(OBJECT(s), bus_name,
188 OBJECT(&s->spi[i]), "spi",
189 &error_abort);
190 g_free(bus_name);
191 }
192
193
194 create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
195 create_unimplemented_device("dma", 0x40003000, 0x1000);
196 create_unimplemented_device("watchdog", 0x40005000, 0x1000);
197 create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
198 create_unimplemented_device("gpio", 0x40013000, 0x1000);
199 create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
200 create_unimplemented_device("can", 0x40015000, 0x1000);
201 create_unimplemented_device("rtc", 0x40017000, 0x1000);
202 create_unimplemented_device("apb_config", 0x40020000, 0x10000);
203 create_unimplemented_device("emac", 0x40041000, 0x1000);
204 create_unimplemented_device("usb", 0x40043000, 0x1000);
205}
206
207static Property m2sxxx_soc_properties[] = {
208
209
210
211
212 DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
213 DEFINE_PROP_STRING("part-name", MSF2State, part_name),
214 DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
215 DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
216 MSF2_ESRAM_MAX_SIZE),
217
218 DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
219
220 DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
221 DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
222 DEFINE_PROP_END_OF_LIST(),
223};
224
225static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
226{
227 DeviceClass *dc = DEVICE_CLASS(klass);
228
229 dc->realize = m2sxxx_soc_realize;
230 dc->props = m2sxxx_soc_properties;
231}
232
233static const TypeInfo m2sxxx_soc_info = {
234 .name = TYPE_MSF2_SOC,
235 .parent = TYPE_SYS_BUS_DEVICE,
236 .instance_size = sizeof(MSF2State),
237 .instance_init = m2sxxx_soc_initfn,
238 .class_init = m2sxxx_soc_class_init,
239};
240
241static void m2sxxx_soc_types(void)
242{
243 type_register_static(&m2sxxx_soc_info);
244}
245
246type_init(m2sxxx_soc_types)
247
