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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "cpu.h"
24#include "qemu/cutils.h"
25#include "qemu/bswap.h"
26#include "sysemu/sysemu.h"
27#include "hw/arm/omap.h"
28#include "hw/arm/boot.h"
29#include "hw/irq.h"
30#include "ui/console.h"
31#include "hw/boards.h"
32#include "hw/i2c/i2c.h"
33#include "hw/display/blizzard.h"
34#include "hw/input/tsc2xxx.h"
35#include "hw/misc/cbus.h"
36#include "hw/misc/tmp105.h"
37#include "hw/block/flash.h"
38#include "hw/hw.h"
39#include "hw/bt.h"
40#include "hw/loader.h"
41#include "hw/sysbus.h"
42#include "qemu/log.h"
43#include "exec/address-spaces.h"
44
45
46struct n800_s {
47 struct omap_mpu_state_s *mpu;
48
49 struct rfbi_chip_s blizzard;
50 struct {
51 void *opaque;
52 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
53 uWireSlave *chip;
54 } ts;
55
56 int keymap[0x80];
57 DeviceState *kbd;
58
59 DeviceState *usb;
60 void *retu;
61 void *tahvo;
62 DeviceState *nand;
63};
64
65
66#define N8X0_TUSB_ENABLE_GPIO 0
67#define N800_MMC2_WP_GPIO 8
68#define N800_UNKNOWN_GPIO0 9
69#define N810_MMC2_VIOSD_GPIO 9
70#define N810_HEADSET_AMP_GPIO 10
71#define N800_CAM_TURN_GPIO 12
72#define N810_GPS_RESET_GPIO 12
73#define N800_BLIZZARD_POWERDOWN_GPIO 15
74#define N800_MMC1_WP_GPIO 23
75#define N810_MMC2_VSD_GPIO 23
76#define N8X0_ONENAND_GPIO 26
77#define N810_BLIZZARD_RESET_GPIO 30
78#define N800_UNKNOWN_GPIO2 53
79#define N8X0_TUSB_INT_GPIO 58
80#define N8X0_BT_WKUP_GPIO 61
81#define N8X0_STI_GPIO 62
82#define N8X0_CBUS_SEL_GPIO 64
83#define N8X0_CBUS_DAT_GPIO 65
84#define N8X0_CBUS_CLK_GPIO 66
85#define N8X0_WLAN_IRQ_GPIO 87
86#define N8X0_BT_RESET_GPIO 92
87#define N8X0_TEA5761_CS_GPIO 93
88#define N800_UNKNOWN_GPIO 94
89#define N810_TSC_RESET_GPIO 94
90#define N800_CAM_ACT_GPIO 95
91#define N810_GPS_WAKEUP_GPIO 95
92#define N8X0_MMC_CS_GPIO 96
93#define N8X0_WLAN_PWR_GPIO 97
94#define N8X0_BT_HOST_WKUP_GPIO 98
95#define N810_SPEAKER_AMP_GPIO 101
96#define N810_KB_LOCK_GPIO 102
97#define N800_TSC_TS_GPIO 103
98#define N810_TSC_TS_GPIO 106
99#define N8X0_HEADPHONE_GPIO 107
100#define N8X0_RETU_GPIO 108
101#define N800_TSC_KP_IRQ_GPIO 109
102#define N810_KEYBOARD_GPIO 109
103#define N800_BAT_COVER_GPIO 110
104#define N810_SLIDE_GPIO 110
105#define N8X0_TAHVO_GPIO 111
106#define N800_UNKNOWN_GPIO4 112
107#define N810_SLEEPX_LED_GPIO 112
108#define N800_TSC_RESET_GPIO 118
109#define N810_AIC33_RESET_GPIO 118
110#define N800_TSC_UNKNOWN_GPIO 119
111#define N8X0_TMP105_GPIO 125
112
113
114#define BT_UART 0
115#define XLDR_LL_UART 1
116
117
118#define N810_TLV320AIC33_ADDR 0x18
119#define N8X0_TCM825x_ADDR 0x29
120#define N810_LP5521_ADDR 0x32
121#define N810_TSL2563_ADDR 0x3d
122#define N810_LM8323_ADDR 0x45
123
124#define N8X0_TMP105_ADDR 0x48
125#define N8X0_MENELAUS_ADDR 0x72
126
127
128#define N8X0_ONENAND_CS 0
129#define N8X0_USB_ASYNC_CS 1
130#define N8X0_USB_SYNC_CS 4
131
132#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
133
134static void n800_mmc_cs_cb(void *opaque, int line, int level)
135{
136
137
138 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
139}
140
141static void n8x0_gpio_setup(struct n800_s *s)
142{
143 qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO,
144 qemu_allocate_irq(n800_mmc_cs_cb, s->mpu->mmc, 0));
145 qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
146}
147
148#define MAEMO_CAL_HEADER(...) \
149 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
150 __VA_ARGS__, \
151 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
152
153static const uint8_t n8x0_cal_wlan_mac[] = {
154 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
155 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
156 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
157 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
158 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
159 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
160};
161
162static const uint8_t n8x0_cal_bt_id[] = {
163 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
164 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
165 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
166 N8X0_BD_ADDR,
167};
168
169static void n8x0_nand_setup(struct n800_s *s)
170{
171 char *otp_region;
172 DriveInfo *dinfo;
173
174 s->nand = qdev_create(NULL, "onenand");
175 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
176
177 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
178 qdev_prop_set_uint16(s->nand, "version_id", 0);
179 qdev_prop_set_int32(s->nand, "shift", 1);
180 dinfo = drive_get(IF_MTD, 0, 0);
181 if (dinfo) {
182 qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo),
183 &error_fatal);
184 }
185 qdev_init_nofail(s->nand);
186 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
187 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
188 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
189 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
190 otp_region = onenand_raw_otp(s->nand);
191
192 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
193 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
194
195}
196
197static qemu_irq n8x0_system_powerdown;
198
199static void n8x0_powerdown_req(Notifier *n, void *opaque)
200{
201 qemu_irq_raise(n8x0_system_powerdown);
202}
203
204static Notifier n8x0_system_powerdown_notifier = {
205 .notify = n8x0_powerdown_req
206};
207
208static void n8x0_i2c_setup(struct n800_s *s)
209{
210 DeviceState *dev;
211 qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
212 I2CBus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
213
214
215 dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
216 qdev_connect_gpio_out(dev, 3,
217 qdev_get_gpio_in(s->mpu->ih[0],
218 OMAP_INT_24XX_SYS_NIRQ));
219
220 n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
221 qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
222
223
224 dev = i2c_create_slave(i2c, TYPE_TMP105, N8X0_TMP105_ADDR);
225 qdev_connect_gpio_out(dev, 0, tmp_irq);
226}
227
228
229static MouseTransformInfo n800_pointercal = {
230 .x = 800,
231 .y = 480,
232 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
233};
234
235static MouseTransformInfo n810_pointercal = {
236 .x = 800,
237 .y = 480,
238 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
239};
240
241#define RETU_KEYCODE 61
242
243static void n800_key_event(void *opaque, int keycode)
244{
245 struct n800_s *s = (struct n800_s *) opaque;
246 int code = s->keymap[keycode & 0x7f];
247
248 if (code == -1) {
249 if ((keycode & 0x7f) == RETU_KEYCODE) {
250 retu_key_event(s->retu, !(keycode & 0x80));
251 }
252 return;
253 }
254
255 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
256}
257
258static const int n800_keys[16] = {
259 -1,
260 72,
261 63,
262 -1,
263 75,
264 28,
265 77,
266 -1,
267 1,
268 80,
269 62,
270 -1,
271 66,
272 64,
273 65,
274 -1,
275};
276
277static void n800_tsc_kbd_setup(struct n800_s *s)
278{
279 int i;
280
281
282
283 qemu_irq penirq = NULL;
284 qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO);
285 qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO);
286
287 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
288 s->ts.opaque = s->ts.chip->opaque;
289 s->ts.txrx = tsc210x_txrx;
290
291 for (i = 0; i < 0x80; i++) {
292 s->keymap[i] = -1;
293 }
294 for (i = 0; i < 0x10; i++) {
295 if (n800_keys[i] >= 0) {
296 s->keymap[n800_keys[i]] = i;
297 }
298 }
299
300 qemu_add_kbd_event_handler(n800_key_event, s);
301
302 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
303}
304
305static void n810_tsc_setup(struct n800_s *s)
306{
307 qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO);
308
309 s->ts.opaque = tsc2005_init(pintdav);
310 s->ts.txrx = tsc2005_txrx;
311
312 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
313}
314
315
316static void n810_key_event(void *opaque, int keycode)
317{
318 struct n800_s *s = (struct n800_s *) opaque;
319 int code = s->keymap[keycode & 0x7f];
320
321 if (code == -1) {
322 if ((keycode & 0x7f) == RETU_KEYCODE) {
323 retu_key_event(s->retu, !(keycode & 0x80));
324 }
325 return;
326 }
327
328 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
329}
330
331#define M 0
332
333static int n810_keys[0x80] = {
334 [0x01] = 16,
335 [0x02] = 37,
336 [0x03] = 24,
337 [0x04] = 25,
338 [0x05] = 14,
339 [0x06] = 30,
340 [0x07] = 31,
341 [0x08] = 32,
342 [0x09] = 33,
343 [0x0a] = 34,
344 [0x0b] = 35,
345 [0x0c] = 36,
346
347 [0x11] = 17,
348 [0x12] = 62,
349 [0x13] = 38,
350 [0x14] = 40,
351 [0x16] = 44,
352 [0x17] = 45,
353 [0x18] = 46,
354 [0x19] = 47,
355 [0x1a] = 48,
356 [0x1b] = 49,
357 [0x1c] = 42,
358 [0x1f] = 65,
359
360 [0x21] = 18,
361 [0x22] = 39,
362 [0x23] = 12,
363 [0x24] = 13,
364 [0x2b] = 56,
365 [0x2c] = 50,
366 [0x2f] = 66,
367
368 [0x31] = 19,
369 [0x32] = 29 | M,
370 [0x34] = 57,
371 [0x35] = 51,
372 [0x37] = 72 | M,
373 [0x3c] = 82 | M,
374 [0x3f] = 64,
375
376 [0x41] = 20,
377 [0x44] = 52,
378 [0x46] = 77 | M,
379 [0x4f] = 63,
380 [0x51] = 21,
381 [0x53] = 80 | M,
382 [0x55] = 28,
383 [0x5f] = 1,
384
385 [0x61] = 22,
386 [0x64] = 75 | M,
387
388 [0x71] = 23,
389#if 0
390 [0x75] = 28 | M,
391#else
392 [0x75] = 15,
393#endif
394};
395
396#undef M
397
398static void n810_kbd_setup(struct n800_s *s)
399{
400 qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
401 int i;
402
403 for (i = 0; i < 0x80; i++) {
404 s->keymap[i] = -1;
405 }
406 for (i = 0; i < 0x80; i++) {
407 if (n810_keys[i] > 0) {
408 s->keymap[n810_keys[i]] = i;
409 }
410 }
411
412 qemu_add_kbd_event_handler(n810_key_event, s);
413
414
415
416 s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
417 "lm8323", N810_LM8323_ADDR);
418 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
419}
420
421
422struct mipid_s {
423 int resp[4];
424 int param[4];
425 int p;
426 int pm;
427 int cmd;
428
429 int sleep;
430 int booster;
431 int te;
432 int selfcheck;
433 int partial;
434 int normal;
435 int vscr;
436 int invert;
437 int onoff;
438 int gamma;
439 uint32_t id;
440};
441
442static void mipid_reset(struct mipid_s *s)
443{
444 s->pm = 0;
445 s->cmd = 0;
446
447 s->sleep = 1;
448 s->booster = 0;
449 s->selfcheck =
450 (1 << 7) |
451 (1 << 5) |
452 (1 << 4);
453 s->te = 0;
454 s->partial = 0;
455 s->normal = 1;
456 s->vscr = 0;
457 s->invert = 0;
458 s->onoff = 1;
459 s->gamma = 0;
460}
461
462static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
463{
464 struct mipid_s *s = (struct mipid_s *) opaque;
465 uint8_t ret;
466
467 if (len > 9) {
468 hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len);
469 }
470
471 if (s->p >= ARRAY_SIZE(s->resp)) {
472 ret = 0;
473 } else {
474 ret = s->resp[s->p++];
475 }
476 if (s->pm-- > 0) {
477 s->param[s->pm] = cmd;
478 } else {
479 s->cmd = cmd;
480 }
481
482 switch (s->cmd) {
483 case 0x00:
484 break;
485
486 case 0x01:
487 mipid_reset(s);
488 break;
489
490 case 0x02:
491 s->booster = 0;
492 break;
493 case 0x03:
494 s->booster = 1;
495 break;
496
497 case 0x04:
498 s->p = 0;
499 s->resp[0] = (s->id >> 16) & 0xff;
500 s->resp[1] = (s->id >> 8) & 0xff;
501 s->resp[2] = (s->id >> 0) & 0xff;
502 break;
503
504 case 0x06:
505 case 0x07:
506
507
508 case 0x08:
509 s->p = 0;
510
511 s->resp[0] = 0x01;
512 break;
513
514 case 0x09:
515 s->p = 0;
516 s->resp[0] = s->booster << 7;
517 s->resp[1] = (5 << 4) | (s->partial << 2) |
518 (s->sleep << 1) | s->normal;
519 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
520 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
521 s->resp[3] = s->gamma << 6;
522 break;
523
524 case 0x0a:
525 s->p = 0;
526 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
527 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
528 break;
529 case 0x0b:
530 s->p = 0;
531 s->resp[0] = 0;
532 break;
533 case 0x0c:
534 s->p = 0;
535 s->resp[0] = 5;
536 break;
537 case 0x0d:
538 s->p = 0;
539 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
540 break;
541 case 0x0e:
542 s->p = 0;
543 s->resp[0] = s->te << 7;
544 break;
545 case 0x0f:
546 s->p = 0;
547 s->resp[0] = s->selfcheck;
548 break;
549
550 case 0x10:
551 s->sleep = 1;
552 break;
553 case 0x11:
554 s->sleep = 0;
555 s->selfcheck ^= 1 << 6;
556 break;
557
558 case 0x12:
559 s->partial = 1;
560 s->normal = 0;
561 s->vscr = 0;
562 break;
563 case 0x13:
564 s->partial = 0;
565 s->normal = 1;
566 s->vscr = 0;
567 break;
568
569 case 0x20:
570 s->invert = 0;
571 break;
572 case 0x21:
573 s->invert = 1;
574 break;
575
576 case 0x22:
577 case 0x23:
578 goto bad_cmd;
579
580 case 0x25:
581 if (s->pm < 0) {
582 s->pm = 1;
583 }
584 goto bad_cmd;
585
586 case 0x26:
587 if (!s->pm) {
588 s->gamma = ctz32(s->param[0] & 0xf);
589 if (s->gamma == 32) {
590 s->gamma = -1;
591 }
592 } else if (s->pm < 0) {
593 s->pm = 1;
594 }
595 break;
596
597 case 0x28:
598 s->onoff = 0;
599 break;
600 case 0x29:
601 s->onoff = 1;
602 break;
603
604 case 0x2a:
605 case 0x2b:
606 case 0x2c:
607 case 0x2d:
608 case 0x2e:
609 case 0x30:
610 case 0x33:
611 goto bad_cmd;
612
613 case 0x34:
614 s->te = 0;
615 break;
616 case 0x35:
617 if (!s->pm) {
618 s->te = 1;
619 } else if (s->pm < 0) {
620 s->pm = 1;
621 }
622 break;
623
624 case 0x36:
625 goto bad_cmd;
626
627 case 0x37:
628 s->partial = 0;
629 s->normal = 0;
630 s->vscr = 1;
631 break;
632
633 case 0x38:
634 case 0x39:
635 case 0x3a:
636 goto bad_cmd;
637
638 case 0xb0:
639 case 0xb1:
640 if (s->pm < 0) {
641 s->pm = 2;
642 }
643 break;
644
645 case 0xb4:
646 break;
647
648 case 0xb5:
649 case 0xb6:
650 case 0xb7:
651 case 0xb8:
652 case 0xba:
653 case 0xbb:
654 goto bad_cmd;
655
656 case 0xbd:
657 s->p = 0;
658 s->resp[0] = 0;
659 s->resp[1] = 1;
660 break;
661
662 case 0xc2:
663 if (s->pm < 0) {
664 s->pm = 2;
665 }
666 break;
667
668 case 0xc6:
669 case 0xc7:
670 case 0xd0:
671 case 0xd1:
672 case 0xd4:
673 case 0xd5:
674 goto bad_cmd;
675
676 case 0xda:
677 s->p = 0;
678 s->resp[0] = (s->id >> 16) & 0xff;
679 break;
680 case 0xdb:
681 s->p = 0;
682 s->resp[0] = (s->id >> 8) & 0xff;
683 break;
684 case 0xdc:
685 s->p = 0;
686 s->resp[0] = (s->id >> 0) & 0xff;
687 break;
688
689 default:
690 bad_cmd:
691 qemu_log_mask(LOG_GUEST_ERROR,
692 "%s: unknown command %02x\n", __func__, s->cmd);
693 break;
694 }
695
696 return ret;
697}
698
699static void *mipid_init(void)
700{
701 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
702
703 s->id = 0x838f03;
704 mipid_reset(s);
705
706 return s;
707}
708
709static void n8x0_spi_setup(struct n800_s *s)
710{
711 void *tsc = s->ts.opaque;
712 void *mipid = mipid_init();
713
714 omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0);
715 omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1);
716}
717
718
719
720static void n800_dss_init(struct rfbi_chip_s *chip)
721{
722 uint8_t *fb_blank;
723
724 chip->write(chip->opaque, 0, 0x2a);
725 chip->write(chip->opaque, 1, 0x64);
726 chip->write(chip->opaque, 0, 0x2c);
727 chip->write(chip->opaque, 1, 0x1e);
728 chip->write(chip->opaque, 0, 0x2e);
729 chip->write(chip->opaque, 1, 0xe0);
730 chip->write(chip->opaque, 0, 0x30);
731 chip->write(chip->opaque, 1, 0x01);
732 chip->write(chip->opaque, 0, 0x32);
733 chip->write(chip->opaque, 1, 0x06);
734 chip->write(chip->opaque, 0, 0x68);
735 chip->write(chip->opaque, 1, 1);
736
737 chip->write(chip->opaque, 0, 0x6c);
738 chip->write(chip->opaque, 1, 0x00);
739 chip->write(chip->opaque, 1, 0x00);
740 chip->write(chip->opaque, 1, 0x00);
741 chip->write(chip->opaque, 1, 0x00);
742 chip->write(chip->opaque, 1, 0x1f);
743 chip->write(chip->opaque, 1, 0x03);
744 chip->write(chip->opaque, 1, 0xdf);
745 chip->write(chip->opaque, 1, 0x01);
746 chip->write(chip->opaque, 1, 0x00);
747 chip->write(chip->opaque, 1, 0x00);
748 chip->write(chip->opaque, 1, 0x00);
749 chip->write(chip->opaque, 1, 0x00);
750 chip->write(chip->opaque, 1, 0x1f);
751 chip->write(chip->opaque, 1, 0x03);
752 chip->write(chip->opaque, 1, 0xdf);
753 chip->write(chip->opaque, 1, 0x01);
754 chip->write(chip->opaque, 1, 0x01);
755 chip->write(chip->opaque, 1, 0x01);
756
757 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
758
759 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
760 g_free(fb_blank);
761}
762
763static void n8x0_dss_setup(struct n800_s *s)
764{
765 s->blizzard.opaque = s1d13745_init(NULL);
766 s->blizzard.block = s1d13745_write_block;
767 s->blizzard.write = s1d13745_write;
768 s->blizzard.read = s1d13745_read;
769
770 omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
771}
772
773static void n8x0_cbus_setup(struct n800_s *s)
774{
775 qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
776 qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
777 qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
778
779 CBus *cbus = cbus_init(dat_out);
780
781 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
782 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
783 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
784
785 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
786 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
787}
788
789static void n8x0_uart_setup(struct n800_s *s)
790{
791 Chardev *radio = uart_hci_init();
792
793 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
794 csrhci_pins_get(radio)[csrhci_pin_reset]);
795 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
796 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
797
798 omap_uart_attach(s->mpu->uart[BT_UART], radio);
799}
800
801static void n8x0_usb_setup(struct n800_s *s)
802{
803 SysBusDevice *dev;
804 s->usb = qdev_create(NULL, "tusb6010");
805 dev = SYS_BUS_DEVICE(s->usb);
806 qdev_init_nofail(s->usb);
807 sysbus_connect_irq(dev, 0,
808 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
809
810 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
811 sysbus_mmio_get_region(dev, 0));
812 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
813 sysbus_mmio_get_region(dev, 1));
814 qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
815 qdev_get_gpio_in(s->usb, 0));
816}
817
818
819
820
821static uint32_t n800_pinout[104] = {
822 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
823 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
824 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
825 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
826 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
827 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
828 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
829 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
830 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
831 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
832 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
833 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
834 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
835 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
836 0x00000000, 0x00000038, 0x00340000, 0x00000000,
837 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
838 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
839 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
840 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
841 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
842 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
843 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
844 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
845 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
846 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
847 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
848};
849
850static void n800_setup_nolo_tags(void *sram_base)
851{
852 int i;
853 uint32_t *p = sram_base + 0x8000;
854 uint32_t *v = sram_base + 0xa000;
855
856 memset(p, 0, 0x3000);
857
858 strcpy((void *) (p + 0), "QEMU N800");
859
860 strcpy((void *) (p + 8), "F5");
861
862 stl_p(p + 10, 0x04f70000);
863 strcpy((void *) (p + 9), "RX-34");
864
865
866 stl_p(p + 12, 0x80);
867
868
869 stl_p(p + 13, OMAP2_SRAM_BASE + 0x9000);
870
871
872 p = sram_base + 0x9000;
873#define ADD_TAG(tag, len) \
874 stw_p((uint16_t *) p + 0, tag); \
875 stw_p((uint16_t *) p + 1, len); p++; \
876 stl_p(p++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
877
878
879 ADD_TAG(0x6e01, 414);
880 for (i = 0; i < ARRAY_SIZE(n800_pinout); i++) {
881 stl_p(v++, n800_pinout[i]);
882 }
883
884
885 ADD_TAG(0x6e05, 1);
886 stl_p(v++, 2);
887
888
889 ADD_TAG(0x6e02, 4);
890 stl_p(v++, XLDR_LL_UART);
891
892#if 0
893
894 ADD_TAG(0x6e03, 6);
895 stw_p((uint16_t *) v + 0, 65);
896 stw_p((uint16_t *) v + 1, 66);
897 stw_p((uint16_t *) v + 2, 64);
898 v += 2;
899#endif
900
901
902 ADD_TAG(0x6e0a, 4);
903 stw_p((uint16_t *) v + 0, 111);
904 stw_p((uint16_t *) v + 1, 108);
905 v++;
906
907
908 ADD_TAG(0x6e04, 4);
909 stw_p((uint16_t *) v + 0, 30);
910 stw_p((uint16_t *) v + 1, 24);
911 v++;
912
913#if 0
914
915 ADD_TAG(0x6e06, 2);
916 stw_p((uint16_t *) (v++), 15);
917#endif
918
919
920 ADD_TAG(0x6e07, 4);
921 stl_p(v++, 0x00720000);
922
923
924 ADD_TAG(0x6e0b, 6);
925 stw_p((uint16_t *) v + 0, 94);
926 stw_p((uint16_t *) v + 1, 23);
927 stw_p((uint16_t *) v + 2, 0);
928 v += 2;
929
930
931 ADD_TAG(0x6e0c, 80);
932 strcpy((void *) v, "bat_cover"); v += 3;
933 stw_p((uint16_t *) v + 0, 110);
934 stw_p((uint16_t *) v + 1, 1);
935 v += 2;
936 strcpy((void *) v, "cam_act"); v += 3;
937 stw_p((uint16_t *) v + 0, 95);
938 stw_p((uint16_t *) v + 1, 32);
939 v += 2;
940 strcpy((void *) v, "cam_turn"); v += 3;
941 stw_p((uint16_t *) v + 0, 12);
942 stw_p((uint16_t *) v + 1, 33);
943 v += 2;
944 strcpy((void *) v, "headphone"); v += 3;
945 stw_p((uint16_t *) v + 0, 107);
946 stw_p((uint16_t *) v + 1, 17);
947 v += 2;
948
949
950 ADD_TAG(0x6e0e, 12);
951 stl_p(v++, 0x5c623d01);
952 stl_p(v++, 0x00000201);
953 stl_p(v++, 0x00000000);
954
955
956 ADD_TAG(0x6e0f, 8);
957 stl_p(v++, 0x00610025);
958 stl_p(v++, 0xffff0057);
959
960
961 ADD_TAG(0x6e10, 12);
962 stl_p(v++, 0xffff000f);
963 stl_p(v++, 0xffffffff);
964 stl_p(v++, 0x00000060);
965
966
967 ADD_TAG(0x6e11, 10);
968 stl_p(v++, 0x00000401);
969 stl_p(v++, 0x0002003a);
970 stl_p(v++, 0x00000002);
971
972
973 ADD_TAG(0x6e12, 2);
974 stl_p(v++, 93);
975
976#if 0
977
978 ADD_TAG(6e09, 0);
979
980
981 ADD_TAG(6e12, 0);
982#endif
983
984
985 stl_p(p++, 0x00000000);
986 stl_p(p++, 0x00000000);
987}
988
989
990
991static void n800_gpmc_init(struct n800_s *s)
992{
993 uint32_t config7 =
994 (0xf << 8) |
995 (1 << 6) |
996 (4 << 0);
997
998 cpu_physical_memory_write(0x6800a078,
999 &config7, sizeof(config7));
1000}
1001
1002
1003static void n8x0_boot_init(void *opaque)
1004{
1005 struct n800_s *s = (struct n800_s *) opaque;
1006 uint32_t buf;
1007
1008
1009#define omap_writel(addr, val) \
1010 buf = (val); \
1011 cpu_physical_memory_write(addr, &buf, sizeof(buf))
1012
1013 omap_writel(0x48008060, 0x41);
1014 omap_writel(0x48008070, 1);
1015 omap_writel(0x48008078, 0);
1016 omap_writel(0x48008090, 0);
1017 omap_writel(0x48008094, 0);
1018 omap_writel(0x48008098, 0);
1019 omap_writel(0x48008140, 2);
1020 omap_writel(0x48008148, 0);
1021 omap_writel(0x48008158, 1);
1022 omap_writel(0x480081c8, 0x15);
1023 omap_writel(0x480081d4, 0x1d4);
1024 omap_writel(0x480081d8, 0);
1025 omap_writel(0x480081dc, 0);
1026 omap_writel(0x480081e0, 0xc);
1027 omap_writel(0x48008200, 0x047e7ff7);
1028 omap_writel(0x48008204, 0x00000004);
1029 omap_writel(0x48008210, 0x047e7ff1);
1030 omap_writel(0x48008214, 0x00000004);
1031 omap_writel(0x4800821c, 0x00000000);
1032 omap_writel(0x48008230, 0);
1033 omap_writel(0x48008234, 0);
1034 omap_writel(0x48008238, 7);
1035 omap_writel(0x4800823c, 0);
1036 omap_writel(0x48008240, 0x04360626);
1037 omap_writel(0x48008244, 0x00000014);
1038 omap_writel(0x48008248, 0);
1039 omap_writel(0x48008300, 0x00000000);
1040 omap_writel(0x48008310, 0x00000000);
1041 omap_writel(0x48008340, 0x00000001);
1042 omap_writel(0x48008400, 0x00000004);
1043 omap_writel(0x48008410, 0x00000004);
1044 omap_writel(0x48008440, 0x00000000);
1045 omap_writel(0x48008500, 0x000000cf);
1046 omap_writel(0x48008530, 0x0000000c);
1047 omap_writel(0x48008540,
1048 (0x78 << 12) | (6 << 8));
1049 omap_writel(0x48008544, 2);
1050
1051
1052 n800_gpmc_init(s);
1053
1054
1055 n800_dss_init(&s->blizzard);
1056
1057
1058 s->mpu->cpu->env.GE = 0x5;
1059
1060
1061 if (s->kbd) {
1062 qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
1063 }
1064}
1065
1066#define OMAP_TAG_NOKIA_BT 0x4e01
1067#define OMAP_TAG_WLAN_CX3110X 0x4e02
1068#define OMAP_TAG_CBUS 0x4e03
1069#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1070
1071static struct omap_gpiosw_info_s {
1072 const char *name;
1073 int line;
1074 int type;
1075} n800_gpiosw_info[] = {
1076 {
1077 "bat_cover", N800_BAT_COVER_GPIO,
1078 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1079 }, {
1080 "cam_act", N800_CAM_ACT_GPIO,
1081 OMAP_GPIOSW_TYPE_ACTIVITY,
1082 }, {
1083 "cam_turn", N800_CAM_TURN_GPIO,
1084 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1085 }, {
1086 "headphone", N8X0_HEADPHONE_GPIO,
1087 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1088 },
1089 { NULL }
1090}, n810_gpiosw_info[] = {
1091 {
1092 "gps_reset", N810_GPS_RESET_GPIO,
1093 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1094 }, {
1095 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1096 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1097 }, {
1098 "headphone", N8X0_HEADPHONE_GPIO,
1099 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1100 }, {
1101 "kb_lock", N810_KB_LOCK_GPIO,
1102 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1103 }, {
1104 "sleepx_led", N810_SLEEPX_LED_GPIO,
1105 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1106 }, {
1107 "slide", N810_SLIDE_GPIO,
1108 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1109 },
1110 { NULL }
1111};
1112
1113static struct omap_partition_info_s {
1114 uint32_t offset;
1115 uint32_t size;
1116 int mask;
1117 const char *name;
1118} n800_part_info[] = {
1119 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1120 { 0x00020000, 0x00060000, 0x0, "config" },
1121 { 0x00080000, 0x00200000, 0x0, "kernel" },
1122 { 0x00280000, 0x00200000, 0x3, "initfs" },
1123 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1124
1125 { 0, 0, 0, NULL }
1126}, n810_part_info[] = {
1127 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1128 { 0x00020000, 0x00060000, 0x0, "config" },
1129 { 0x00080000, 0x00220000, 0x0, "kernel" },
1130 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1131 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1132
1133 { 0, 0, 0, NULL }
1134};
1135
1136static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1137
1138static int n8x0_atag_setup(void *p, int model)
1139{
1140 uint8_t *b;
1141 uint16_t *w;
1142 uint32_t *l;
1143 struct omap_gpiosw_info_s *gpiosw;
1144 struct omap_partition_info_s *partition;
1145 const char *tag;
1146
1147 w = p;
1148
1149 stw_p(w++, OMAP_TAG_UART);
1150 stw_p(w++, 4);
1151 stw_p(w++, (1 << 2) | (1 << 1) | (1 << 0));
1152 w++;
1153
1154#if 0
1155 stw_p(w++, OMAP_TAG_SERIAL_CONSOLE);
1156 stw_p(w++, 4);
1157 stw_p(w++, XLDR_LL_UART + 1);
1158 stw_p(w++, 115200);
1159#endif
1160
1161 stw_p(w++, OMAP_TAG_LCD);
1162 stw_p(w++, 36);
1163 strcpy((void *) w, "QEMU LCD panel");
1164 w += 8;
1165 strcpy((void *) w, "blizzard");
1166 w += 8;
1167 stw_p(w++, N810_BLIZZARD_RESET_GPIO);
1168 stw_p(w++, 24);
1169
1170 stw_p(w++, OMAP_TAG_CBUS);
1171 stw_p(w++, 8);
1172 stw_p(w++, N8X0_CBUS_CLK_GPIO);
1173 stw_p(w++, N8X0_CBUS_DAT_GPIO);
1174 stw_p(w++, N8X0_CBUS_SEL_GPIO);
1175 w++;
1176
1177 stw_p(w++, OMAP_TAG_EM_ASIC_BB5);
1178 stw_p(w++, 4);
1179 stw_p(w++, N8X0_RETU_GPIO);
1180 stw_p(w++, N8X0_TAHVO_GPIO);
1181
1182 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1183 for (; gpiosw->name; gpiosw++) {
1184 stw_p(w++, OMAP_TAG_GPIO_SWITCH);
1185 stw_p(w++, 20);
1186 strcpy((void *) w, gpiosw->name);
1187 w += 6;
1188 stw_p(w++, gpiosw->line);
1189 stw_p(w++, gpiosw->type);
1190 stw_p(w++, 0);
1191 stw_p(w++, 0);
1192 }
1193
1194 stw_p(w++, OMAP_TAG_NOKIA_BT);
1195 stw_p(w++, 12);
1196 b = (void *) w;
1197 stb_p(b++, 0x01);
1198 stb_p(b++, N8X0_BT_WKUP_GPIO);
1199 stb_p(b++, N8X0_BT_HOST_WKUP_GPIO);
1200 stb_p(b++, N8X0_BT_RESET_GPIO);
1201 stb_p(b++, BT_UART + 1);
1202 memcpy(b, &n8x0_bd_addr, 6);
1203 b += 6;
1204 stb_p(b++, 0x02);
1205 w = (void *) b;
1206
1207 stw_p(w++, OMAP_TAG_WLAN_CX3110X);
1208 stw_p(w++, 8);
1209 stw_p(w++, 0x25);
1210 stw_p(w++, N8X0_WLAN_PWR_GPIO);
1211 stw_p(w++, N8X0_WLAN_IRQ_GPIO);
1212 stw_p(w++, -1);
1213
1214 stw_p(w++, OMAP_TAG_MMC);
1215 stw_p(w++, 16);
1216 if (model == 810) {
1217 stw_p(w++, 0x23f);
1218 stw_p(w++, -1);
1219 stw_p(w++, -1);
1220 stw_p(w++, -1);
1221 stw_p(w++, 0x240);
1222 stw_p(w++, 0xc000);
1223 stw_p(w++, 0x0248);
1224 stw_p(w++, 0xc000);
1225 } else {
1226 stw_p(w++, 0xf);
1227 stw_p(w++, -1);
1228 stw_p(w++, -1);
1229 stw_p(w++, -1);
1230 stw_p(w++, 0);
1231 stw_p(w++, 0);
1232 stw_p(w++, 0);
1233 stw_p(w++, 0);
1234 }
1235
1236 stw_p(w++, OMAP_TAG_TEA5761);
1237 stw_p(w++, 4);
1238 stw_p(w++, N8X0_TEA5761_CS_GPIO);
1239 w++;
1240
1241 partition = (model == 810) ? n810_part_info : n800_part_info;
1242 for (; partition->name; partition++) {
1243 stw_p(w++, OMAP_TAG_PARTITION);
1244 stw_p(w++, 28);
1245 strcpy((void *) w, partition->name);
1246 l = (void *) (w + 8);
1247 stl_p(l++, partition->size);
1248 stl_p(l++, partition->offset);
1249 stl_p(l++, partition->mask);
1250 w = (void *) l;
1251 }
1252
1253 stw_p(w++, OMAP_TAG_BOOT_REASON);
1254 stw_p(w++, 12);
1255#if 0
1256 strcpy((void *) w, "por");
1257 strcpy((void *) w, "charger");
1258 strcpy((void *) w, "32wd_to");
1259 strcpy((void *) w, "sw_rst");
1260 strcpy((void *) w, "mbus");
1261 strcpy((void *) w, "unknown");
1262 strcpy((void *) w, "swdg_to");
1263 strcpy((void *) w, "sec_vio");
1264 strcpy((void *) w, "pwr_key");
1265 strcpy((void *) w, "rtc_alarm");
1266#else
1267 strcpy((void *) w, "pwr_key");
1268#endif
1269 w += 6;
1270
1271 tag = (model == 810) ? "RX-44" : "RX-34";
1272 stw_p(w++, OMAP_TAG_VERSION_STR);
1273 stw_p(w++, 24);
1274 strcpy((void *) w, "product");
1275 w += 6;
1276 strcpy((void *) w, tag);
1277 w += 6;
1278
1279 stw_p(w++, OMAP_TAG_VERSION_STR);
1280 stw_p(w++, 24);
1281 strcpy((void *) w, "hw-build");
1282 w += 6;
1283 strcpy((void *) w, "QEMU ");
1284 pstrcat((void *) w, 12, qemu_hw_version());
1285 w += 6;
1286
1287 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1288 stw_p(w++, OMAP_TAG_VERSION_STR);
1289 stw_p(w++, 24);
1290 strcpy((void *) w, "nolo");
1291 w += 6;
1292 strcpy((void *) w, tag);
1293 w += 6;
1294
1295 return (void *) w - p;
1296}
1297
1298static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1299{
1300 return n8x0_atag_setup(p, 800);
1301}
1302
1303static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1304{
1305 return n8x0_atag_setup(p, 810);
1306}
1307
1308static void n8x0_init(MachineState *machine,
1309 struct arm_boot_info *binfo, int model)
1310{
1311 MemoryRegion *sysmem = get_system_memory();
1312 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1313 int sdram_size = binfo->ram_size;
1314
1315 s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type);
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342 n8x0_gpio_setup(s);
1343 n8x0_nand_setup(s);
1344 n8x0_i2c_setup(s);
1345 if (model == 800) {
1346 n800_tsc_kbd_setup(s);
1347 } else if (model == 810) {
1348 n810_tsc_setup(s);
1349 n810_kbd_setup(s);
1350 }
1351 n8x0_spi_setup(s);
1352 n8x0_dss_setup(s);
1353 n8x0_cbus_setup(s);
1354 n8x0_uart_setup(s);
1355 if (machine_usb(machine)) {
1356 n8x0_usb_setup(s);
1357 }
1358
1359 if (machine->kernel_filename) {
1360
1361 binfo->kernel_filename = machine->kernel_filename;
1362 binfo->kernel_cmdline = machine->kernel_cmdline;
1363 binfo->initrd_filename = machine->initrd_filename;
1364 arm_load_kernel(s->mpu->cpu, binfo);
1365
1366 qemu_register_reset(n8x0_boot_init, s);
1367 }
1368
1369 if (option_rom[0].name &&
1370 (machine->boot_order[0] == 'n' || !machine->kernel_filename)) {
1371 uint8_t *nolo_tags = g_new(uint8_t, 0x10000);
1372
1373 s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384 load_image_targphys(option_rom[0].name,
1385 OMAP2_Q2_BASE + 0x400000,
1386 sdram_size - 0x400000);
1387
1388 n800_setup_nolo_tags(nolo_tags);
1389 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1390 g_free(nolo_tags);
1391 }
1392}
1393
1394static struct arm_boot_info n800_binfo = {
1395 .loader_start = OMAP2_Q2_BASE,
1396
1397 .ram_size = 0x08000000,
1398 .board_id = 0x4f7,
1399 .atag_board = n800_atag_setup,
1400};
1401
1402static struct arm_boot_info n810_binfo = {
1403 .loader_start = OMAP2_Q2_BASE,
1404
1405 .ram_size = 0x08000000,
1406
1407
1408
1409 .board_id = 0x60c,
1410 .atag_board = n810_atag_setup,
1411};
1412
1413static void n800_init(MachineState *machine)
1414{
1415 n8x0_init(machine, &n800_binfo, 800);
1416}
1417
1418static void n810_init(MachineState *machine)
1419{
1420 n8x0_init(machine, &n810_binfo, 810);
1421}
1422
1423static void n800_class_init(ObjectClass *oc, void *data)
1424{
1425 MachineClass *mc = MACHINE_CLASS(oc);
1426
1427 mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)";
1428 mc->init = n800_init;
1429 mc->default_boot_order = "";
1430 mc->ignore_memory_transaction_failures = true;
1431 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
1432}
1433
1434static const TypeInfo n800_type = {
1435 .name = MACHINE_TYPE_NAME("n800"),
1436 .parent = TYPE_MACHINE,
1437 .class_init = n800_class_init,
1438};
1439
1440static void n810_class_init(ObjectClass *oc, void *data)
1441{
1442 MachineClass *mc = MACHINE_CLASS(oc);
1443
1444 mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)";
1445 mc->init = n810_init;
1446 mc->default_boot_order = "";
1447 mc->ignore_memory_transaction_failures = true;
1448 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
1449}
1450
1451static const TypeInfo n810_type = {
1452 .name = MACHINE_TYPE_NAME("n810"),
1453 .parent = TYPE_MACHINE,
1454 .class_init = n810_class_init,
1455};
1456
1457static void nseries_machine_init(void)
1458{
1459 type_register_static(&n800_type);
1460 type_register_static(&n810_type);
1461}
1462
1463type_init(nseries_machine_init)
1464