LXR qemu/hw/arm/sabrelite.c

   1/*
   2 * SABRELITE Board System emulation.
   3 *
   4 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
   5 *
   6 * This code is licensed under the GPL, version 2 or later.
   7 * See the file `COPYING' in the top level directory.
   8 *
   9 * It (partially) emulates a sabrelite board, with a Freescale
  10 * i.MX6 SoC
  11 */
  12
  13#include "qemu/osdep.h"
  14#include "qapi/error.h"
  15#include "hw/arm/fsl-imx6.h"
  16#include "hw/boards.h"
  17#include "sysemu/sysemu.h"
  18#include "qemu/error-report.h"
  19#include "sysemu/qtest.h"
  20
  21typedef struct IMX6Sabrelite {
  22    FslIMX6State soc;
  23    MemoryRegion ram;
  24} IMX6Sabrelite;
  25
  26static struct arm_boot_info sabrelite_binfo = {
  27    /* DDR memory start */
  28    .loader_start = FSL_IMX6_MMDC_ADDR,
  29    /* No board ID, we boot from DT tree */
  30    .board_id = -1,
  31};
  32
  33/* No need to do any particular setup for secondary boot */
  34static void sabrelite_write_secondary(ARMCPU *cpu,
  35                                      const struct arm_boot_info *info)
  36{
  37}
  38
  39/* Secondary cores are reset through SRC device */
  40static void sabrelite_reset_secondary(ARMCPU *cpu,
  41                                      const struct arm_boot_info *info)
  42{
  43}
  44
  45static void sabrelite_init(MachineState *machine)
  46{
  47    IMX6Sabrelite *s = g_new0(IMX6Sabrelite, 1);
  48    Error *err = NULL;
  49
  50    /* Check the amount of memory is compatible with the SOC */
  51    if (machine->ram_size > FSL_IMX6_MMDC_SIZE) {
  52        error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
  53                     machine->ram_size, FSL_IMX6_MMDC_SIZE);
  54        exit(1);
  55    }
  56
  57    object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
  58                            TYPE_FSL_IMX6, &error_abort, NULL);
  59
  60    object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
  61    if (err != NULL) {
  62        error_report("%s", error_get_pretty(err));
  63        exit(1);
  64    }
  65
  66    memory_region_allocate_system_memory(&s->ram, NULL, "sabrelite.ram",
  67                                         machine->ram_size);
  68    memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
  69                                &s->ram);
  70
  71    {
  72        /*
  73         * TODO: Ideally we would expose the chip select and spi bus on the
  74         * SoC object using alias properties; then we would not need to
  75         * directly access the underlying spi device object.
  76         */
  77        /* Add the sst25vf016b NOR FLASH memory to first SPI */
  78        Object *spi_dev;
  79
  80        spi_dev = object_resolve_path_component(OBJECT(&s->soc), "spi1");
  81        if (spi_dev) {
  82            SSIBus *spi_bus;
  83
  84            spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi");
  85            if (spi_bus) {
  86                DeviceState *flash_dev;
  87                qemu_irq cs_line;
  88                DriveInfo *dinfo = drive_get_next(IF_MTD);
  89
  90                flash_dev = ssi_create_slave_no_init(spi_bus, "sst25vf016b");
  91                if (dinfo) {
  92                    qdev_prop_set_drive(flash_dev, "drive",
  93                                        blk_by_legacy_dinfo(dinfo),
  94                                        &error_fatal);
  95                }
  96                qdev_init_nofail(flash_dev);
  97
  98                cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
  99                sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
 100            }
 101        }
 102    }
 103
 104    sabrelite_binfo.ram_size = machine->ram_size;
 105    sabrelite_binfo.kernel_filename = machine->kernel_filename;
 106    sabrelite_binfo.kernel_cmdline = machine->kernel_cmdline;
 107    sabrelite_binfo.initrd_filename = machine->initrd_filename;
 108    sabrelite_binfo.nb_cpus = machine->smp.cpus;
 109    sabrelite_binfo.secure_boot = true;
 110    sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
 111    sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
 112
 113    if (!qtest_enabled()) {
 114        arm_load_kernel(&s->soc.cpu[0], &sabrelite_binfo);
 115    }
 116}
 117
 118static void sabrelite_machine_init(MachineClass *mc)
 119{
 120    mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)";
 121    mc->init = sabrelite_init;
 122    mc->max_cpus = FSL_IMX6_NUM_CPUS;
 123    mc->ignore_memory_transaction_failures = true;
 124}
 125
 126DEFINE_MACHINE("sabrelite", sabrelite_machine_init)
 127