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10#include "qemu/osdep.h"
11#include "qapi/error.h"
12#include "hw/sysbus.h"
13#include "hw/ssi/ssi.h"
14#include "hw/arm/boot.h"
15#include "qemu/timer.h"
16#include "hw/i2c/i2c.h"
17#include "net/net.h"
18#include "hw/boards.h"
19#include "qemu/log.h"
20#include "exec/address-spaces.h"
21#include "sysemu/sysemu.h"
22#include "hw/arm/armv7m.h"
23#include "hw/char/pl011.h"
24#include "hw/input/gamepad.h"
25#include "hw/watchdog/cmsdk-apb-watchdog.h"
26#include "hw/misc/unimp.h"
27#include "cpu.h"
28
29#define GPIO_A 0
30#define GPIO_B 1
31#define GPIO_C 2
32#define GPIO_D 3
33#define GPIO_E 4
34#define GPIO_F 5
35#define GPIO_G 6
36
37#define BP_OLED_I2C 0x01
38#define BP_OLED_SSI 0x02
39#define BP_GAMEPAD 0x04
40
41#define NUM_IRQ_LINES 64
42
43typedef const struct {
44 const char *name;
45 uint32_t did0;
46 uint32_t did1;
47 uint32_t dc0;
48 uint32_t dc1;
49 uint32_t dc2;
50 uint32_t dc3;
51 uint32_t dc4;
52 uint32_t peripherals;
53} stellaris_board_info;
54
55
56
57#define TYPE_STELLARIS_GPTM "stellaris-gptm"
58#define STELLARIS_GPTM(obj) \
59 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
60
61typedef struct gptm_state {
62 SysBusDevice parent_obj;
63
64 MemoryRegion iomem;
65 uint32_t config;
66 uint32_t mode[2];
67 uint32_t control;
68 uint32_t state;
69 uint32_t mask;
70 uint32_t load[2];
71 uint32_t match[2];
72 uint32_t prescale[2];
73 uint32_t match_prescale[2];
74 uint32_t rtc;
75 int64_t tick[2];
76 struct gptm_state *opaque[2];
77 QEMUTimer *timer[2];
78
79 qemu_irq trigger;
80 qemu_irq irq;
81} gptm_state;
82
83static void gptm_update_irq(gptm_state *s)
84{
85 int level;
86 level = (s->state & s->mask) != 0;
87 qemu_set_irq(s->irq, level);
88}
89
90static void gptm_stop(gptm_state *s, int n)
91{
92 timer_del(s->timer[n]);
93}
94
95static void gptm_reload(gptm_state *s, int n, int reset)
96{
97 int64_t tick;
98 if (reset)
99 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
100 else
101 tick = s->tick[n];
102
103 if (s->config == 0) {
104
105 uint32_t count;
106 count = s->load[0] | (s->load[1] << 16);
107 tick += (int64_t)count * system_clock_scale;
108 } else if (s->config == 1) {
109
110 tick += NANOSECONDS_PER_SECOND;
111 } else if (s->mode[n] == 0xa) {
112
113 } else {
114 qemu_log_mask(LOG_UNIMP,
115 "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
116 s->mode[n]);
117 return;
118 }
119 s->tick[n] = tick;
120 timer_mod(s->timer[n], tick);
121}
122
123static void gptm_tick(void *opaque)
124{
125 gptm_state **p = (gptm_state **)opaque;
126 gptm_state *s;
127 int n;
128
129 s = *p;
130 n = p - s->opaque;
131 if (s->config == 0) {
132 s->state |= 1;
133 if ((s->control & 0x20)) {
134
135 qemu_irq_pulse(s->trigger);
136 }
137 if (s->mode[0] & 1) {
138
139 s->control &= ~1;
140 } else {
141
142 gptm_reload(s, 0, 0);
143 }
144 } else if (s->config == 1) {
145
146 uint32_t match;
147 s->rtc++;
148 match = s->match[0] | (s->match[1] << 16);
149 if (s->rtc > match)
150 s->rtc = 0;
151 if (s->rtc == 0) {
152 s->state |= 8;
153 }
154 gptm_reload(s, 0, 0);
155 } else if (s->mode[n] == 0xa) {
156
157 } else {
158 qemu_log_mask(LOG_UNIMP,
159 "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
160 s->mode[n]);
161 }
162 gptm_update_irq(s);
163}
164
165static uint64_t gptm_read(void *opaque, hwaddr offset,
166 unsigned size)
167{
168 gptm_state *s = (gptm_state *)opaque;
169
170 switch (offset) {
171 case 0x00:
172 return s->config;
173 case 0x04:
174 return s->mode[0];
175 case 0x08:
176 return s->mode[1];
177 case 0x0c:
178 return s->control;
179 case 0x18:
180 return s->mask;
181 case 0x1c:
182 return s->state;
183 case 0x20:
184 return s->state & s->mask;
185 case 0x24:
186 return 0;
187 case 0x28:
188 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
189 case 0x2c:
190 return s->load[1];
191 case 0x30:
192 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
193 case 0x34:
194 return s->match[1];
195 case 0x38:
196 return s->prescale[0];
197 case 0x3c:
198 return s->prescale[1];
199 case 0x40:
200 return s->match_prescale[0];
201 case 0x44:
202 return s->match_prescale[1];
203 case 0x48:
204 if (s->config == 1) {
205 return s->rtc;
206 }
207 qemu_log_mask(LOG_UNIMP,
208 "GPTM: read of TAR but timer read not supported\n");
209 return 0;
210 case 0x4c:
211 qemu_log_mask(LOG_UNIMP,
212 "GPTM: read of TBR but timer read not supported\n");
213 return 0;
214 default:
215 qemu_log_mask(LOG_GUEST_ERROR,
216 "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n",
217 offset);
218 return 0;
219 }
220}
221
222static void gptm_write(void *opaque, hwaddr offset,
223 uint64_t value, unsigned size)
224{
225 gptm_state *s = (gptm_state *)opaque;
226 uint32_t oldval;
227
228
229
230
231 switch (offset) {
232 case 0x00:
233 s->config = value;
234 break;
235 case 0x04:
236 s->mode[0] = value;
237 break;
238 case 0x08:
239 s->mode[1] = value;
240 break;
241 case 0x0c:
242 oldval = s->control;
243 s->control = value;
244
245 if ((oldval ^ value) & 1) {
246 if (value & 1) {
247 gptm_reload(s, 0, 1);
248 } else {
249 gptm_stop(s, 0);
250 }
251 }
252 if (((oldval ^ value) & 0x100) && s->config >= 4) {
253 if (value & 0x100) {
254 gptm_reload(s, 1, 1);
255 } else {
256 gptm_stop(s, 1);
257 }
258 }
259 break;
260 case 0x18:
261 s->mask = value & 0x77;
262 gptm_update_irq(s);
263 break;
264 case 0x24:
265 s->state &= ~value;
266 break;
267 case 0x28:
268 s->load[0] = value & 0xffff;
269 if (s->config < 4) {
270 s->load[1] = value >> 16;
271 }
272 break;
273 case 0x2c:
274 s->load[1] = value & 0xffff;
275 break;
276 case 0x30:
277 s->match[0] = value & 0xffff;
278 if (s->config < 4) {
279 s->match[1] = value >> 16;
280 }
281 break;
282 case 0x34:
283 s->match[1] = value >> 16;
284 break;
285 case 0x38:
286 s->prescale[0] = value;
287 break;
288 case 0x3c:
289 s->prescale[1] = value;
290 break;
291 case 0x40:
292 s->match_prescale[0] = value;
293 break;
294 case 0x44:
295 s->match_prescale[0] = value;
296 break;
297 default:
298 qemu_log_mask(LOG_GUEST_ERROR,
299 "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n",
300 offset);
301 }
302 gptm_update_irq(s);
303}
304
305static const MemoryRegionOps gptm_ops = {
306 .read = gptm_read,
307 .write = gptm_write,
308 .endianness = DEVICE_NATIVE_ENDIAN,
309};
310
311static const VMStateDescription vmstate_stellaris_gptm = {
312 .name = "stellaris_gptm",
313 .version_id = 1,
314 .minimum_version_id = 1,
315 .fields = (VMStateField[]) {
316 VMSTATE_UINT32(config, gptm_state),
317 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
318 VMSTATE_UINT32(control, gptm_state),
319 VMSTATE_UINT32(state, gptm_state),
320 VMSTATE_UINT32(mask, gptm_state),
321 VMSTATE_UNUSED(8),
322 VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
323 VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
324 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
325 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
326 VMSTATE_UINT32(rtc, gptm_state),
327 VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
328 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
329 VMSTATE_END_OF_LIST()
330 }
331};
332
333static void stellaris_gptm_init(Object *obj)
334{
335 DeviceState *dev = DEVICE(obj);
336 gptm_state *s = STELLARIS_GPTM(obj);
337 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
338
339 sysbus_init_irq(sbd, &s->irq);
340 qdev_init_gpio_out(dev, &s->trigger, 1);
341
342 memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
343 "gptm", 0x1000);
344 sysbus_init_mmio(sbd, &s->iomem);
345
346 s->opaque[0] = s->opaque[1] = s;
347 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
348 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
349}
350
351
352
353
354typedef struct {
355 MemoryRegion iomem;
356 uint32_t pborctl;
357 uint32_t ldopctl;
358 uint32_t int_status;
359 uint32_t int_mask;
360 uint32_t resc;
361 uint32_t rcc;
362 uint32_t rcc2;
363 uint32_t rcgc[3];
364 uint32_t scgc[3];
365 uint32_t dcgc[3];
366 uint32_t clkvclr;
367 uint32_t ldoarst;
368 uint32_t user0;
369 uint32_t user1;
370 qemu_irq irq;
371 stellaris_board_info *board;
372} ssys_state;
373
374static void ssys_update(ssys_state *s)
375{
376 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
377}
378
379static uint32_t pllcfg_sandstorm[16] = {
380 0x31c0,
381 0x1ae0,
382 0x18c0,
383 0xd573,
384 0x37a6,
385 0x1ae2,
386 0x0c40,
387 0x98bc,
388 0x935b,
389 0x09c0,
390 0x4dee,
391 0x0c41,
392 0x75db,
393 0x1ae6,
394 0x0600,
395 0x585b
396};
397
398static uint32_t pllcfg_fury[16] = {
399 0x3200,
400 0x1b20,
401 0x1900,
402 0xf42b,
403 0x37e3,
404 0x1b21,
405 0x0c80,
406 0x98ee,
407 0xd5b4,
408 0x0a00,
409 0x4e27,
410 0x1902,
411 0xec1c,
412 0x1b23,
413 0x0640,
414 0xb11c
415};
416
417#define DID0_VER_MASK 0x70000000
418#define DID0_VER_0 0x00000000
419#define DID0_VER_1 0x10000000
420
421#define DID0_CLASS_MASK 0x00FF0000
422#define DID0_CLASS_SANDSTORM 0x00000000
423#define DID0_CLASS_FURY 0x00010000
424
425static int ssys_board_class(const ssys_state *s)
426{
427 uint32_t did0 = s->board->did0;
428 switch (did0 & DID0_VER_MASK) {
429 case DID0_VER_0:
430 return DID0_CLASS_SANDSTORM;
431 case DID0_VER_1:
432 switch (did0 & DID0_CLASS_MASK) {
433 case DID0_CLASS_SANDSTORM:
434 case DID0_CLASS_FURY:
435 return did0 & DID0_CLASS_MASK;
436 }
437
438 default:
439
440
441
442 g_assert_not_reached();
443 }
444}
445
446static uint64_t ssys_read(void *opaque, hwaddr offset,
447 unsigned size)
448{
449 ssys_state *s = (ssys_state *)opaque;
450
451 switch (offset) {
452 case 0x000:
453 return s->board->did0;
454 case 0x004:
455 return s->board->did1;
456 case 0x008:
457 return s->board->dc0;
458 case 0x010:
459 return s->board->dc1;
460 case 0x014:
461 return s->board->dc2;
462 case 0x018:
463 return s->board->dc3;
464 case 0x01c:
465 return s->board->dc4;
466 case 0x030:
467 return s->pborctl;
468 case 0x034:
469 return s->ldopctl;
470 case 0x040:
471 return 0;
472 case 0x044:
473 return 0;
474 case 0x048:
475 return 0;
476 case 0x050:
477 return s->int_status;
478 case 0x054:
479 return s->int_mask;
480 case 0x058:
481 return s->int_status & s->int_mask;
482 case 0x05c:
483 return s->resc;
484 case 0x060:
485 return s->rcc;
486 case 0x064:
487 {
488 int xtal;
489 xtal = (s->rcc >> 6) & 0xf;
490 switch (ssys_board_class(s)) {
491 case DID0_CLASS_FURY:
492 return pllcfg_fury[xtal];
493 case DID0_CLASS_SANDSTORM:
494 return pllcfg_sandstorm[xtal];
495 default:
496 g_assert_not_reached();
497 }
498 }
499 case 0x070:
500 return s->rcc2;
501 case 0x100:
502 return s->rcgc[0];
503 case 0x104:
504 return s->rcgc[1];
505 case 0x108:
506 return s->rcgc[2];
507 case 0x110:
508 return s->scgc[0];
509 case 0x114:
510 return s->scgc[1];
511 case 0x118:
512 return s->scgc[2];
513 case 0x120:
514 return s->dcgc[0];
515 case 0x124:
516 return s->dcgc[1];
517 case 0x128:
518 return s->dcgc[2];
519 case 0x150:
520 return s->clkvclr;
521 case 0x160:
522 return s->ldoarst;
523 case 0x1e0:
524 return s->user0;
525 case 0x1e4:
526 return s->user1;
527 default:
528 qemu_log_mask(LOG_GUEST_ERROR,
529 "SSYS: read at bad offset 0x%x\n", (int)offset);
530 return 0;
531 }
532}
533
534static bool ssys_use_rcc2(ssys_state *s)
535{
536 return (s->rcc2 >> 31) & 0x1;
537}
538
539
540
541
542static void ssys_calculate_system_clock(ssys_state *s)
543{
544 if (ssys_use_rcc2(s)) {
545 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
546 } else {
547 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
548 }
549}
550
551static void ssys_write(void *opaque, hwaddr offset,
552 uint64_t value, unsigned size)
553{
554 ssys_state *s = (ssys_state *)opaque;
555
556 switch (offset) {
557 case 0x030:
558 s->pborctl = value & 0xffff;
559 break;
560 case 0x034:
561 s->ldopctl = value & 0x1f;
562 break;
563 case 0x040:
564 case 0x044:
565 case 0x048:
566 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
567 break;
568 case 0x054:
569 s->int_mask = value & 0x7f;
570 break;
571 case 0x058:
572 s->int_status &= ~value;
573 break;
574 case 0x05c:
575 s->resc = value & 0x3f;
576 break;
577 case 0x060:
578 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
579
580 s->int_status |= (1 << 6);
581 }
582 s->rcc = value;
583 ssys_calculate_system_clock(s);
584 break;
585 case 0x070:
586 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
587 break;
588 }
589
590 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
591
592 s->int_status |= (1 << 6);
593 }
594 s->rcc2 = value;
595 ssys_calculate_system_clock(s);
596 break;
597 case 0x100:
598 s->rcgc[0] = value;
599 break;
600 case 0x104:
601 s->rcgc[1] = value;
602 break;
603 case 0x108:
604 s->rcgc[2] = value;
605 break;
606 case 0x110:
607 s->scgc[0] = value;
608 break;
609 case 0x114:
610 s->scgc[1] = value;
611 break;
612 case 0x118:
613 s->scgc[2] = value;
614 break;
615 case 0x120:
616 s->dcgc[0] = value;
617 break;
618 case 0x124:
619 s->dcgc[1] = value;
620 break;
621 case 0x128:
622 s->dcgc[2] = value;
623 break;
624 case 0x150:
625 s->clkvclr = value;
626 break;
627 case 0x160:
628 s->ldoarst = value;
629 break;
630 default:
631 qemu_log_mask(LOG_GUEST_ERROR,
632 "SSYS: write at bad offset 0x%x\n", (int)offset);
633 }
634 ssys_update(s);
635}
636
637static const MemoryRegionOps ssys_ops = {
638 .read = ssys_read,
639 .write = ssys_write,
640 .endianness = DEVICE_NATIVE_ENDIAN,
641};
642
643static void ssys_reset(void *opaque)
644{
645 ssys_state *s = (ssys_state *)opaque;
646
647 s->pborctl = 0x7ffd;
648 s->rcc = 0x078e3ac0;
649
650 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
651 s->rcc2 = 0;
652 } else {
653 s->rcc2 = 0x07802810;
654 }
655 s->rcgc[0] = 1;
656 s->scgc[0] = 1;
657 s->dcgc[0] = 1;
658 ssys_calculate_system_clock(s);
659}
660
661static int stellaris_sys_post_load(void *opaque, int version_id)
662{
663 ssys_state *s = opaque;
664
665 ssys_calculate_system_clock(s);
666
667 return 0;
668}
669
670static const VMStateDescription vmstate_stellaris_sys = {
671 .name = "stellaris_sys",
672 .version_id = 2,
673 .minimum_version_id = 1,
674 .post_load = stellaris_sys_post_load,
675 .fields = (VMStateField[]) {
676 VMSTATE_UINT32(pborctl, ssys_state),
677 VMSTATE_UINT32(ldopctl, ssys_state),
678 VMSTATE_UINT32(int_mask, ssys_state),
679 VMSTATE_UINT32(int_status, ssys_state),
680 VMSTATE_UINT32(resc, ssys_state),
681 VMSTATE_UINT32(rcc, ssys_state),
682 VMSTATE_UINT32_V(rcc2, ssys_state, 2),
683 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
684 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
685 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
686 VMSTATE_UINT32(clkvclr, ssys_state),
687 VMSTATE_UINT32(ldoarst, ssys_state),
688 VMSTATE_END_OF_LIST()
689 }
690};
691
692static int stellaris_sys_init(uint32_t base, qemu_irq irq,
693 stellaris_board_info * board,
694 uint8_t *macaddr)
695{
696 ssys_state *s;
697
698 s = g_new0(ssys_state, 1);
699 s->irq = irq;
700 s->board = board;
701
702 s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
703 s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
704
705 memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
706 memory_region_add_subregion(get_system_memory(), base, &s->iomem);
707 ssys_reset(s);
708 vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
709 return 0;
710}
711
712
713
714
715#define TYPE_STELLARIS_I2C "stellaris-i2c"
716#define STELLARIS_I2C(obj) \
717 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
718
719typedef struct {
720 SysBusDevice parent_obj;
721
722 I2CBus *bus;
723 qemu_irq irq;
724 MemoryRegion iomem;
725 uint32_t msa;
726 uint32_t mcs;
727 uint32_t mdr;
728 uint32_t mtpr;
729 uint32_t mimr;
730 uint32_t mris;
731 uint32_t mcr;
732} stellaris_i2c_state;
733
734#define STELLARIS_I2C_MCS_BUSY 0x01
735#define STELLARIS_I2C_MCS_ERROR 0x02
736#define STELLARIS_I2C_MCS_ADRACK 0x04
737#define STELLARIS_I2C_MCS_DATACK 0x08
738#define STELLARIS_I2C_MCS_ARBLST 0x10
739#define STELLARIS_I2C_MCS_IDLE 0x20
740#define STELLARIS_I2C_MCS_BUSBSY 0x40
741
742static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
743 unsigned size)
744{
745 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
746
747 switch (offset) {
748 case 0x00:
749 return s->msa;
750 case 0x04:
751
752 return s->mcs | STELLARIS_I2C_MCS_IDLE;
753 case 0x08:
754 return s->mdr;
755 case 0x0c:
756 return s->mtpr;
757 case 0x10:
758 return s->mimr;
759 case 0x14:
760 return s->mris;
761 case 0x18:
762 return s->mris & s->mimr;
763 case 0x20:
764 return s->mcr;
765 default:
766 qemu_log_mask(LOG_GUEST_ERROR,
767 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
768 return 0;
769 }
770}
771
772static void stellaris_i2c_update(stellaris_i2c_state *s)
773{
774 int level;
775
776 level = (s->mris & s->mimr) != 0;
777 qemu_set_irq(s->irq, level);
778}
779
780static void stellaris_i2c_write(void *opaque, hwaddr offset,
781 uint64_t value, unsigned size)
782{
783 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
784
785 switch (offset) {
786 case 0x00:
787 s->msa = value & 0xff;
788 break;
789 case 0x04:
790 if ((s->mcr & 0x10) == 0) {
791
792 break;
793 }
794
795 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
796 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
797 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
798 } else {
799 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
800 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
801 }
802 }
803
804 if (!i2c_bus_busy(s->bus)
805 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
806 s->mcs |= STELLARIS_I2C_MCS_ERROR;
807 break;
808 }
809 s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
810 if (value & 1) {
811
812
813 if (s->msa & 1) {
814
815 s->mdr = i2c_recv(s->bus);
816 } else {
817
818 i2c_send(s->bus, s->mdr);
819 }
820
821 s->mris |= 1;
822 }
823 if (value & 4) {
824
825 i2c_end_transfer(s->bus);
826 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
827 }
828 break;
829 case 0x08:
830 s->mdr = value & 0xff;
831 break;
832 case 0x0c:
833 s->mtpr = value & 0xff;
834 break;
835 case 0x10:
836 s->mimr = 1;
837 break;
838 case 0x1c:
839 s->mris &= ~value;
840 break;
841 case 0x20:
842 if (value & 1) {
843 qemu_log_mask(LOG_UNIMP,
844 "stellaris_i2c: Loopback not implemented\n");
845 }
846 if (value & 0x20) {
847 qemu_log_mask(LOG_UNIMP,
848 "stellaris_i2c: Slave mode not implemented\n");
849 }
850 s->mcr = value & 0x31;
851 break;
852 default:
853 qemu_log_mask(LOG_GUEST_ERROR,
854 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
855 }
856 stellaris_i2c_update(s);
857}
858
859static void stellaris_i2c_reset(stellaris_i2c_state *s)
860{
861 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
862 i2c_end_transfer(s->bus);
863
864 s->msa = 0;
865 s->mcs = 0;
866 s->mdr = 0;
867 s->mtpr = 1;
868 s->mimr = 0;
869 s->mris = 0;
870 s->mcr = 0;
871 stellaris_i2c_update(s);
872}
873
874static const MemoryRegionOps stellaris_i2c_ops = {
875 .read = stellaris_i2c_read,
876 .write = stellaris_i2c_write,
877 .endianness = DEVICE_NATIVE_ENDIAN,
878};
879
880static const VMStateDescription vmstate_stellaris_i2c = {
881 .name = "stellaris_i2c",
882 .version_id = 1,
883 .minimum_version_id = 1,
884 .fields = (VMStateField[]) {
885 VMSTATE_UINT32(msa, stellaris_i2c_state),
886 VMSTATE_UINT32(mcs, stellaris_i2c_state),
887 VMSTATE_UINT32(mdr, stellaris_i2c_state),
888 VMSTATE_UINT32(mtpr, stellaris_i2c_state),
889 VMSTATE_UINT32(mimr, stellaris_i2c_state),
890 VMSTATE_UINT32(mris, stellaris_i2c_state),
891 VMSTATE_UINT32(mcr, stellaris_i2c_state),
892 VMSTATE_END_OF_LIST()
893 }
894};
895
896static void stellaris_i2c_init(Object *obj)
897{
898 DeviceState *dev = DEVICE(obj);
899 stellaris_i2c_state *s = STELLARIS_I2C(obj);
900 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
901 I2CBus *bus;
902
903 sysbus_init_irq(sbd, &s->irq);
904 bus = i2c_init_bus(dev, "i2c");
905 s->bus = bus;
906
907 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
908 "i2c", 0x1000);
909 sysbus_init_mmio(sbd, &s->iomem);
910
911 stellaris_i2c_reset(s);
912}
913
914
915
916
917#define STELLARIS_ADC_EM_CONTROLLER 0
918#define STELLARIS_ADC_EM_COMP 1
919#define STELLARIS_ADC_EM_EXTERNAL 4
920#define STELLARIS_ADC_EM_TIMER 5
921#define STELLARIS_ADC_EM_PWM0 6
922#define STELLARIS_ADC_EM_PWM1 7
923#define STELLARIS_ADC_EM_PWM2 8
924
925#define STELLARIS_ADC_FIFO_EMPTY 0x0100
926#define STELLARIS_ADC_FIFO_FULL 0x1000
927
928#define TYPE_STELLARIS_ADC "stellaris-adc"
929#define STELLARIS_ADC(obj) \
930 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
931
932typedef struct StellarisADCState {
933 SysBusDevice parent_obj;
934
935 MemoryRegion iomem;
936 uint32_t actss;
937 uint32_t ris;
938 uint32_t im;
939 uint32_t emux;
940 uint32_t ostat;
941 uint32_t ustat;
942 uint32_t sspri;
943 uint32_t sac;
944 struct {
945 uint32_t state;
946 uint32_t data[16];
947 } fifo[4];
948 uint32_t ssmux[4];
949 uint32_t ssctl[4];
950 uint32_t noise;
951 qemu_irq irq[4];
952} stellaris_adc_state;
953
954static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
955{
956 int tail;
957
958 tail = s->fifo[n].state & 0xf;
959 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
960 s->ustat |= 1 << n;
961 } else {
962 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
963 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
964 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
965 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
966 }
967 return s->fifo[n].data[tail];
968}
969
970static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
971 uint32_t value)
972{
973 int head;
974
975
976
977 head = (s->fifo[n].state >> 4) & 0xf;
978 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
979 s->ostat |= 1 << n;
980 return;
981 }
982 s->fifo[n].data[head] = value;
983 head = (head + 1) & 0xf;
984 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
985 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
986 if ((s->fifo[n].state & 0xf) == head)
987 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
988}
989
990static void stellaris_adc_update(stellaris_adc_state *s)
991{
992 int level;
993 int n;
994
995 for (n = 0; n < 4; n++) {
996 level = (s->ris & s->im & (1 << n)) != 0;
997 qemu_set_irq(s->irq[n], level);
998 }
999}
1000
1001static void stellaris_adc_trigger(void *opaque, int irq, int level)
1002{
1003 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1004 int n;
1005
1006 for (n = 0; n < 4; n++) {
1007 if ((s->actss & (1 << n)) == 0) {
1008 continue;
1009 }
1010
1011 if (((s->emux >> (n * 4)) & 0xff) != 5) {
1012 continue;
1013 }
1014
1015
1016
1017 s->noise = s->noise * 314159 + 1;
1018
1019 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
1020 s->ris |= (1 << n);
1021 stellaris_adc_update(s);
1022 }
1023}
1024
1025static void stellaris_adc_reset(stellaris_adc_state *s)
1026{
1027 int n;
1028
1029 for (n = 0; n < 4; n++) {
1030 s->ssmux[n] = 0;
1031 s->ssctl[n] = 0;
1032 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1033 }
1034}
1035
1036static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1037 unsigned size)
1038{
1039 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1040
1041
1042 if (offset >= 0x40 && offset < 0xc0) {
1043 int n;
1044 n = (offset - 0x40) >> 5;
1045 switch (offset & 0x1f) {
1046 case 0x00:
1047 return s->ssmux[n];
1048 case 0x04:
1049 return s->ssctl[n];
1050 case 0x08:
1051 return stellaris_adc_fifo_read(s, n);
1052 case 0x0c:
1053 return s->fifo[n].state;
1054 default:
1055 break;
1056 }
1057 }
1058 switch (offset) {
1059 case 0x00:
1060 return s->actss;
1061 case 0x04:
1062 return s->ris;
1063 case 0x08:
1064 return s->im;
1065 case 0x0c:
1066 return s->ris & s->im;
1067 case 0x10:
1068 return s->ostat;
1069 case 0x14:
1070 return s->emux;
1071 case 0x18:
1072 return s->ustat;
1073 case 0x20:
1074 return s->sspri;
1075 case 0x30:
1076 return s->sac;
1077 default:
1078 qemu_log_mask(LOG_GUEST_ERROR,
1079 "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
1080 return 0;
1081 }
1082}
1083
1084static void stellaris_adc_write(void *opaque, hwaddr offset,
1085 uint64_t value, unsigned size)
1086{
1087 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1088
1089
1090 if (offset >= 0x40 && offset < 0xc0) {
1091 int n;
1092 n = (offset - 0x40) >> 5;
1093 switch (offset & 0x1f) {
1094 case 0x00:
1095 s->ssmux[n] = value & 0x33333333;
1096 return;
1097 case 0x04:
1098 if (value != 6) {
1099 qemu_log_mask(LOG_UNIMP,
1100 "ADC: Unimplemented sequence %" PRIx64 "\n",
1101 value);
1102 }
1103 s->ssctl[n] = value;
1104 return;
1105 default:
1106 break;
1107 }
1108 }
1109 switch (offset) {
1110 case 0x00:
1111 s->actss = value & 0xf;
1112 break;
1113 case 0x08:
1114 s->im = value;
1115 break;
1116 case 0x0c:
1117 s->ris &= ~value;
1118 break;
1119 case 0x10:
1120 s->ostat &= ~value;
1121 break;
1122 case 0x14:
1123 s->emux = value;
1124 break;
1125 case 0x18:
1126 s->ustat &= ~value;
1127 break;
1128 case 0x20:
1129 s->sspri = value;
1130 break;
1131 case 0x28:
1132 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
1133 break;
1134 case 0x30:
1135 s->sac = value;
1136 break;
1137 default:
1138 qemu_log_mask(LOG_GUEST_ERROR,
1139 "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
1140 }
1141 stellaris_adc_update(s);
1142}
1143
1144static const MemoryRegionOps stellaris_adc_ops = {
1145 .read = stellaris_adc_read,
1146 .write = stellaris_adc_write,
1147 .endianness = DEVICE_NATIVE_ENDIAN,
1148};
1149
1150static const VMStateDescription vmstate_stellaris_adc = {
1151 .name = "stellaris_adc",
1152 .version_id = 1,
1153 .minimum_version_id = 1,
1154 .fields = (VMStateField[]) {
1155 VMSTATE_UINT32(actss, stellaris_adc_state),
1156 VMSTATE_UINT32(ris, stellaris_adc_state),
1157 VMSTATE_UINT32(im, stellaris_adc_state),
1158 VMSTATE_UINT32(emux, stellaris_adc_state),
1159 VMSTATE_UINT32(ostat, stellaris_adc_state),
1160 VMSTATE_UINT32(ustat, stellaris_adc_state),
1161 VMSTATE_UINT32(sspri, stellaris_adc_state),
1162 VMSTATE_UINT32(sac, stellaris_adc_state),
1163 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1164 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1165 VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1166 VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1167 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1168 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1169 VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1170 VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1171 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1172 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1173 VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1174 VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1175 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1176 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1177 VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1178 VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1179 VMSTATE_UINT32(noise, stellaris_adc_state),
1180 VMSTATE_END_OF_LIST()
1181 }
1182};
1183
1184static void stellaris_adc_init(Object *obj)
1185{
1186 DeviceState *dev = DEVICE(obj);
1187 stellaris_adc_state *s = STELLARIS_ADC(obj);
1188 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1189 int n;
1190
1191 for (n = 0; n < 4; n++) {
1192 sysbus_init_irq(sbd, &s->irq[n]);
1193 }
1194
1195 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
1196 "adc", 0x1000);
1197 sysbus_init_mmio(sbd, &s->iomem);
1198 stellaris_adc_reset(s);
1199 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1200}
1201
1202static
1203void do_sys_reset(void *opaque, int n, int level)
1204{
1205 if (level) {
1206 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1207 }
1208}
1209
1210
1211static stellaris_board_info stellaris_boards[] = {
1212 { "LM3S811EVB",
1213 0,
1214 0x0032000e,
1215 0x001f001f,
1216 0x001132bf,
1217 0x01071013,
1218 0x3f0f01ff,
1219 0x0000001f,
1220 BP_OLED_I2C
1221 },
1222 { "LM3S6965EVB",
1223 0x10010002,
1224 0x1073402e,
1225 0x00ff007f,
1226 0x001133ff,
1227 0x030f5317,
1228 0x0f0f87ff,
1229 0x5000007f,
1230 BP_OLED_SSI | BP_GAMEPAD
1231 }
1232};
1233
1234static void stellaris_init(MachineState *ms, stellaris_board_info *board)
1235{
1236 static const int uart_irq[] = {5, 6, 33, 34};
1237 static const int timer_irq[] = {19, 21, 23, 35};
1238 static const uint32_t gpio_addr[7] =
1239 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1240 0x40024000, 0x40025000, 0x40026000};
1241 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277 DeviceState *gpio_dev[7], *nvic;
1278 qemu_irq gpio_in[7][8];
1279 qemu_irq gpio_out[7][8];
1280 qemu_irq adc;
1281 int sram_size;
1282 int flash_size;
1283 I2CBus *i2c;
1284 DeviceState *dev;
1285 int i;
1286 int j;
1287
1288 MemoryRegion *sram = g_new(MemoryRegion, 1);
1289 MemoryRegion *flash = g_new(MemoryRegion, 1);
1290 MemoryRegion *system_memory = get_system_memory();
1291
1292 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1293 sram_size = ((board->dc0 >> 18) + 1) * 1024;
1294
1295
1296 memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size,
1297 &error_fatal);
1298 memory_region_set_readonly(flash, true);
1299 memory_region_add_subregion(system_memory, 0, flash);
1300
1301 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1302 &error_fatal);
1303 memory_region_add_subregion(system_memory, 0x20000000, sram);
1304
1305 nvic = qdev_create(NULL, TYPE_ARMV7M);
1306 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
1307 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
1308 qdev_prop_set_bit(nvic, "enable-bitband", true);
1309 object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()),
1310 "memory", &error_abort);
1311
1312 qdev_init_nofail(nvic);
1313
1314 qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
1315 qemu_allocate_irq(&do_sys_reset, NULL, 0));
1316
1317 if (board->dc1 & (1 << 16)) {
1318 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1319 qdev_get_gpio_in(nvic, 14),
1320 qdev_get_gpio_in(nvic, 15),
1321 qdev_get_gpio_in(nvic, 16),
1322 qdev_get_gpio_in(nvic, 17),
1323 NULL);
1324 adc = qdev_get_gpio_in(dev, 0);
1325 } else {
1326 adc = NULL;
1327 }
1328 for (i = 0; i < 4; i++) {
1329 if (board->dc2 & (0x10000 << i)) {
1330 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1331 0x40030000 + i * 0x1000,
1332 qdev_get_gpio_in(nvic, timer_irq[i]));
1333
1334
1335 qdev_connect_gpio_out(dev, 0, adc);
1336 }
1337 }
1338
1339 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
1340 board, nd_table[0].macaddr.a);
1341
1342
1343 if (board->dc1 & (1 << 3)) {
1344 dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG);
1345
1346
1347 uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
1348 qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
1349
1350 qdev_init_nofail(dev);
1351 sysbus_mmio_map(SYS_BUS_DEVICE(dev),
1352 0,
1353 0x40000000u);
1354 sysbus_connect_irq(SYS_BUS_DEVICE(dev),
1355 0,
1356 qdev_get_gpio_in(nvic, 18));
1357 }
1358
1359
1360 for (i = 0; i < 7; i++) {
1361 if (board->dc4 & (1 << i)) {
1362 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1363 qdev_get_gpio_in(nvic,
1364 gpio_irq[i]));
1365 for (j = 0; j < 8; j++) {
1366 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1367 gpio_out[i][j] = NULL;
1368 }
1369 }
1370 }
1371
1372 if (board->dc2 & (1 << 12)) {
1373 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1374 qdev_get_gpio_in(nvic, 8));
1375 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1376 if (board->peripherals & BP_OLED_I2C) {
1377 i2c_create_slave(i2c, "ssd0303", 0x3d);
1378 }
1379 }
1380
1381 for (i = 0; i < 4; i++) {
1382 if (board->dc2 & (1 << i)) {
1383 pl011_luminary_create(0x4000c000 + i * 0x1000,
1384 qdev_get_gpio_in(nvic, uart_irq[i]),
1385 serial_hd(i));
1386 }
1387 }
1388 if (board->dc2 & (1 << 4)) {
1389 dev = sysbus_create_simple("pl022", 0x40008000,
1390 qdev_get_gpio_in(nvic, 7));
1391 if (board->peripherals & BP_OLED_SSI) {
1392 void *bus;
1393 DeviceState *sddev;
1394 DeviceState *ssddev;
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404 bus = qdev_get_child_bus(dev, "ssi");
1405
1406 sddev = ssi_create_slave(bus, "ssi-sd");
1407 ssddev = ssi_create_slave(bus, "ssd0323");
1408 gpio_out[GPIO_D][0] = qemu_irq_split(
1409 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1410 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1411 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1412
1413
1414 qemu_irq_raise(gpio_out[GPIO_D][0]);
1415 }
1416 }
1417 if (board->dc4 & (1 << 28)) {
1418 DeviceState *enet;
1419
1420 qemu_check_nic_model(&nd_table[0], "stellaris");
1421
1422 enet = qdev_create(NULL, "stellaris_enet");
1423 qdev_set_nic_properties(enet, &nd_table[0]);
1424 qdev_init_nofail(enet);
1425 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1426 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1427 }
1428 if (board->peripherals & BP_GAMEPAD) {
1429 qemu_irq gpad_irq[5];
1430 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1431
1432 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]);
1433 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]);
1434 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]);
1435 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]);
1436 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]);
1437
1438 stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1439 }
1440 for (i = 0; i < 7; i++) {
1441 if (board->dc4 & (1 << i)) {
1442 for (j = 0; j < 8; j++) {
1443 if (gpio_out[i][j]) {
1444 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1445 }
1446 }
1447 }
1448 }
1449
1450
1451
1452
1453 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1454 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1455 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1456 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1457 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1458 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1459 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1460 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1461
1462 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size);
1463}
1464
1465
1466static void lm3s811evb_init(MachineState *machine)
1467{
1468 stellaris_init(machine, &stellaris_boards[0]);
1469}
1470
1471static void lm3s6965evb_init(MachineState *machine)
1472{
1473 stellaris_init(machine, &stellaris_boards[1]);
1474}
1475
1476static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1477{
1478 MachineClass *mc = MACHINE_CLASS(oc);
1479
1480 mc->desc = "Stellaris LM3S811EVB";
1481 mc->init = lm3s811evb_init;
1482 mc->ignore_memory_transaction_failures = true;
1483 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1484}
1485
1486static const TypeInfo lm3s811evb_type = {
1487 .name = MACHINE_TYPE_NAME("lm3s811evb"),
1488 .parent = TYPE_MACHINE,
1489 .class_init = lm3s811evb_class_init,
1490};
1491
1492static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1493{
1494 MachineClass *mc = MACHINE_CLASS(oc);
1495
1496 mc->desc = "Stellaris LM3S6965EVB";
1497 mc->init = lm3s6965evb_init;
1498 mc->ignore_memory_transaction_failures = true;
1499 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1500}
1501
1502static const TypeInfo lm3s6965evb_type = {
1503 .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1504 .parent = TYPE_MACHINE,
1505 .class_init = lm3s6965evb_class_init,
1506};
1507
1508static void stellaris_machine_init(void)
1509{
1510 type_register_static(&lm3s811evb_type);
1511 type_register_static(&lm3s6965evb_type);
1512}
1513
1514type_init(stellaris_machine_init)
1515
1516static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1517{
1518 DeviceClass *dc = DEVICE_CLASS(klass);
1519
1520 dc->vmsd = &vmstate_stellaris_i2c;
1521}
1522
1523static const TypeInfo stellaris_i2c_info = {
1524 .name = TYPE_STELLARIS_I2C,
1525 .parent = TYPE_SYS_BUS_DEVICE,
1526 .instance_size = sizeof(stellaris_i2c_state),
1527 .instance_init = stellaris_i2c_init,
1528 .class_init = stellaris_i2c_class_init,
1529};
1530
1531static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1532{
1533 DeviceClass *dc = DEVICE_CLASS(klass);
1534
1535 dc->vmsd = &vmstate_stellaris_gptm;
1536}
1537
1538static const TypeInfo stellaris_gptm_info = {
1539 .name = TYPE_STELLARIS_GPTM,
1540 .parent = TYPE_SYS_BUS_DEVICE,
1541 .instance_size = sizeof(gptm_state),
1542 .instance_init = stellaris_gptm_init,
1543 .class_init = stellaris_gptm_class_init,
1544};
1545
1546static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1547{
1548 DeviceClass *dc = DEVICE_CLASS(klass);
1549
1550 dc->vmsd = &vmstate_stellaris_adc;
1551}
1552
1553static const TypeInfo stellaris_adc_info = {
1554 .name = TYPE_STELLARIS_ADC,
1555 .parent = TYPE_SYS_BUS_DEVICE,
1556 .instance_size = sizeof(stellaris_adc_state),
1557 .instance_init = stellaris_adc_init,
1558 .class_init = stellaris_adc_class_init,
1559};
1560
1561static void stellaris_register_types(void)
1562{
1563 type_register_static(&stellaris_i2c_info);
1564 type_register_static(&stellaris_gptm_info);
1565 type_register_static(&stellaris_adc_info);
1566}
1567
1568type_init(stellaris_register_types)
1569