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30#include "qemu/osdep.h"
31#include "qemu-common.h"
32#include "cpu.h"
33#include "hw/boards.h"
34#include "hw/sysbus.h"
35#include "strongarm.h"
36#include "qemu/error-report.h"
37#include "hw/arm/boot.h"
38#include "chardev/char-fe.h"
39#include "chardev/char-serial.h"
40#include "sysemu/sysemu.h"
41#include "hw/ssi/ssi.h"
42#include "qemu/cutils.h"
43#include "qemu/log.h"
44
45
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63
64#ifdef DEBUG
65# define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
66#else
67# define DPRINTF(format, ...) do { } while (0)
68#endif
69
70static struct {
71 hwaddr io_base;
72 int irq;
73} sa_serial[] = {
74 { 0x80010000, SA_PIC_UART1 },
75 { 0x80030000, SA_PIC_UART2 },
76 { 0x80050000, SA_PIC_UART3 },
77 { 0, 0 }
78};
79
80
81
82#define TYPE_STRONGARM_PIC "strongarm_pic"
83#define STRONGARM_PIC(obj) \
84 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
85
86typedef struct StrongARMPICState {
87 SysBusDevice parent_obj;
88
89 MemoryRegion iomem;
90 qemu_irq irq;
91 qemu_irq fiq;
92
93 uint32_t pending;
94 uint32_t enabled;
95 uint32_t is_fiq;
96 uint32_t int_idle;
97} StrongARMPICState;
98
99#define ICIP 0x00
100#define ICMR 0x04
101#define ICLR 0x08
102#define ICFP 0x10
103#define ICPR 0x20
104#define ICCR 0x0c
105
106#define SA_PIC_SRCS 32
107
108
109static void strongarm_pic_update(void *opaque)
110{
111 StrongARMPICState *s = opaque;
112
113
114 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq);
115 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
116}
117
118static void strongarm_pic_set_irq(void *opaque, int irq, int level)
119{
120 StrongARMPICState *s = opaque;
121
122 if (level) {
123 s->pending |= 1 << irq;
124 } else {
125 s->pending &= ~(1 << irq);
126 }
127
128 strongarm_pic_update(s);
129}
130
131static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
132 unsigned size)
133{
134 StrongARMPICState *s = opaque;
135
136 switch (offset) {
137 case ICIP:
138 return s->pending & ~s->is_fiq & s->enabled;
139 case ICMR:
140 return s->enabled;
141 case ICLR:
142 return s->is_fiq;
143 case ICCR:
144 return s->int_idle == 0;
145 case ICFP:
146 return s->pending & s->is_fiq & s->enabled;
147 case ICPR:
148 return s->pending;
149 default:
150 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
151 __func__, offset);
152 return 0;
153 }
154}
155
156static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
157 uint64_t value, unsigned size)
158{
159 StrongARMPICState *s = opaque;
160
161 switch (offset) {
162 case ICMR:
163 s->enabled = value;
164 break;
165 case ICLR:
166 s->is_fiq = value;
167 break;
168 case ICCR:
169 s->int_idle = (value & 1) ? 0 : ~0;
170 break;
171 default:
172 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
173 __func__, offset);
174 break;
175 }
176 strongarm_pic_update(s);
177}
178
179static const MemoryRegionOps strongarm_pic_ops = {
180 .read = strongarm_pic_mem_read,
181 .write = strongarm_pic_mem_write,
182 .endianness = DEVICE_NATIVE_ENDIAN,
183};
184
185static void strongarm_pic_initfn(Object *obj)
186{
187 DeviceState *dev = DEVICE(obj);
188 StrongARMPICState *s = STRONGARM_PIC(obj);
189 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
190
191 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
192 memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s,
193 "pic", 0x1000);
194 sysbus_init_mmio(sbd, &s->iomem);
195 sysbus_init_irq(sbd, &s->irq);
196 sysbus_init_irq(sbd, &s->fiq);
197}
198
199static int strongarm_pic_post_load(void *opaque, int version_id)
200{
201 strongarm_pic_update(opaque);
202 return 0;
203}
204
205static VMStateDescription vmstate_strongarm_pic_regs = {
206 .name = "strongarm_pic",
207 .version_id = 0,
208 .minimum_version_id = 0,
209 .post_load = strongarm_pic_post_load,
210 .fields = (VMStateField[]) {
211 VMSTATE_UINT32(pending, StrongARMPICState),
212 VMSTATE_UINT32(enabled, StrongARMPICState),
213 VMSTATE_UINT32(is_fiq, StrongARMPICState),
214 VMSTATE_UINT32(int_idle, StrongARMPICState),
215 VMSTATE_END_OF_LIST(),
216 },
217};
218
219static void strongarm_pic_class_init(ObjectClass *klass, void *data)
220{
221 DeviceClass *dc = DEVICE_CLASS(klass);
222
223 dc->desc = "StrongARM PIC";
224 dc->vmsd = &vmstate_strongarm_pic_regs;
225}
226
227static const TypeInfo strongarm_pic_info = {
228 .name = TYPE_STRONGARM_PIC,
229 .parent = TYPE_SYS_BUS_DEVICE,
230 .instance_size = sizeof(StrongARMPICState),
231 .instance_init = strongarm_pic_initfn,
232 .class_init = strongarm_pic_class_init,
233};
234
235
236#define RTAR 0x00
237#define RCNR 0x04
238#define RTTR 0x08
239#define RTSR 0x10
240
241#define RTSR_AL (1 << 0)
242#define RTSR_HZ (1 << 1)
243#define RTSR_ALE (1 << 2)
244#define RTSR_HZE (1 << 3)
245
246
247
248
249
250#define TYPE_STRONGARM_RTC "strongarm-rtc"
251#define STRONGARM_RTC(obj) \
252 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
253
254typedef struct StrongARMRTCState {
255 SysBusDevice parent_obj;
256
257 MemoryRegion iomem;
258 uint32_t rttr;
259 uint32_t rtsr;
260 uint32_t rtar;
261 uint32_t last_rcnr;
262 int64_t last_hz;
263 QEMUTimer *rtc_alarm;
264 QEMUTimer *rtc_hz;
265 qemu_irq rtc_irq;
266 qemu_irq rtc_hz_irq;
267} StrongARMRTCState;
268
269static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
270{
271 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
272 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
273}
274
275static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
276{
277 int64_t rt = qemu_clock_get_ms(rtc_clock);
278 s->last_rcnr += ((rt - s->last_hz) << 15) /
279 (1000 * ((s->rttr & 0xffff) + 1));
280 s->last_hz = rt;
281}
282
283static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
284{
285 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
286 timer_mod(s->rtc_hz, s->last_hz + 1000);
287 } else {
288 timer_del(s->rtc_hz);
289 }
290
291 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
292 timer_mod(s->rtc_alarm, s->last_hz +
293 (((s->rtar - s->last_rcnr) * 1000 *
294 ((s->rttr & 0xffff) + 1)) >> 15));
295 } else {
296 timer_del(s->rtc_alarm);
297 }
298}
299
300static inline void strongarm_rtc_alarm_tick(void *opaque)
301{
302 StrongARMRTCState *s = opaque;
303 s->rtsr |= RTSR_AL;
304 strongarm_rtc_timer_update(s);
305 strongarm_rtc_int_update(s);
306}
307
308static inline void strongarm_rtc_hz_tick(void *opaque)
309{
310 StrongARMRTCState *s = opaque;
311 s->rtsr |= RTSR_HZ;
312 strongarm_rtc_timer_update(s);
313 strongarm_rtc_int_update(s);
314}
315
316static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
317 unsigned size)
318{
319 StrongARMRTCState *s = opaque;
320
321 switch (addr) {
322 case RTTR:
323 return s->rttr;
324 case RTSR:
325 return s->rtsr;
326 case RTAR:
327 return s->rtar;
328 case RCNR:
329 return s->last_rcnr +
330 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
331 (1000 * ((s->rttr & 0xffff) + 1));
332 default:
333 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
334 return 0;
335 }
336}
337
338static void strongarm_rtc_write(void *opaque, hwaddr addr,
339 uint64_t value, unsigned size)
340{
341 StrongARMRTCState *s = opaque;
342 uint32_t old_rtsr;
343
344 switch (addr) {
345 case RTTR:
346 strongarm_rtc_hzupdate(s);
347 s->rttr = value;
348 strongarm_rtc_timer_update(s);
349 break;
350
351 case RTSR:
352 old_rtsr = s->rtsr;
353 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
354 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
355
356 if (s->rtsr != old_rtsr) {
357 strongarm_rtc_timer_update(s);
358 }
359
360 strongarm_rtc_int_update(s);
361 break;
362
363 case RTAR:
364 s->rtar = value;
365 strongarm_rtc_timer_update(s);
366 break;
367
368 case RCNR:
369 strongarm_rtc_hzupdate(s);
370 s->last_rcnr = value;
371 strongarm_rtc_timer_update(s);
372 break;
373
374 default:
375 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
376 }
377}
378
379static const MemoryRegionOps strongarm_rtc_ops = {
380 .read = strongarm_rtc_read,
381 .write = strongarm_rtc_write,
382 .endianness = DEVICE_NATIVE_ENDIAN,
383};
384
385static void strongarm_rtc_init(Object *obj)
386{
387 StrongARMRTCState *s = STRONGARM_RTC(obj);
388 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
389 struct tm tm;
390
391 s->rttr = 0x0;
392 s->rtsr = 0;
393
394 qemu_get_timedate(&tm, 0);
395
396 s->last_rcnr = (uint32_t) mktimegm(&tm);
397 s->last_hz = qemu_clock_get_ms(rtc_clock);
398
399 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
400 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s);
401
402 sysbus_init_irq(dev, &s->rtc_irq);
403 sysbus_init_irq(dev, &s->rtc_hz_irq);
404
405 memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s,
406 "rtc", 0x10000);
407 sysbus_init_mmio(dev, &s->iomem);
408}
409
410static int strongarm_rtc_pre_save(void *opaque)
411{
412 StrongARMRTCState *s = opaque;
413
414 strongarm_rtc_hzupdate(s);
415
416 return 0;
417}
418
419static int strongarm_rtc_post_load(void *opaque, int version_id)
420{
421 StrongARMRTCState *s = opaque;
422
423 strongarm_rtc_timer_update(s);
424 strongarm_rtc_int_update(s);
425
426 return 0;
427}
428
429static const VMStateDescription vmstate_strongarm_rtc_regs = {
430 .name = "strongarm-rtc",
431 .version_id = 0,
432 .minimum_version_id = 0,
433 .pre_save = strongarm_rtc_pre_save,
434 .post_load = strongarm_rtc_post_load,
435 .fields = (VMStateField[]) {
436 VMSTATE_UINT32(rttr, StrongARMRTCState),
437 VMSTATE_UINT32(rtsr, StrongARMRTCState),
438 VMSTATE_UINT32(rtar, StrongARMRTCState),
439 VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
440 VMSTATE_INT64(last_hz, StrongARMRTCState),
441 VMSTATE_END_OF_LIST(),
442 },
443};
444
445static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
446{
447 DeviceClass *dc = DEVICE_CLASS(klass);
448
449 dc->desc = "StrongARM RTC Controller";
450 dc->vmsd = &vmstate_strongarm_rtc_regs;
451}
452
453static const TypeInfo strongarm_rtc_sysbus_info = {
454 .name = TYPE_STRONGARM_RTC,
455 .parent = TYPE_SYS_BUS_DEVICE,
456 .instance_size = sizeof(StrongARMRTCState),
457 .instance_init = strongarm_rtc_init,
458 .class_init = strongarm_rtc_sysbus_class_init,
459};
460
461
462#define GPLR 0x00
463#define GPDR 0x04
464#define GPSR 0x08
465#define GPCR 0x0c
466#define GRER 0x10
467#define GFER 0x14
468#define GEDR 0x18
469#define GAFR 0x1c
470
471#define TYPE_STRONGARM_GPIO "strongarm-gpio"
472#define STRONGARM_GPIO(obj) \
473 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
474
475typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
476struct StrongARMGPIOInfo {
477 SysBusDevice busdev;
478 MemoryRegion iomem;
479 qemu_irq handler[28];
480 qemu_irq irqs[11];
481 qemu_irq irqX;
482
483 uint32_t ilevel;
484 uint32_t olevel;
485 uint32_t dir;
486 uint32_t rising;
487 uint32_t falling;
488 uint32_t status;
489 uint32_t gafr;
490
491 uint32_t prev_level;
492};
493
494
495static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
496{
497 int i;
498 for (i = 0; i < 11; i++) {
499 qemu_set_irq(s->irqs[i], s->status & (1 << i));
500 }
501
502 qemu_set_irq(s->irqX, (s->status & ~0x7ff));
503}
504
505static void strongarm_gpio_set(void *opaque, int line, int level)
506{
507 StrongARMGPIOInfo *s = opaque;
508 uint32_t mask;
509
510 mask = 1 << line;
511
512 if (level) {
513 s->status |= s->rising & mask &
514 ~s->ilevel & ~s->dir;
515 s->ilevel |= mask;
516 } else {
517 s->status |= s->falling & mask &
518 s->ilevel & ~s->dir;
519 s->ilevel &= ~mask;
520 }
521
522 if (s->status & mask) {
523 strongarm_gpio_irq_update(s);
524 }
525}
526
527static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
528{
529 uint32_t level, diff;
530 int bit;
531
532 level = s->olevel & s->dir;
533
534 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
535 bit = ctz32(diff);
536 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
537 }
538
539 s->prev_level = level;
540}
541
542static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
543 unsigned size)
544{
545 StrongARMGPIOInfo *s = opaque;
546
547 switch (offset) {
548 case GPDR:
549 return s->dir;
550
551 case GPSR:
552 qemu_log_mask(LOG_GUEST_ERROR,
553 "strongarm GPIO: read from write only register GPSR\n");
554 return 0;
555
556 case GPCR:
557 qemu_log_mask(LOG_GUEST_ERROR,
558 "strongarm GPIO: read from write only register GPCR\n");
559 return 0;
560
561 case GRER:
562 return s->rising;
563
564 case GFER:
565 return s->falling;
566
567 case GAFR:
568 return s->gafr;
569
570 case GPLR:
571 return (s->olevel & s->dir) |
572 (s->ilevel & ~s->dir);
573
574 case GEDR:
575 return s->status;
576
577 default:
578 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
579 }
580
581 return 0;
582}
583
584static void strongarm_gpio_write(void *opaque, hwaddr offset,
585 uint64_t value, unsigned size)
586{
587 StrongARMGPIOInfo *s = opaque;
588
589 switch (offset) {
590 case GPDR:
591 s->dir = value & 0x0fffffff;
592 strongarm_gpio_handler_update(s);
593 break;
594
595 case GPSR:
596 s->olevel |= value & 0x0fffffff;
597 strongarm_gpio_handler_update(s);
598 break;
599
600 case GPCR:
601 s->olevel &= ~value;
602 strongarm_gpio_handler_update(s);
603 break;
604
605 case GRER:
606 s->rising = value;
607 break;
608
609 case GFER:
610 s->falling = value;
611 break;
612
613 case GAFR:
614 s->gafr = value;
615 break;
616
617 case GEDR:
618 s->status &= ~value;
619 strongarm_gpio_irq_update(s);
620 break;
621
622 default:
623 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
624 }
625}
626
627static const MemoryRegionOps strongarm_gpio_ops = {
628 .read = strongarm_gpio_read,
629 .write = strongarm_gpio_write,
630 .endianness = DEVICE_NATIVE_ENDIAN,
631};
632
633static DeviceState *strongarm_gpio_init(hwaddr base,
634 DeviceState *pic)
635{
636 DeviceState *dev;
637 int i;
638
639 dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
640 qdev_init_nofail(dev);
641
642 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
643 for (i = 0; i < 12; i++)
644 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
645 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
646
647 return dev;
648}
649
650static void strongarm_gpio_initfn(Object *obj)
651{
652 DeviceState *dev = DEVICE(obj);
653 StrongARMGPIOInfo *s = STRONGARM_GPIO(obj);
654 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
655 int i;
656
657 qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
658 qdev_init_gpio_out(dev, s->handler, 28);
659
660 memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s,
661 "gpio", 0x1000);
662
663 sysbus_init_mmio(sbd, &s->iomem);
664 for (i = 0; i < 11; i++) {
665 sysbus_init_irq(sbd, &s->irqs[i]);
666 }
667 sysbus_init_irq(sbd, &s->irqX);
668}
669
670static const VMStateDescription vmstate_strongarm_gpio_regs = {
671 .name = "strongarm-gpio",
672 .version_id = 0,
673 .minimum_version_id = 0,
674 .fields = (VMStateField[]) {
675 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
676 VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
677 VMSTATE_UINT32(dir, StrongARMGPIOInfo),
678 VMSTATE_UINT32(rising, StrongARMGPIOInfo),
679 VMSTATE_UINT32(falling, StrongARMGPIOInfo),
680 VMSTATE_UINT32(status, StrongARMGPIOInfo),
681 VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
682 VMSTATE_UINT32(prev_level, StrongARMGPIOInfo),
683 VMSTATE_END_OF_LIST(),
684 },
685};
686
687static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
688{
689 DeviceClass *dc = DEVICE_CLASS(klass);
690
691 dc->desc = "StrongARM GPIO controller";
692 dc->vmsd = &vmstate_strongarm_gpio_regs;
693}
694
695static const TypeInfo strongarm_gpio_info = {
696 .name = TYPE_STRONGARM_GPIO,
697 .parent = TYPE_SYS_BUS_DEVICE,
698 .instance_size = sizeof(StrongARMGPIOInfo),
699 .instance_init = strongarm_gpio_initfn,
700 .class_init = strongarm_gpio_class_init,
701};
702
703
704#define PPDR 0x00
705#define PPSR 0x04
706#define PPAR 0x08
707#define PSDR 0x0c
708#define PPFR 0x10
709
710#define TYPE_STRONGARM_PPC "strongarm-ppc"
711#define STRONGARM_PPC(obj) \
712 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
713
714typedef struct StrongARMPPCInfo StrongARMPPCInfo;
715struct StrongARMPPCInfo {
716 SysBusDevice parent_obj;
717
718 MemoryRegion iomem;
719 qemu_irq handler[28];
720
721 uint32_t ilevel;
722 uint32_t olevel;
723 uint32_t dir;
724 uint32_t ppar;
725 uint32_t psdr;
726 uint32_t ppfr;
727
728 uint32_t prev_level;
729};
730
731static void strongarm_ppc_set(void *opaque, int line, int level)
732{
733 StrongARMPPCInfo *s = opaque;
734
735 if (level) {
736 s->ilevel |= 1 << line;
737 } else {
738 s->ilevel &= ~(1 << line);
739 }
740}
741
742static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
743{
744 uint32_t level, diff;
745 int bit;
746
747 level = s->olevel & s->dir;
748
749 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
750 bit = ctz32(diff);
751 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
752 }
753
754 s->prev_level = level;
755}
756
757static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
758 unsigned size)
759{
760 StrongARMPPCInfo *s = opaque;
761
762 switch (offset) {
763 case PPDR:
764 return s->dir | ~0x3fffff;
765
766 case PPSR:
767 return (s->olevel & s->dir) |
768 (s->ilevel & ~s->dir) |
769 ~0x3fffff;
770
771 case PPAR:
772 return s->ppar | ~0x41000;
773
774 case PSDR:
775 return s->psdr;
776
777 case PPFR:
778 return s->ppfr | ~0x7f001;
779
780 default:
781 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
782 }
783
784 return 0;
785}
786
787static void strongarm_ppc_write(void *opaque, hwaddr offset,
788 uint64_t value, unsigned size)
789{
790 StrongARMPPCInfo *s = opaque;
791
792 switch (offset) {
793 case PPDR:
794 s->dir = value & 0x3fffff;
795 strongarm_ppc_handler_update(s);
796 break;
797
798 case PPSR:
799 s->olevel = value & s->dir & 0x3fffff;
800 strongarm_ppc_handler_update(s);
801 break;
802
803 case PPAR:
804 s->ppar = value & 0x41000;
805 break;
806
807 case PSDR:
808 s->psdr = value & 0x3fffff;
809 break;
810
811 case PPFR:
812 s->ppfr = value & 0x7f001;
813 break;
814
815 default:
816 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
817 }
818}
819
820static const MemoryRegionOps strongarm_ppc_ops = {
821 .read = strongarm_ppc_read,
822 .write = strongarm_ppc_write,
823 .endianness = DEVICE_NATIVE_ENDIAN,
824};
825
826static void strongarm_ppc_init(Object *obj)
827{
828 DeviceState *dev = DEVICE(obj);
829 StrongARMPPCInfo *s = STRONGARM_PPC(obj);
830 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
831
832 qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
833 qdev_init_gpio_out(dev, s->handler, 22);
834
835 memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s,
836 "ppc", 0x1000);
837
838 sysbus_init_mmio(sbd, &s->iomem);
839}
840
841static const VMStateDescription vmstate_strongarm_ppc_regs = {
842 .name = "strongarm-ppc",
843 .version_id = 0,
844 .minimum_version_id = 0,
845 .fields = (VMStateField[]) {
846 VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
847 VMSTATE_UINT32(olevel, StrongARMPPCInfo),
848 VMSTATE_UINT32(dir, StrongARMPPCInfo),
849 VMSTATE_UINT32(ppar, StrongARMPPCInfo),
850 VMSTATE_UINT32(psdr, StrongARMPPCInfo),
851 VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
852 VMSTATE_UINT32(prev_level, StrongARMPPCInfo),
853 VMSTATE_END_OF_LIST(),
854 },
855};
856
857static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
858{
859 DeviceClass *dc = DEVICE_CLASS(klass);
860
861 dc->desc = "StrongARM PPC controller";
862 dc->vmsd = &vmstate_strongarm_ppc_regs;
863}
864
865static const TypeInfo strongarm_ppc_info = {
866 .name = TYPE_STRONGARM_PPC,
867 .parent = TYPE_SYS_BUS_DEVICE,
868 .instance_size = sizeof(StrongARMPPCInfo),
869 .instance_init = strongarm_ppc_init,
870 .class_init = strongarm_ppc_class_init,
871};
872
873
874#define UTCR0 0x00
875#define UTCR1 0x04
876#define UTCR2 0x08
877#define UTCR3 0x0c
878#define UTDR 0x14
879#define UTSR0 0x1c
880#define UTSR1 0x20
881
882#define UTCR0_PE (1 << 0)
883#define UTCR0_OES (1 << 1)
884#define UTCR0_SBS (1 << 2)
885#define UTCR0_DSS (1 << 3)
886
887#define UTCR3_RXE (1 << 0)
888#define UTCR3_TXE (1 << 1)
889#define UTCR3_BRK (1 << 2)
890#define UTCR3_RIE (1 << 3)
891#define UTCR3_TIE (1 << 4)
892#define UTCR3_LBM (1 << 5)
893
894#define UTSR0_TFS (1 << 0)
895#define UTSR0_RFS (1 << 1)
896#define UTSR0_RID (1 << 2)
897#define UTSR0_RBB (1 << 3)
898#define UTSR0_REB (1 << 4)
899#define UTSR0_EIF (1 << 5)
900
901#define UTSR1_RNE (1 << 1)
902#define UTSR1_TNF (1 << 2)
903#define UTSR1_PRE (1 << 3)
904#define UTSR1_FRE (1 << 4)
905#define UTSR1_ROR (1 << 5)
906
907#define RX_FIFO_PRE (1 << 8)
908#define RX_FIFO_FRE (1 << 9)
909#define RX_FIFO_ROR (1 << 10)
910
911#define TYPE_STRONGARM_UART "strongarm-uart"
912#define STRONGARM_UART(obj) \
913 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
914
915typedef struct StrongARMUARTState {
916 SysBusDevice parent_obj;
917
918 MemoryRegion iomem;
919 CharBackend chr;
920 qemu_irq irq;
921
922 uint8_t utcr0;
923 uint16_t brd;
924 uint8_t utcr3;
925 uint8_t utsr0;
926 uint8_t utsr1;
927
928 uint8_t tx_fifo[8];
929 uint8_t tx_start;
930 uint8_t tx_len;
931 uint16_t rx_fifo[12];
932 uint8_t rx_start;
933 uint8_t rx_len;
934
935 uint64_t char_transmit_time;
936 bool wait_break_end;
937 QEMUTimer *rx_timeout_timer;
938 QEMUTimer *tx_timer;
939} StrongARMUARTState;
940
941static void strongarm_uart_update_status(StrongARMUARTState *s)
942{
943 uint16_t utsr1 = 0;
944
945 if (s->tx_len != 8) {
946 utsr1 |= UTSR1_TNF;
947 }
948
949 if (s->rx_len != 0) {
950 uint16_t ent = s->rx_fifo[s->rx_start];
951
952 utsr1 |= UTSR1_RNE;
953 if (ent & RX_FIFO_PRE) {
954 s->utsr1 |= UTSR1_PRE;
955 }
956 if (ent & RX_FIFO_FRE) {
957 s->utsr1 |= UTSR1_FRE;
958 }
959 if (ent & RX_FIFO_ROR) {
960 s->utsr1 |= UTSR1_ROR;
961 }
962 }
963
964 s->utsr1 = utsr1;
965}
966
967static void strongarm_uart_update_int_status(StrongARMUARTState *s)
968{
969 uint16_t utsr0 = s->utsr0 &
970 (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
971 int i;
972
973 if ((s->utcr3 & UTCR3_TXE) &&
974 (s->utcr3 & UTCR3_TIE) &&
975 s->tx_len <= 4) {
976 utsr0 |= UTSR0_TFS;
977 }
978
979 if ((s->utcr3 & UTCR3_RXE) &&
980 (s->utcr3 & UTCR3_RIE) &&
981 s->rx_len > 4) {
982 utsr0 |= UTSR0_RFS;
983 }
984
985 for (i = 0; i < s->rx_len && i < 4; i++)
986 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
987 utsr0 |= UTSR0_EIF;
988 break;
989 }
990
991 s->utsr0 = utsr0;
992 qemu_set_irq(s->irq, utsr0);
993}
994
995static void strongarm_uart_update_parameters(StrongARMUARTState *s)
996{
997 int speed, parity, data_bits, stop_bits, frame_size;
998 QEMUSerialSetParams ssp;
999
1000
1001 frame_size = 1;
1002 if (s->utcr0 & UTCR0_PE) {
1003
1004 frame_size++;
1005 if (s->utcr0 & UTCR0_OES) {
1006 parity = 'E';
1007 } else {
1008 parity = 'O';
1009 }
1010 } else {
1011 parity = 'N';
1012 }
1013 if (s->utcr0 & UTCR0_SBS) {
1014 stop_bits = 2;
1015 } else {
1016 stop_bits = 1;
1017 }
1018
1019 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
1020 frame_size += data_bits + stop_bits;
1021 speed = 3686400 / 16 / (s->brd + 1);
1022 ssp.speed = speed;
1023 ssp.parity = parity;
1024 ssp.data_bits = data_bits;
1025 ssp.stop_bits = stop_bits;
1026 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size;
1027 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1028
1029 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1030 speed, parity, data_bits, stop_bits);
1031}
1032
1033static void strongarm_uart_rx_to(void *opaque)
1034{
1035 StrongARMUARTState *s = opaque;
1036
1037 if (s->rx_len) {
1038 s->utsr0 |= UTSR0_RID;
1039 strongarm_uart_update_int_status(s);
1040 }
1041}
1042
1043static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1044{
1045 if ((s->utcr3 & UTCR3_RXE) == 0) {
1046
1047 return;
1048 }
1049
1050 if (s->wait_break_end) {
1051 s->utsr0 |= UTSR0_REB;
1052 s->wait_break_end = false;
1053 }
1054
1055 if (s->rx_len < 12) {
1056 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1057 s->rx_len++;
1058 } else
1059 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1060}
1061
1062static int strongarm_uart_can_receive(void *opaque)
1063{
1064 StrongARMUARTState *s = opaque;
1065
1066 if (s->rx_len == 12) {
1067 return 0;
1068 }
1069
1070 if (s->rx_len < 8) {
1071 return 8 - s->rx_len;
1072 }
1073 return 1;
1074}
1075
1076static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1077{
1078 StrongARMUARTState *s = opaque;
1079 int i;
1080
1081 for (i = 0; i < size; i++) {
1082 strongarm_uart_rx_push(s, buf[i]);
1083 }
1084
1085
1086 timer_mod(s->rx_timeout_timer,
1087 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1088
1089 strongarm_uart_update_status(s);
1090 strongarm_uart_update_int_status(s);
1091}
1092
1093static void strongarm_uart_event(void *opaque, int event)
1094{
1095 StrongARMUARTState *s = opaque;
1096 if (event == CHR_EVENT_BREAK) {
1097 s->utsr0 |= UTSR0_RBB;
1098 strongarm_uart_rx_push(s, RX_FIFO_FRE);
1099 s->wait_break_end = true;
1100 strongarm_uart_update_status(s);
1101 strongarm_uart_update_int_status(s);
1102 }
1103}
1104
1105static void strongarm_uart_tx(void *opaque)
1106{
1107 StrongARMUARTState *s = opaque;
1108 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1109
1110 if (s->utcr3 & UTCR3_LBM) {
1111 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1112 } else if (qemu_chr_fe_backend_connected(&s->chr)) {
1113
1114
1115 qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1);
1116 }
1117
1118 s->tx_start = (s->tx_start + 1) % 8;
1119 s->tx_len--;
1120 if (s->tx_len) {
1121 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1122 }
1123 strongarm_uart_update_status(s);
1124 strongarm_uart_update_int_status(s);
1125}
1126
1127static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
1128 unsigned size)
1129{
1130 StrongARMUARTState *s = opaque;
1131 uint16_t ret;
1132
1133 switch (addr) {
1134 case UTCR0:
1135 return s->utcr0;
1136
1137 case UTCR1:
1138 return s->brd >> 8;
1139
1140 case UTCR2:
1141 return s->brd & 0xff;
1142
1143 case UTCR3:
1144 return s->utcr3;
1145
1146 case UTDR:
1147 if (s->rx_len != 0) {
1148 ret = s->rx_fifo[s->rx_start];
1149 s->rx_start = (s->rx_start + 1) % 12;
1150 s->rx_len--;
1151 strongarm_uart_update_status(s);
1152 strongarm_uart_update_int_status(s);
1153 return ret;
1154 }
1155 return 0;
1156
1157 case UTSR0:
1158 return s->utsr0;
1159
1160 case UTSR1:
1161 return s->utsr1;
1162
1163 default:
1164 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1165 return 0;
1166 }
1167}
1168
1169static void strongarm_uart_write(void *opaque, hwaddr addr,
1170 uint64_t value, unsigned size)
1171{
1172 StrongARMUARTState *s = opaque;
1173
1174 switch (addr) {
1175 case UTCR0:
1176 s->utcr0 = value & 0x7f;
1177 strongarm_uart_update_parameters(s);
1178 break;
1179
1180 case UTCR1:
1181 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1182 strongarm_uart_update_parameters(s);
1183 break;
1184
1185 case UTCR2:
1186 s->brd = (s->brd & 0xf00) | (value & 0xff);
1187 strongarm_uart_update_parameters(s);
1188 break;
1189
1190 case UTCR3:
1191 s->utcr3 = value & 0x3f;
1192 if ((s->utcr3 & UTCR3_RXE) == 0) {
1193 s->rx_len = 0;
1194 }
1195 if ((s->utcr3 & UTCR3_TXE) == 0) {
1196 s->tx_len = 0;
1197 }
1198 strongarm_uart_update_status(s);
1199 strongarm_uart_update_int_status(s);
1200 break;
1201
1202 case UTDR:
1203 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1204 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1205 s->tx_len++;
1206 strongarm_uart_update_status(s);
1207 strongarm_uart_update_int_status(s);
1208 if (s->tx_len == 1) {
1209 strongarm_uart_tx(s);
1210 }
1211 }
1212 break;
1213
1214 case UTSR0:
1215 s->utsr0 = s->utsr0 & ~(value &
1216 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1217 strongarm_uart_update_int_status(s);
1218 break;
1219
1220 default:
1221 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1222 }
1223}
1224
1225static const MemoryRegionOps strongarm_uart_ops = {
1226 .read = strongarm_uart_read,
1227 .write = strongarm_uart_write,
1228 .endianness = DEVICE_NATIVE_ENDIAN,
1229};
1230
1231static void strongarm_uart_init(Object *obj)
1232{
1233 StrongARMUARTState *s = STRONGARM_UART(obj);
1234 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1235
1236 memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s,
1237 "uart", 0x10000);
1238 sysbus_init_mmio(dev, &s->iomem);
1239 sysbus_init_irq(dev, &s->irq);
1240
1241 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);
1242 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
1243}
1244
1245static void strongarm_uart_realize(DeviceState *dev, Error **errp)
1246{
1247 StrongARMUARTState *s = STRONGARM_UART(dev);
1248
1249 qemu_chr_fe_set_handlers(&s->chr,
1250 strongarm_uart_can_receive,
1251 strongarm_uart_receive,
1252 strongarm_uart_event,
1253 NULL, s, NULL, true);
1254}
1255
1256static void strongarm_uart_reset(DeviceState *dev)
1257{
1258 StrongARMUARTState *s = STRONGARM_UART(dev);
1259
1260 s->utcr0 = UTCR0_DSS;
1261 s->brd = 23;
1262
1263 s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1264
1265 s->rx_len = s->tx_len = 0;
1266
1267 strongarm_uart_update_parameters(s);
1268 strongarm_uart_update_status(s);
1269 strongarm_uart_update_int_status(s);
1270}
1271
1272static int strongarm_uart_post_load(void *opaque, int version_id)
1273{
1274 StrongARMUARTState *s = opaque;
1275
1276 strongarm_uart_update_parameters(s);
1277 strongarm_uart_update_status(s);
1278 strongarm_uart_update_int_status(s);
1279
1280
1281 if (s->tx_len) {
1282 strongarm_uart_tx(s);
1283 }
1284
1285
1286 if (s->rx_len) {
1287 timer_mod(s->rx_timeout_timer,
1288 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1289 }
1290
1291 return 0;
1292}
1293
1294static const VMStateDescription vmstate_strongarm_uart_regs = {
1295 .name = "strongarm-uart",
1296 .version_id = 0,
1297 .minimum_version_id = 0,
1298 .post_load = strongarm_uart_post_load,
1299 .fields = (VMStateField[]) {
1300 VMSTATE_UINT8(utcr0, StrongARMUARTState),
1301 VMSTATE_UINT16(brd, StrongARMUARTState),
1302 VMSTATE_UINT8(utcr3, StrongARMUARTState),
1303 VMSTATE_UINT8(utsr0, StrongARMUARTState),
1304 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1305 VMSTATE_UINT8(tx_start, StrongARMUARTState),
1306 VMSTATE_UINT8(tx_len, StrongARMUARTState),
1307 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1308 VMSTATE_UINT8(rx_start, StrongARMUARTState),
1309 VMSTATE_UINT8(rx_len, StrongARMUARTState),
1310 VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1311 VMSTATE_END_OF_LIST(),
1312 },
1313};
1314
1315static Property strongarm_uart_properties[] = {
1316 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1317 DEFINE_PROP_END_OF_LIST(),
1318};
1319
1320static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1321{
1322 DeviceClass *dc = DEVICE_CLASS(klass);
1323
1324 dc->desc = "StrongARM UART controller";
1325 dc->reset = strongarm_uart_reset;
1326 dc->vmsd = &vmstate_strongarm_uart_regs;
1327 dc->props = strongarm_uart_properties;
1328 dc->realize = strongarm_uart_realize;
1329}
1330
1331static const TypeInfo strongarm_uart_info = {
1332 .name = TYPE_STRONGARM_UART,
1333 .parent = TYPE_SYS_BUS_DEVICE,
1334 .instance_size = sizeof(StrongARMUARTState),
1335 .instance_init = strongarm_uart_init,
1336 .class_init = strongarm_uart_class_init,
1337};
1338
1339
1340
1341#define TYPE_STRONGARM_SSP "strongarm-ssp"
1342#define STRONGARM_SSP(obj) \
1343 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1344
1345typedef struct StrongARMSSPState {
1346 SysBusDevice parent_obj;
1347
1348 MemoryRegion iomem;
1349 qemu_irq irq;
1350 SSIBus *bus;
1351
1352 uint16_t sscr[2];
1353 uint16_t sssr;
1354
1355 uint16_t rx_fifo[8];
1356 uint8_t rx_level;
1357 uint8_t rx_start;
1358} StrongARMSSPState;
1359
1360#define SSCR0 0x60
1361#define SSCR1 0x64
1362#define SSDR 0x6c
1363#define SSSR 0x74
1364
1365
1366#define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1367#define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1368#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1369#define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1370#define SSCR0_SSE (1 << 7)
1371#define SSCR0_DSS(x) (((x) & 0xf) + 1)
1372#define SSCR1_RIE (1 << 0)
1373#define SSCR1_TIE (1 << 1)
1374#define SSCR1_LBM (1 << 2)
1375#define SSSR_TNF (1 << 2)
1376#define SSSR_RNE (1 << 3)
1377#define SSSR_TFS (1 << 5)
1378#define SSSR_RFS (1 << 6)
1379#define SSSR_ROR (1 << 7)
1380#define SSSR_RW 0x0080
1381
1382static void strongarm_ssp_int_update(StrongARMSSPState *s)
1383{
1384 int level = 0;
1385
1386 level |= (s->sssr & SSSR_ROR);
1387 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
1388 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
1389 qemu_set_irq(s->irq, level);
1390}
1391
1392static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1393{
1394 s->sssr &= ~SSSR_TFS;
1395 s->sssr &= ~SSSR_TNF;
1396 if (s->sscr[0] & SSCR0_SSE) {
1397 if (s->rx_level >= 4) {
1398 s->sssr |= SSSR_RFS;
1399 } else {
1400 s->sssr &= ~SSSR_RFS;
1401 }
1402 if (s->rx_level) {
1403 s->sssr |= SSSR_RNE;
1404 } else {
1405 s->sssr &= ~SSSR_RNE;
1406 }
1407
1408
1409 s->sssr |= SSSR_TFS;
1410 s->sssr |= SSSR_TNF;
1411 }
1412
1413 strongarm_ssp_int_update(s);
1414}
1415
1416static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
1417 unsigned size)
1418{
1419 StrongARMSSPState *s = opaque;
1420 uint32_t retval;
1421
1422 switch (addr) {
1423 case SSCR0:
1424 return s->sscr[0];
1425 case SSCR1:
1426 return s->sscr[1];
1427 case SSSR:
1428 return s->sssr;
1429 case SSDR:
1430 if (~s->sscr[0] & SSCR0_SSE) {
1431 return 0xffffffff;
1432 }
1433 if (s->rx_level < 1) {
1434 printf("%s: SSP Rx Underrun\n", __func__);
1435 return 0xffffffff;
1436 }
1437 s->rx_level--;
1438 retval = s->rx_fifo[s->rx_start++];
1439 s->rx_start &= 0x7;
1440 strongarm_ssp_fifo_update(s);
1441 return retval;
1442 default:
1443 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1444 break;
1445 }
1446 return 0;
1447}
1448
1449static void strongarm_ssp_write(void *opaque, hwaddr addr,
1450 uint64_t value, unsigned size)
1451{
1452 StrongARMSSPState *s = opaque;
1453
1454 switch (addr) {
1455 case SSCR0:
1456 s->sscr[0] = value & 0xffbf;
1457 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1458 printf("%s: Wrong data size: %i bits\n", __func__,
1459 (int)SSCR0_DSS(value));
1460 }
1461 if (!(value & SSCR0_SSE)) {
1462 s->sssr = 0;
1463 s->rx_level = 0;
1464 }
1465 strongarm_ssp_fifo_update(s);
1466 break;
1467
1468 case SSCR1:
1469 s->sscr[1] = value & 0x2f;
1470 if (value & SSCR1_LBM) {
1471 printf("%s: Attempt to use SSP LBM mode\n", __func__);
1472 }
1473 strongarm_ssp_fifo_update(s);
1474 break;
1475
1476 case SSSR:
1477 s->sssr &= ~(value & SSSR_RW);
1478 strongarm_ssp_int_update(s);
1479 break;
1480
1481 case SSDR:
1482 if (SSCR0_UWIRE(s->sscr[0])) {
1483 value &= 0xff;
1484 } else
1485
1486 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1487
1488
1489
1490
1491 if (s->sscr[0] & SSCR0_SSE) {
1492 uint32_t readval;
1493 if (s->sscr[1] & SSCR1_LBM) {
1494 readval = value;
1495 } else {
1496 readval = ssi_transfer(s->bus, value);
1497 }
1498
1499 if (s->rx_level < 0x08) {
1500 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1501 } else {
1502 s->sssr |= SSSR_ROR;
1503 }
1504 }
1505 strongarm_ssp_fifo_update(s);
1506 break;
1507
1508 default:
1509 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1510 break;
1511 }
1512}
1513
1514static const MemoryRegionOps strongarm_ssp_ops = {
1515 .read = strongarm_ssp_read,
1516 .write = strongarm_ssp_write,
1517 .endianness = DEVICE_NATIVE_ENDIAN,
1518};
1519
1520static int strongarm_ssp_post_load(void *opaque, int version_id)
1521{
1522 StrongARMSSPState *s = opaque;
1523
1524 strongarm_ssp_fifo_update(s);
1525
1526 return 0;
1527}
1528
1529static void strongarm_ssp_init(Object *obj)
1530{
1531 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1532 DeviceState *dev = DEVICE(sbd);
1533 StrongARMSSPState *s = STRONGARM_SSP(dev);
1534
1535 sysbus_init_irq(sbd, &s->irq);
1536
1537 memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s,
1538 "ssp", 0x1000);
1539 sysbus_init_mmio(sbd, &s->iomem);
1540
1541 s->bus = ssi_create_bus(dev, "ssi");
1542}
1543
1544static void strongarm_ssp_reset(DeviceState *dev)
1545{
1546 StrongARMSSPState *s = STRONGARM_SSP(dev);
1547
1548 s->sssr = 0x03;
1549 s->rx_start = 0;
1550 s->rx_level = 0;
1551}
1552
1553static const VMStateDescription vmstate_strongarm_ssp_regs = {
1554 .name = "strongarm-ssp",
1555 .version_id = 0,
1556 .minimum_version_id = 0,
1557 .post_load = strongarm_ssp_post_load,
1558 .fields = (VMStateField[]) {
1559 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1560 VMSTATE_UINT16(sssr, StrongARMSSPState),
1561 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1562 VMSTATE_UINT8(rx_start, StrongARMSSPState),
1563 VMSTATE_UINT8(rx_level, StrongARMSSPState),
1564 VMSTATE_END_OF_LIST(),
1565 },
1566};
1567
1568static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1569{
1570 DeviceClass *dc = DEVICE_CLASS(klass);
1571
1572 dc->desc = "StrongARM SSP controller";
1573 dc->reset = strongarm_ssp_reset;
1574 dc->vmsd = &vmstate_strongarm_ssp_regs;
1575}
1576
1577static const TypeInfo strongarm_ssp_info = {
1578 .name = TYPE_STRONGARM_SSP,
1579 .parent = TYPE_SYS_BUS_DEVICE,
1580 .instance_size = sizeof(StrongARMSSPState),
1581 .instance_init = strongarm_ssp_init,
1582 .class_init = strongarm_ssp_class_init,
1583};
1584
1585
1586StrongARMState *sa1110_init(MemoryRegion *sysmem,
1587 unsigned int sdram_size, const char *cpu_type)
1588{
1589 StrongARMState *s;
1590 int i;
1591
1592 s = g_new0(StrongARMState, 1);
1593
1594 if (strncmp(cpu_type, "sa1110", 6)) {
1595 error_report("Machine requires a SA1110 processor.");
1596 exit(1);
1597 }
1598
1599 s->cpu = ARM_CPU(cpu_create(cpu_type));
1600
1601 memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
1602 sdram_size);
1603 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1604
1605 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1606 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ),
1607 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ),
1608 NULL);
1609
1610 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1611 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1612 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1613 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1614 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1615 NULL);
1616
1617 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000,
1618 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1619
1620 s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1621
1622 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
1623
1624 for (i = 0; sa_serial[i].io_base; i++) {
1625 DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
1626 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
1627 qdev_init_nofail(dev);
1628 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
1629 sa_serial[i].io_base);
1630 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
1631 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1632 }
1633
1634 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000,
1635 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1636 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1637
1638 return s;
1639}
1640
1641static void strongarm_register_types(void)
1642{
1643 type_register_static(&strongarm_pic_info);
1644 type_register_static(&strongarm_rtc_sysbus_info);
1645 type_register_static(&strongarm_gpio_info);
1646 type_register_static(&strongarm_ppc_info);
1647 type_register_static(&strongarm_uart_info);
1648 type_register_static(&strongarm_ssp_info);
1649}
1650
1651type_init(strongarm_register_types)
1652
