1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include "qemu/osdep.h"
19#include "qapi/error.h"
20#include "cpu.h"
21#include "hw/sysbus.h"
22#include "hw/arm/boot.h"
23#include "net/net.h"
24#include "exec/address-spaces.h"
25#include "sysemu/sysemu.h"
26#include "hw/boards.h"
27#include "hw/block/flash.h"
28#include "hw/loader.h"
29#include "hw/misc/zynq-xadc.h"
30#include "hw/ssi/ssi.h"
31#include "qemu/error-report.h"
32#include "hw/sd/sdhci.h"
33#include "hw/char/cadence_uart.h"
34#include "hw/net/cadence_gem.h"
35#include "hw/cpu/a9mpcore.h"
36
37#define NUM_SPI_FLASHES 4
38#define NUM_QSPI_FLASHES 2
39#define NUM_QSPI_BUSSES 2
40
41#define FLASH_SIZE (64 * 1024 * 1024)
42#define FLASH_SECTOR_SIZE (128 * 1024)
43
44#define IRQ_OFFSET 32
45
46#define MPCORE_PERIPHBASE 0xF8F00000
47#define ZYNQ_BOARD_MIDR 0x413FC090
48
49static const int dma_irqs[8] = {
50 46, 47, 48, 49, 72, 73, 74, 75
51};
52
53#define BOARD_SETUP_ADDR 0x100
54
55#define SLCR_LOCK_OFFSET 0x004
56#define SLCR_UNLOCK_OFFSET 0x008
57#define SLCR_ARM_PLL_OFFSET 0x100
58
59#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
60#define SLCR_XILINX_LOCK_KEY 0x767b
61
62#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080
63
64#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
65 extract32((x), 12, 4) << 16)
66
67
68
69
70
71#define SLCR_WRITE(addr, val) \
72 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), \
73 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), \
74 0xe5801000 + (addr)
75
76static void zynq_write_board_setup(ARMCPU *cpu,
77 const struct arm_boot_info *info)
78{
79 int n;
80 uint32_t board_setup_blob[] = {
81 0xe3a004f8,
82 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
83 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
84 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
85 0xe12fff1e,
86 };
87 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
88 board_setup_blob[n] = tswap32(board_setup_blob[n]);
89 }
90 rom_add_blob_fixed("board-setup", board_setup_blob,
91 sizeof(board_setup_blob), BOARD_SETUP_ADDR);
92}
93
94static struct arm_boot_info zynq_binfo = {};
95
96static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
97{
98 DeviceState *dev;
99 SysBusDevice *s;
100
101 dev = qdev_create(NULL, TYPE_CADENCE_GEM);
102 if (nd->used) {
103 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
104 qdev_set_nic_properties(dev, nd);
105 }
106 qdev_init_nofail(dev);
107 s = SYS_BUS_DEVICE(dev);
108 sysbus_mmio_map(s, 0, base);
109 sysbus_connect_irq(s, 0, irq);
110}
111
112static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
113 bool is_qspi)
114{
115 DeviceState *dev;
116 SysBusDevice *busdev;
117 SSIBus *spi;
118 DeviceState *flash_dev;
119 int i, j;
120 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
121 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
122
123 dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
124 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
125 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
126 qdev_prop_set_uint8(dev, "num-busses", num_busses);
127 qdev_init_nofail(dev);
128 busdev = SYS_BUS_DEVICE(dev);
129 sysbus_mmio_map(busdev, 0, base_addr);
130 if (is_qspi) {
131 sysbus_mmio_map(busdev, 1, 0xFC000000);
132 }
133 sysbus_connect_irq(busdev, 0, irq);
134
135 for (i = 0; i < num_busses; ++i) {
136 char bus_name[16];
137 qemu_irq cs_line;
138
139 snprintf(bus_name, 16, "spi%d", i);
140 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
141
142 for (j = 0; j < num_ss; ++j) {
143 DriveInfo *dinfo = drive_get_next(IF_MTD);
144 flash_dev = ssi_create_slave_no_init(spi, "n25q128");
145 if (dinfo) {
146 qdev_prop_set_drive(flash_dev, "drive",
147 blk_by_legacy_dinfo(dinfo), &error_fatal);
148 }
149 qdev_init_nofail(flash_dev);
150
151 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
152 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
153 }
154 }
155
156}
157
158static void zynq_init(MachineState *machine)
159{
160 ram_addr_t ram_size = machine->ram_size;
161 const char *kernel_filename = machine->kernel_filename;
162 const char *kernel_cmdline = machine->kernel_cmdline;
163 const char *initrd_filename = machine->initrd_filename;
164 ARMCPU *cpu;
165 MemoryRegion *address_space_mem = get_system_memory();
166 MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
167 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
168 DeviceState *dev;
169 SysBusDevice *busdev;
170 qemu_irq pic[64];
171 int n;
172
173 cpu = ARM_CPU(object_new(machine->cpu_type));
174
175
176
177
178
179 if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
180 object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
181 }
182
183 object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
184 &error_fatal);
185 object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
186 &error_fatal);
187 object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
188
189
190 if (ram_size > 0x80000000) {
191 ram_size = 0x80000000;
192 }
193
194
195 memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
196 ram_size);
197 memory_region_add_subregion(address_space_mem, 0, ext_ram);
198
199
200 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
201 &error_fatal);
202 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
203
204 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
205
206
207 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
208 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
209 FLASH_SECTOR_SIZE, 1,
210 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
211 0);
212
213 dev = qdev_create(NULL, "xilinx,zynq_slcr");
214 qdev_init_nofail(dev);
215 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
216
217 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
218 qdev_prop_set_uint32(dev, "num-cpu", 1);
219 qdev_init_nofail(dev);
220 busdev = SYS_BUS_DEVICE(dev);
221 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
222 sysbus_connect_irq(busdev, 0,
223 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
224
225 for (n = 0; n < 64; n++) {
226 pic[n] = qdev_get_gpio_in(dev, n);
227 }
228
229 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
230 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
231 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
232
233 sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
234 sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
235
236 cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
237 cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
238
239 sysbus_create_varargs("cadence_ttc", 0xF8001000,
240 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
241 sysbus_create_varargs("cadence_ttc", 0xF8002000,
242 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
243
244 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
245 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
246
247 for (n = 0; n < 2; n++) {
248 int hci_irq = n ? 79 : 56;
249 hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
250 DriveInfo *di;
251 BlockBackend *blk;
252 DeviceState *carddev;
253
254
255
256
257
258
259 dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
260 qdev_prop_set_uint8(dev, "sd-spec-version", 2);
261 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
262 qdev_init_nofail(dev);
263 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
264 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
265
266 di = drive_get_next(IF_SD);
267 blk = di ? blk_by_legacy_dinfo(di) : NULL;
268 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
269 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
270 object_property_set_bool(OBJECT(carddev), true, "realized",
271 &error_fatal);
272 }
273
274 dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
275 qdev_init_nofail(dev);
276 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
277 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
278
279 dev = qdev_create(NULL, "pl330");
280 qdev_prop_set_uint8(dev, "num_chnls", 8);
281 qdev_prop_set_uint8(dev, "num_periph_req", 4);
282 qdev_prop_set_uint8(dev, "num_events", 16);
283
284 qdev_prop_set_uint8(dev, "data_width", 64);
285 qdev_prop_set_uint8(dev, "wr_cap", 8);
286 qdev_prop_set_uint8(dev, "wr_q_dep", 16);
287 qdev_prop_set_uint8(dev, "rd_cap", 8);
288 qdev_prop_set_uint8(dev, "rd_q_dep", 16);
289 qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
290
291 qdev_init_nofail(dev);
292 busdev = SYS_BUS_DEVICE(dev);
293 sysbus_mmio_map(busdev, 0, 0xF8003000);
294 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]);
295 for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) {
296 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
297 }
298
299 dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
300 qdev_init_nofail(dev);
301 busdev = SYS_BUS_DEVICE(dev);
302 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
303 sysbus_mmio_map(busdev, 0, 0xF8007000);
304
305 zynq_binfo.ram_size = ram_size;
306 zynq_binfo.kernel_filename = kernel_filename;
307 zynq_binfo.kernel_cmdline = kernel_cmdline;
308 zynq_binfo.initrd_filename = initrd_filename;
309 zynq_binfo.nb_cpus = 1;
310 zynq_binfo.board_id = 0xd32;
311 zynq_binfo.loader_start = 0;
312 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
313 zynq_binfo.write_board_setup = zynq_write_board_setup;
314
315 arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
316}
317
318static void zynq_machine_init(MachineClass *mc)
319{
320 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
321 mc->init = zynq_init;
322 mc->max_cpus = 1;
323 mc->no_sdcard = 1;
324 mc->ignore_memory_transaction_failures = true;
325 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
326}
327
328DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
329
