LXR qemu/hw/audio/cs4231.c

   1/*
   2 * QEMU Crystal CS4231 audio chip emulation
   3 *
   4 * Copyright (c) 2006 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "hw/sysbus.h"
  27#include "qemu/module.h"
  28#include "trace.h"
  29
  30/*
  31 * In addition to Crystal CS4231 there is a DMA controller on Sparc.
  32 */
  33#define CS_SIZE 0x40
  34#define CS_REGS 16
  35#define CS_DREGS 32
  36#define CS_MAXDREG (CS_DREGS - 1)
  37
  38#define TYPE_CS4231 "SUNW,CS4231"
  39#define CS4231(obj) \
  40    OBJECT_CHECK(CSState, (obj), TYPE_CS4231)
  41
  42typedef struct CSState {
  43    SysBusDevice parent_obj;
  44
  45    MemoryRegion iomem;
  46    qemu_irq irq;
  47    uint32_t regs[CS_REGS];
  48    uint8_t dregs[CS_DREGS];
  49} CSState;
  50
  51#define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
  52#define CS_VER 0xa0
  53#define CS_CDC_VER 0x8a
  54
  55static void cs_reset(DeviceState *d)
  56{
  57    CSState *s = CS4231(d);
  58
  59    memset(s->regs, 0, CS_REGS * 4);
  60    memset(s->dregs, 0, CS_DREGS);
  61    s->dregs[12] = CS_CDC_VER;
  62    s->dregs[25] = CS_VER;
  63}
  64
  65static uint64_t cs_mem_read(void *opaque, hwaddr addr,
  66                            unsigned size)
  67{
  68    CSState *s = opaque;
  69    uint32_t saddr, ret;
  70
  71    saddr = addr >> 2;
  72    switch (saddr) {
  73    case 1:
  74        switch (CS_RAP(s)) {
  75        case 3: // Write only
  76            ret = 0;
  77            break;
  78        default:
  79            ret = s->dregs[CS_RAP(s)];
  80            break;
  81        }
  82        trace_cs4231_mem_readl_dreg(CS_RAP(s), ret);
  83        break;
  84    default:
  85        ret = s->regs[saddr];
  86        trace_cs4231_mem_readl_reg(saddr, ret);
  87        break;
  88    }
  89    return ret;
  90}
  91
  92static void cs_mem_write(void *opaque, hwaddr addr,
  93                         uint64_t val, unsigned size)
  94{
  95    CSState *s = opaque;
  96    uint32_t saddr;
  97
  98    saddr = addr >> 2;
  99    trace_cs4231_mem_writel_reg(saddr, s->regs[saddr], val);
 100    switch (saddr) {
 101    case 1:
 102        trace_cs4231_mem_writel_dreg(CS_RAP(s), s->dregs[CS_RAP(s)], val);
 103        switch(CS_RAP(s)) {
 104        case 11:
 105        case 25: // Read only
 106            break;
 107        case 12:
 108            val &= 0x40;
 109            val |= CS_CDC_VER; // Codec version
 110            s->dregs[CS_RAP(s)] = val;
 111            break;
 112        default:
 113            s->dregs[CS_RAP(s)] = val;
 114            break;
 115        }
 116        break;
 117    case 2: // Read only
 118        break;
 119    case 4:
 120        if (val & 1) {
 121            cs_reset(DEVICE(s));
 122        }
 123        val &= 0x7f;
 124        s->regs[saddr] = val;
 125        break;
 126    default:
 127        s->regs[saddr] = val;
 128        break;
 129    }
 130}
 131
 132static const MemoryRegionOps cs_mem_ops = {
 133    .read = cs_mem_read,
 134    .write = cs_mem_write,
 135    .endianness = DEVICE_NATIVE_ENDIAN,
 136};
 137
 138static const VMStateDescription vmstate_cs4231 = {
 139    .name ="cs4231",
 140    .version_id = 1,
 141    .minimum_version_id = 1,
 142    .fields = (VMStateField[]) {
 143        VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS),
 144        VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS),
 145        VMSTATE_END_OF_LIST()
 146    }
 147};
 148
 149static void cs4231_init(Object *obj)
 150{
 151    CSState *s = CS4231(obj);
 152    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 153
 154    memory_region_init_io(&s->iomem, obj, &cs_mem_ops, s, "cs4321",
 155                          CS_SIZE);
 156    sysbus_init_mmio(dev, &s->iomem);
 157    sysbus_init_irq(dev, &s->irq);
 158}
 159
 160static Property cs4231_properties[] = {
 161    {.name = NULL},
 162};
 163
 164static void cs4231_class_init(ObjectClass *klass, void *data)
 165{
 166    DeviceClass *dc = DEVICE_CLASS(klass);
 167
 168    dc->reset = cs_reset;
 169    dc->vmsd = &vmstate_cs4231;
 170    dc->props = cs4231_properties;
 171}
 172
 173static const TypeInfo cs4231_info = {
 174    .name          = TYPE_CS4231,
 175    .parent        = TYPE_SYS_BUS_DEVICE,
 176    .instance_size = sizeof(CSState),
 177    .instance_init = cs4231_init,
 178    .class_init    = cs4231_class_init,
 179};
 180
 181static void cs4231_register_types(void)
 182{
 183    type_register_static(&cs4231_info);
 184}
 185
 186type_init(cs4231_register_types)
 187