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39#include "qemu/osdep.h"
40#include "hw/hw.h"
41#include "hw/block/block.h"
42#include "hw/block/flash.h"
43#include "sysemu/block-backend.h"
44#include "qapi/error.h"
45#include "qemu/timer.h"
46#include "qemu/bitops.h"
47#include "qemu/error-report.h"
48#include "qemu/host-utils.h"
49#include "qemu/log.h"
50#include "qemu/module.h"
51#include "qemu/option.h"
52#include "hw/sysbus.h"
53#include "sysemu/blockdev.h"
54#include "sysemu/sysemu.h"
55#include "trace.h"
56
57
58#ifdef PFLASH_DEBUG
59#define DPRINTF(fmt, ...) \
60do { \
61 fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \
62} while (0)
63#else
64#define DPRINTF(fmt, ...) do { } while (0)
65#endif
66
67#define PFLASH_BE 0
68#define PFLASH_SECURE 1
69
70struct PFlashCFI01 {
71
72 SysBusDevice parent_obj;
73
74
75 BlockBackend *blk;
76 uint32_t nb_blocs;
77 uint64_t sector_len;
78 uint8_t bank_width;
79 uint8_t device_width;
80 uint8_t max_device_width;
81 uint32_t features;
82 uint8_t wcycle;
83 int ro;
84 uint8_t cmd;
85 uint8_t status;
86 uint16_t ident0;
87 uint16_t ident1;
88 uint16_t ident2;
89 uint16_t ident3;
90 uint8_t cfi_table[0x52];
91 uint64_t counter;
92 unsigned int writeblock_size;
93 QEMUTimer *timer;
94 MemoryRegion mem;
95 char *name;
96 void *storage;
97 VMChangeStateEntry *vmstate;
98 bool old_multiple_chip_handling;
99};
100
101static int pflash_post_load(void *opaque, int version_id);
102
103static const VMStateDescription vmstate_pflash = {
104 .name = "pflash_cfi01",
105 .version_id = 1,
106 .minimum_version_id = 1,
107 .post_load = pflash_post_load,
108 .fields = (VMStateField[]) {
109 VMSTATE_UINT8(wcycle, PFlashCFI01),
110 VMSTATE_UINT8(cmd, PFlashCFI01),
111 VMSTATE_UINT8(status, PFlashCFI01),
112 VMSTATE_UINT64(counter, PFlashCFI01),
113 VMSTATE_END_OF_LIST()
114 }
115};
116
117static void pflash_timer (void *opaque)
118{
119 PFlashCFI01 *pfl = opaque;
120
121 trace_pflash_timer_expired(pfl->cmd);
122
123 pfl->status ^= 0x80;
124 memory_region_rom_device_set_romd(&pfl->mem, true);
125 pfl->wcycle = 0;
126 pfl->cmd = 0;
127}
128
129
130
131
132
133static uint32_t pflash_cfi_query(PFlashCFI01 *pfl, hwaddr offset)
134{
135 int i;
136 uint32_t resp = 0;
137 hwaddr boff;
138
139
140
141
142
143
144
145
146
147
148
149 boff = offset >> (ctz32(pfl->bank_width) +
150 ctz32(pfl->max_device_width) - ctz32(pfl->device_width));
151
152 if (boff >= sizeof(pfl->cfi_table)) {
153 return 0;
154 }
155
156
157
158
159
160 resp = pfl->cfi_table[boff];
161 if (pfl->device_width != pfl->max_device_width) {
162
163
164
165 if (pfl->device_width != 1 || pfl->bank_width > 4) {
166 DPRINTF("%s: Unsupported device configuration: "
167 "device_width=%d, max_device_width=%d\n",
168 __func__, pfl->device_width,
169 pfl->max_device_width);
170 return 0;
171 }
172
173
174
175 for (i = 1; i < pfl->max_device_width; i++) {
176 resp = deposit32(resp, 8 * i, 8, pfl->cfi_table[boff]);
177 }
178 }
179
180 if (pfl->device_width < pfl->bank_width) {
181 for (i = pfl->device_width;
182 i < pfl->bank_width; i += pfl->device_width) {
183 resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp);
184 }
185 }
186
187 return resp;
188}
189
190
191
192
193static uint32_t pflash_devid_query(PFlashCFI01 *pfl, hwaddr offset)
194{
195 int i;
196 uint32_t resp;
197 hwaddr boff;
198
199
200
201
202
203
204
205
206
207
208
209 boff = offset >> (ctz32(pfl->bank_width) +
210 ctz32(pfl->max_device_width) - ctz32(pfl->device_width));
211
212
213
214
215
216 switch (boff & 0xFF) {
217 case 0:
218 resp = pfl->ident0;
219 trace_pflash_manufacturer_id(resp);
220 break;
221 case 1:
222 resp = pfl->ident1;
223 trace_pflash_device_id(resp);
224 break;
225 default:
226 trace_pflash_device_info(offset);
227 return 0;
228 break;
229 }
230
231 if (pfl->device_width < pfl->bank_width) {
232 for (i = pfl->device_width;
233 i < pfl->bank_width; i += pfl->device_width) {
234 resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp);
235 }
236 }
237
238 return resp;
239}
240
241static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwaddr offset,
242 int width, int be)
243{
244 uint8_t *p;
245 uint32_t ret;
246
247 p = pfl->storage;
248 switch (width) {
249 case 1:
250 ret = p[offset];
251 break;
252 case 2:
253 if (be) {
254 ret = p[offset] << 8;
255 ret |= p[offset + 1];
256 } else {
257 ret = p[offset];
258 ret |= p[offset + 1] << 8;
259 }
260 break;
261 case 4:
262 if (be) {
263 ret = p[offset] << 24;
264 ret |= p[offset + 1] << 16;
265 ret |= p[offset + 2] << 8;
266 ret |= p[offset + 3];
267 } else {
268 ret = p[offset];
269 ret |= p[offset + 1] << 8;
270 ret |= p[offset + 2] << 16;
271 ret |= p[offset + 3] << 24;
272 }
273 break;
274 default:
275 DPRINTF("BUG in %s\n", __func__);
276 abort();
277 }
278 trace_pflash_data_read(offset, width << 1, ret);
279 return ret;
280}
281
282static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
283 int width, int be)
284{
285 hwaddr boff;
286 uint32_t ret;
287
288 ret = -1;
289 switch (pfl->cmd) {
290 default:
291
292 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
293 pfl->wcycle = 0;
294 pfl->cmd = 0;
295
296 case 0x00:
297
298 ret = pflash_data_read(pfl, offset, width, be);
299 break;
300 case 0x10:
301 case 0x20:
302 case 0x28:
303 case 0x40:
304 case 0x50:
305 case 0x60:
306 case 0x70:
307 case 0xe8:
308
309
310
311 ret = pfl->status;
312 if (pfl->device_width && width > pfl->device_width) {
313 int shift = pfl->device_width * 8;
314 while (shift + pfl->device_width * 8 <= width * 8) {
315 ret |= pfl->status << shift;
316 shift += pfl->device_width * 8;
317 }
318 } else if (!pfl->device_width && width > 2) {
319
320
321
322 ret |= pfl->status << 16;
323 }
324 DPRINTF("%s: status %x\n", __func__, ret);
325 break;
326 case 0x90:
327 if (!pfl->device_width) {
328
329 boff = offset & 0xFF;
330 if (pfl->bank_width == 2) {
331 boff = boff >> 1;
332 } else if (pfl->bank_width == 4) {
333 boff = boff >> 2;
334 }
335
336 switch (boff) {
337 case 0:
338 ret = pfl->ident0 << 8 | pfl->ident1;
339 trace_pflash_manufacturer_id(ret);
340 break;
341 case 1:
342 ret = pfl->ident2 << 8 | pfl->ident3;
343 trace_pflash_device_id(ret);
344 break;
345 default:
346 trace_pflash_device_info(boff);
347 ret = 0;
348 break;
349 }
350 } else {
351
352
353
354 int i;
355 for (i = 0; i < width; i += pfl->bank_width) {
356 ret = deposit32(ret, i * 8, pfl->bank_width * 8,
357 pflash_devid_query(pfl,
358 offset + i * pfl->bank_width));
359 }
360 }
361 break;
362 case 0x98:
363 if (!pfl->device_width) {
364
365 boff = offset & 0xFF;
366 if (pfl->bank_width == 2) {
367 boff = boff >> 1;
368 } else if (pfl->bank_width == 4) {
369 boff = boff >> 2;
370 }
371
372 if (boff < sizeof(pfl->cfi_table)) {
373 ret = pfl->cfi_table[boff];
374 } else {
375 ret = 0;
376 }
377 } else {
378
379
380
381 int i;
382 for (i = 0; i < width; i += pfl->bank_width) {
383 ret = deposit32(ret, i * 8, pfl->bank_width * 8,
384 pflash_cfi_query(pfl,
385 offset + i * pfl->bank_width));
386 }
387 }
388
389 break;
390 }
391 trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle);
392
393 return ret;
394}
395
396
397static void pflash_update(PFlashCFI01 *pfl, int offset,
398 int size)
399{
400 int offset_end;
401 if (pfl->blk) {
402 offset_end = offset + size;
403
404 offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
405 offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
406 blk_pwrite(pfl->blk, offset, pfl->storage + offset,
407 offset_end - offset, 0);
408 }
409}
410
411static inline void pflash_data_write(PFlashCFI01 *pfl, hwaddr offset,
412 uint32_t value, int width, int be)
413{
414 uint8_t *p = pfl->storage;
415
416 trace_pflash_data_write(offset, width << 1, value, pfl->counter);
417 switch (width) {
418 case 1:
419 p[offset] = value;
420 break;
421 case 2:
422 if (be) {
423 p[offset] = value >> 8;
424 p[offset + 1] = value;
425 } else {
426 p[offset] = value;
427 p[offset + 1] = value >> 8;
428 }
429 break;
430 case 4:
431 if (be) {
432 p[offset] = value >> 24;
433 p[offset + 1] = value >> 16;
434 p[offset + 2] = value >> 8;
435 p[offset + 3] = value;
436 } else {
437 p[offset] = value;
438 p[offset + 1] = value >> 8;
439 p[offset + 2] = value >> 16;
440 p[offset + 3] = value >> 24;
441 }
442 break;
443 }
444
445}
446
447static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
448 uint32_t value, int width, int be)
449{
450 uint8_t *p;
451 uint8_t cmd;
452
453 cmd = value;
454
455 trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle);
456 if (!pfl->wcycle) {
457
458 memory_region_rom_device_set_romd(&pfl->mem, false);
459 }
460
461 switch (pfl->wcycle) {
462 case 0:
463
464 switch (cmd) {
465 case 0x00:
466 goto reset_flash;
467 case 0x10:
468 case 0x40:
469 DPRINTF("%s: Single Byte Program\n", __func__);
470 break;
471 case 0x20:
472 p = pfl->storage;
473 offset &= ~(pfl->sector_len - 1);
474
475 DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n",
476 __func__, offset, (unsigned)pfl->sector_len);
477
478 if (!pfl->ro) {
479 memset(p + offset, 0xff, pfl->sector_len);
480 pflash_update(pfl, offset, pfl->sector_len);
481 } else {
482 pfl->status |= 0x20;
483 }
484 pfl->status |= 0x80;
485 break;
486 case 0x50:
487 DPRINTF("%s: Clear status bits\n", __func__);
488 pfl->status = 0x0;
489 goto reset_flash;
490 case 0x60:
491 DPRINTF("%s: Block unlock\n", __func__);
492 break;
493 case 0x70:
494 DPRINTF("%s: Read status register\n", __func__);
495 pfl->cmd = cmd;
496 return;
497 case 0x90:
498 DPRINTF("%s: Read Device information\n", __func__);
499 pfl->cmd = cmd;
500 return;
501 case 0x98:
502 DPRINTF("%s: CFI query\n", __func__);
503 break;
504 case 0xe8:
505 DPRINTF("%s: Write to buffer\n", __func__);
506
507 qemu_log_mask(LOG_UNIMP,
508 "%s: Write to buffer emulation is flawed\n",
509 __func__);
510 pfl->status |= 0x80;
511 break;
512 case 0xf0:
513 DPRINTF("%s: Probe for AMD flash\n", __func__);
514 goto reset_flash;
515 case 0xff:
516 DPRINTF("%s: Read array mode\n", __func__);
517 goto reset_flash;
518 default:
519 goto error_flash;
520 }
521 pfl->wcycle++;
522 pfl->cmd = cmd;
523 break;
524 case 1:
525 switch (pfl->cmd) {
526 case 0x10:
527 case 0x40:
528 DPRINTF("%s: Single Byte Program\n", __func__);
529 if (!pfl->ro) {
530 pflash_data_write(pfl, offset, value, width, be);
531 pflash_update(pfl, offset, width);
532 } else {
533 pfl->status |= 0x10;
534 }
535 pfl->status |= 0x80;
536 pfl->wcycle = 0;
537 break;
538 case 0x20:
539 case 0x28:
540 if (cmd == 0xd0) {
541 pfl->wcycle = 0;
542 pfl->status |= 0x80;
543 } else if (cmd == 0xff) {
544 goto reset_flash;
545 } else
546 goto error_flash;
547
548 break;
549 case 0xe8:
550
551
552
553
554 if (pfl->device_width) {
555 value = extract32(value, 0, pfl->device_width * 8);
556 } else {
557 value = extract32(value, 0, pfl->bank_width * 8);
558 }
559 DPRINTF("%s: block write of %x bytes\n", __func__, value);
560 pfl->counter = value;
561 pfl->wcycle++;
562 break;
563 case 0x60:
564 if (cmd == 0xd0) {
565 pfl->wcycle = 0;
566 pfl->status |= 0x80;
567 } else if (cmd == 0x01) {
568 pfl->wcycle = 0;
569 pfl->status |= 0x80;
570 } else if (cmd == 0xff) {
571 goto reset_flash;
572 } else {
573 DPRINTF("%s: Unknown (un)locking command\n", __func__);
574 goto reset_flash;
575 }
576 break;
577 case 0x98:
578 if (cmd == 0xff) {
579 goto reset_flash;
580 } else {
581 DPRINTF("%s: leaving query mode\n", __func__);
582 }
583 break;
584 default:
585 goto error_flash;
586 }
587 break;
588 case 2:
589 switch (pfl->cmd) {
590 case 0xe8:
591
592 if (!pfl->ro) {
593
594
595
596
597
598 pflash_data_write(pfl, offset, value, width, be);
599 } else {
600 pfl->status |= 0x10;
601 }
602
603 pfl->status |= 0x80;
604
605 if (!pfl->counter) {
606 hwaddr mask = pfl->writeblock_size - 1;
607 mask = ~mask;
608
609 DPRINTF("%s: block write finished\n", __func__);
610 pfl->wcycle++;
611 if (!pfl->ro) {
612
613
614 pflash_update(pfl, offset & mask, pfl->writeblock_size);
615 } else {
616 pfl->status |= 0x10;
617 }
618 }
619
620 pfl->counter--;
621 break;
622 default:
623 goto error_flash;
624 }
625 break;
626 case 3:
627 switch (pfl->cmd) {
628 case 0xe8:
629 if (cmd == 0xd0) {
630
631 pfl->wcycle = 0;
632 pfl->status |= 0x80;
633 } else {
634 qemu_log_mask(LOG_UNIMP,
635 "%s: Aborting write to buffer not implemented,"
636 " the data is already written to storage!\n"
637 "Flash device reset into READ mode.\n",
638 __func__);
639 goto reset_flash;
640 }
641 break;
642 default:
643 goto error_flash;
644 }
645 break;
646 default:
647
648 DPRINTF("%s: invalid write state\n", __func__);
649 goto reset_flash;
650 }
651 return;
652
653 error_flash:
654 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence "
655 "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)"
656 "\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
657
658 reset_flash:
659 trace_pflash_reset();
660 memory_region_rom_device_set_romd(&pfl->mem, true);
661 pfl->wcycle = 0;
662 pfl->cmd = 0;
663}
664
665
666static MemTxResult pflash_mem_read_with_attrs(void *opaque, hwaddr addr, uint64_t *value,
667 unsigned len, MemTxAttrs attrs)
668{
669 PFlashCFI01 *pfl = opaque;
670 bool be = !!(pfl->features & (1 << PFLASH_BE));
671
672 if ((pfl->features & (1 << PFLASH_SECURE)) && !attrs.secure) {
673 *value = pflash_data_read(opaque, addr, len, be);
674 } else {
675 *value = pflash_read(opaque, addr, len, be);
676 }
677 return MEMTX_OK;
678}
679
680static MemTxResult pflash_mem_write_with_attrs(void *opaque, hwaddr addr, uint64_t value,
681 unsigned len, MemTxAttrs attrs)
682{
683 PFlashCFI01 *pfl = opaque;
684 bool be = !!(pfl->features & (1 << PFLASH_BE));
685
686 if ((pfl->features & (1 << PFLASH_SECURE)) && !attrs.secure) {
687 return MEMTX_ERROR;
688 } else {
689 pflash_write(opaque, addr, value, len, be);
690 return MEMTX_OK;
691 }
692}
693
694static const MemoryRegionOps pflash_cfi01_ops = {
695 .read_with_attrs = pflash_mem_read_with_attrs,
696 .write_with_attrs = pflash_mem_write_with_attrs,
697 .endianness = DEVICE_NATIVE_ENDIAN,
698};
699
700static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
701{
702 PFlashCFI01 *pfl = PFLASH_CFI01(dev);
703 uint64_t total_len;
704 int ret;
705 uint64_t blocks_per_device, sector_len_per_device, device_len;
706 int num_devices;
707 Error *local_err = NULL;
708
709 if (pfl->sector_len == 0) {
710 error_setg(errp, "attribute \"sector-length\" not specified or zero.");
711 return;
712 }
713 if (pfl->nb_blocs == 0) {
714 error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
715 return;
716 }
717 if (pfl->name == NULL) {
718 error_setg(errp, "attribute \"name\" not specified.");
719 return;
720 }
721
722 total_len = pfl->sector_len * pfl->nb_blocs;
723
724
725
726
727 num_devices = pfl->device_width ? (pfl->bank_width / pfl->device_width) : 1;
728 if (pfl->old_multiple_chip_handling) {
729 blocks_per_device = pfl->nb_blocs / num_devices;
730 sector_len_per_device = pfl->sector_len;
731 } else {
732 blocks_per_device = pfl->nb_blocs;
733 sector_len_per_device = pfl->sector_len / num_devices;
734 }
735 device_len = sector_len_per_device * blocks_per_device;
736
737 memory_region_init_rom_device(
738 &pfl->mem, OBJECT(dev),
739 &pflash_cfi01_ops,
740 pfl,
741 pfl->name, total_len, &local_err);
742 if (local_err) {
743 error_propagate(errp, local_err);
744 return;
745 }
746
747 pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
748 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
749
750 if (pfl->blk) {
751 uint64_t perm;
752 pfl->ro = blk_is_read_only(pfl->blk);
753 perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
754 ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
755 if (ret < 0) {
756 return;
757 }
758 } else {
759 pfl->ro = 0;
760 }
761
762 if (pfl->blk) {
763 if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, total_len,
764 errp)) {
765 vmstate_unregister_ram(&pfl->mem, DEVICE(pfl));
766 return;
767 }
768 }
769
770
771
772
773 if (!pfl->max_device_width) {
774 pfl->max_device_width = pfl->device_width;
775 }
776
777 pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
778 pfl->wcycle = 0;
779 pfl->cmd = 0;
780 pfl->status = 0x80;
781
782
783 pfl->cfi_table[0x10] = 'Q';
784 pfl->cfi_table[0x11] = 'R';
785 pfl->cfi_table[0x12] = 'Y';
786
787 pfl->cfi_table[0x13] = 0x01;
788 pfl->cfi_table[0x14] = 0x00;
789
790 pfl->cfi_table[0x15] = 0x31;
791 pfl->cfi_table[0x16] = 0x00;
792
793 pfl->cfi_table[0x17] = 0x00;
794 pfl->cfi_table[0x18] = 0x00;
795
796 pfl->cfi_table[0x19] = 0x00;
797 pfl->cfi_table[0x1A] = 0x00;
798
799 pfl->cfi_table[0x1B] = 0x45;
800
801 pfl->cfi_table[0x1C] = 0x55;
802
803 pfl->cfi_table[0x1D] = 0x00;
804
805 pfl->cfi_table[0x1E] = 0x00;
806
807 pfl->cfi_table[0x1F] = 0x07;
808
809 pfl->cfi_table[0x20] = 0x07;
810
811 pfl->cfi_table[0x21] = 0x0a;
812
813 pfl->cfi_table[0x22] = 0x00;
814
815 pfl->cfi_table[0x23] = 0x04;
816
817 pfl->cfi_table[0x24] = 0x04;
818
819 pfl->cfi_table[0x25] = 0x04;
820
821 pfl->cfi_table[0x26] = 0x00;
822
823 pfl->cfi_table[0x27] = ctz32(device_len);
824
825 pfl->cfi_table[0x28] = 0x02;
826 pfl->cfi_table[0x29] = 0x00;
827
828 if (pfl->bank_width == 1) {
829 pfl->cfi_table[0x2A] = 0x08;
830 } else {
831 pfl->cfi_table[0x2A] = 0x0B;
832 }
833 pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
834 if (!pfl->old_multiple_chip_handling && num_devices > 1) {
835 pfl->writeblock_size *= num_devices;
836 }
837
838 pfl->cfi_table[0x2B] = 0x00;
839
840 pfl->cfi_table[0x2C] = 0x01;
841
842 pfl->cfi_table[0x2D] = blocks_per_device - 1;
843 pfl->cfi_table[0x2E] = (blocks_per_device - 1) >> 8;
844 pfl->cfi_table[0x2F] = sector_len_per_device >> 8;
845 pfl->cfi_table[0x30] = sector_len_per_device >> 16;
846
847
848 pfl->cfi_table[0x31] = 'P';
849 pfl->cfi_table[0x32] = 'R';
850 pfl->cfi_table[0x33] = 'I';
851
852 pfl->cfi_table[0x34] = '1';
853 pfl->cfi_table[0x35] = '0';
854
855 pfl->cfi_table[0x36] = 0x00;
856 pfl->cfi_table[0x37] = 0x00;
857 pfl->cfi_table[0x38] = 0x00;
858 pfl->cfi_table[0x39] = 0x00;
859
860 pfl->cfi_table[0x3a] = 0x00;
861
862 pfl->cfi_table[0x3b] = 0x00;
863 pfl->cfi_table[0x3c] = 0x00;
864
865 pfl->cfi_table[0x3f] = 0x01;
866}
867
868static void pflash_cfi01_system_reset(DeviceState *dev)
869{
870 PFlashCFI01 *pfl = PFLASH_CFI01(dev);
871
872
873
874
875
876 pfl->cmd = 0x00;
877 pfl->wcycle = 0;
878 memory_region_rom_device_set_romd(&pfl->mem, true);
879
880
881
882
883 pfl->status = 0x80;
884}
885
886static Property pflash_cfi01_properties[] = {
887 DEFINE_PROP_DRIVE("drive", PFlashCFI01, blk),
888
889
890
891
892
893 DEFINE_PROP_UINT32("num-blocks", PFlashCFI01, nb_blocs, 0),
894 DEFINE_PROP_UINT64("sector-length", PFlashCFI01, sector_len, 0),
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911 DEFINE_PROP_UINT8("width", PFlashCFI01, bank_width, 0),
912 DEFINE_PROP_UINT8("device-width", PFlashCFI01, device_width, 0),
913 DEFINE_PROP_UINT8("max-device-width", PFlashCFI01, max_device_width, 0),
914 DEFINE_PROP_BIT("big-endian", PFlashCFI01, features, PFLASH_BE, 0),
915 DEFINE_PROP_BIT("secure", PFlashCFI01, features, PFLASH_SECURE, 0),
916 DEFINE_PROP_UINT16("id0", PFlashCFI01, ident0, 0),
917 DEFINE_PROP_UINT16("id1", PFlashCFI01, ident1, 0),
918 DEFINE_PROP_UINT16("id2", PFlashCFI01, ident2, 0),
919 DEFINE_PROP_UINT16("id3", PFlashCFI01, ident3, 0),
920 DEFINE_PROP_STRING("name", PFlashCFI01, name),
921 DEFINE_PROP_BOOL("old-multiple-chip-handling", PFlashCFI01,
922 old_multiple_chip_handling, false),
923 DEFINE_PROP_END_OF_LIST(),
924};
925
926static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
927{
928 DeviceClass *dc = DEVICE_CLASS(klass);
929
930 dc->reset = pflash_cfi01_system_reset;
931 dc->realize = pflash_cfi01_realize;
932 dc->props = pflash_cfi01_properties;
933 dc->vmsd = &vmstate_pflash;
934 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
935}
936
937
938static const TypeInfo pflash_cfi01_info = {
939 .name = TYPE_PFLASH_CFI01,
940 .parent = TYPE_SYS_BUS_DEVICE,
941 .instance_size = sizeof(PFlashCFI01),
942 .class_init = pflash_cfi01_class_init,
943};
944
945static void pflash_cfi01_register_types(void)
946{
947 type_register_static(&pflash_cfi01_info);
948}
949
950type_init(pflash_cfi01_register_types)
951
952PFlashCFI01 *pflash_cfi01_register(hwaddr base,
953 const char *name,
954 hwaddr size,
955 BlockBackend *blk,
956 uint32_t sector_len,
957 int bank_width,
958 uint16_t id0, uint16_t id1,
959 uint16_t id2, uint16_t id3,
960 int be)
961{
962 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
963
964 if (blk) {
965 qdev_prop_set_drive(dev, "drive", blk, &error_abort);
966 }
967 assert(size % sector_len == 0);
968 qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
969 qdev_prop_set_uint64(dev, "sector-length", sector_len);
970 qdev_prop_set_uint8(dev, "width", bank_width);
971 qdev_prop_set_bit(dev, "big-endian", !!be);
972 qdev_prop_set_uint16(dev, "id0", id0);
973 qdev_prop_set_uint16(dev, "id1", id1);
974 qdev_prop_set_uint16(dev, "id2", id2);
975 qdev_prop_set_uint16(dev, "id3", id3);
976 qdev_prop_set_string(dev, "name", name);
977 qdev_init_nofail(dev);
978
979 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
980 return PFLASH_CFI01(dev);
981}
982
983BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl)
984{
985 return fl->blk;
986}
987
988MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl)
989{
990 return &fl->mem;
991}
992
993
994
995
996
997
998
999void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, DriveInfo *dinfo)
1000{
1001 Location loc;
1002
1003 if (!dinfo) {
1004 return;
1005 }
1006
1007 loc_push_none(&loc);
1008 qemu_opts_loc_restore(dinfo->opts);
1009 if (fl->blk) {
1010 error_report("clashes with -machine");
1011 exit(1);
1012 }
1013 qdev_prop_set_drive(DEVICE(fl), "drive",
1014 blk_by_legacy_dinfo(dinfo), &error_fatal);
1015 loc_pop(&loc);
1016}
1017
1018static void postload_update_cb(void *opaque, int running, RunState state)
1019{
1020 PFlashCFI01 *pfl = opaque;
1021
1022
1023 qemu_del_vm_change_state_handler(pfl->vmstate);
1024 pfl->vmstate = NULL;
1025
1026 DPRINTF("%s: updating bdrv for %s\n", __func__, pfl->name);
1027 pflash_update(pfl, 0, pfl->sector_len * pfl->nb_blocs);
1028}
1029
1030static int pflash_post_load(void *opaque, int version_id)
1031{
1032 PFlashCFI01 *pfl = opaque;
1033
1034 if (!pfl->ro) {
1035 pfl->vmstate = qemu_add_vm_change_state_handler(postload_update_cb,
1036 pfl);
1037 }
1038 return 0;
1039}
1040