LXR qemu/hw/char/bcm2835

   1/*
   2 * BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI).
   3 * Copyright (c) 2015, Microsoft
   4 * Written by Andrew Baumann
   5 * Based on pl011.c, copyright terms below:
   6 *
   7 * Arm PrimeCell PL011 UART
   8 *
   9 * Copyright (c) 2006 CodeSourcery.
  10 * Written by Paul Brook
  11 *
  12 * This code is licensed under the GPL.
  13 *
  14 * At present only the core UART functions (data path for tx/rx) are
  15 * implemented. The following features/registers are unimplemented:
  16 *  - Line/modem control
  17 *  - Scratch register
  18 *  - Extra control
  19 *  - Baudrate
  20 *  - SPI interfaces
  21 */
  22
  23#include "qemu/osdep.h"
  24#include "hw/char/bcm2835_aux.h"
  25#include "qemu/log.h"
  26#include "qemu/module.h"
  27
  28#define AUX_IRQ         0x0
  29#define AUX_ENABLES     0x4
  30#define AUX_MU_IO_REG   0x40
  31#define AUX_MU_IER_REG  0x44
  32#define AUX_MU_IIR_REG  0x48
  33#define AUX_MU_LCR_REG  0x4c
  34#define AUX_MU_MCR_REG  0x50
  35#define AUX_MU_LSR_REG  0x54
  36#define AUX_MU_MSR_REG  0x58
  37#define AUX_MU_SCRATCH  0x5c
  38#define AUX_MU_CNTL_REG 0x60
  39#define AUX_MU_STAT_REG 0x64
  40#define AUX_MU_BAUD_REG 0x68
  41
  42/* bits in IER/IIR registers */
  43#define RX_INT  0x1
  44#define TX_INT  0x2
  45
  46static void bcm2835_aux_update(BCM2835AuxState *s)
  47{
  48    /* signal an interrupt if either:
  49     * 1. rx interrupt is enabled and we have a non-empty rx fifo, or
  50     * 2. the tx interrupt is enabled (since we instantly drain the tx fifo)
  51     */
  52    s->iir = 0;
  53    if ((s->ier & RX_INT) && s->read_count != 0) {
  54        s->iir |= RX_INT;
  55    }
  56    if (s->ier & TX_INT) {
  57        s->iir |= TX_INT;
  58    }
  59    qemu_set_irq(s->irq, s->iir != 0);
  60}
  61
  62static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
  63{
  64    BCM2835AuxState *s = opaque;
  65    uint32_t c, res;
  66
  67    switch (offset) {
  68    case AUX_IRQ:
  69        return s->iir != 0;
  70
  71    case AUX_ENABLES:
  72        return 1; /* mini UART permanently enabled */
  73
  74    case AUX_MU_IO_REG:
  75        /* "DLAB bit set means access baudrate register" is NYI */
  76        c = s->read_fifo[s->read_pos];
  77        if (s->read_count > 0) {
  78            s->read_count--;
  79            if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) {
  80                s->read_pos = 0;
  81            }
  82        }
  83        qemu_chr_fe_accept_input(&s->chr);
  84        bcm2835_aux_update(s);
  85        return c;
  86
  87    case AUX_MU_IER_REG:
  88        /* "DLAB bit set means access baudrate register" is NYI */
  89        return 0xc0 | s->ier; /* FIFO enables always read 1 */
  90
  91    case AUX_MU_IIR_REG:
  92        res = 0xc0; /* FIFO enables */
  93        /* The spec is unclear on what happens when both tx and rx
  94         * interrupts are active, besides that this cannot occur. At
  95         * present, we choose to prioritise the rx interrupt, since
  96         * the tx fifo is always empty. */
  97        if (s->read_count != 0) {
  98            res |= 0x4;
  99        } else {
 100            res |= 0x2;
 101        }
 102        if (s->iir == 0) {
 103            res |= 0x1;
 104        }
 105        return res;
 106
 107    case AUX_MU_LCR_REG:
 108        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
 109        return 0;
 110
 111    case AUX_MU_MCR_REG:
 112        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
 113        return 0;
 114
 115    case AUX_MU_LSR_REG:
 116        res = 0x60; /* tx idle, empty */
 117        if (s->read_count != 0) {
 118            res |= 0x1;
 119        }
 120        return res;
 121
 122    case AUX_MU_MSR_REG:
 123        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__);
 124        return 0;
 125
 126    case AUX_MU_SCRATCH:
 127        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
 128        return 0;
 129
 130    case AUX_MU_CNTL_REG:
 131        return 0x3; /* tx, rx enabled */
 132
 133    case AUX_MU_STAT_REG:
 134        res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */
 135        if (s->read_count > 0) {
 136            res |= 0x1; /* data in input buffer */
 137            assert(s->read_count < BCM2835_AUX_RX_FIFO_LEN);
 138            res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */
 139        }
 140        return res;
 141
 142    case AUX_MU_BAUD_REG:
 143        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
 144        return 0;
 145
 146    default:
 147        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 148                      __func__, offset);
 149        return 0;
 150    }
 151}
 152
 153static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value,
 154                              unsigned size)
 155{
 156    BCM2835AuxState *s = opaque;
 157    unsigned char ch;
 158
 159    switch (offset) {
 160    case AUX_ENABLES:
 161        if (value != 1) {
 162            qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI "
 163                          "or disable UART\n", __func__);
 164        }
 165        break;
 166
 167    case AUX_MU_IO_REG:
 168        /* "DLAB bit set means access baudrate register" is NYI */
 169        ch = value;
 170        /* XXX this blocks entire thread. Rewrite to use
 171         * qemu_chr_fe_write and background I/O callbacks */
 172        qemu_chr_fe_write_all(&s->chr, &ch, 1);
 173        break;
 174
 175    case AUX_MU_IER_REG:
 176        /* "DLAB bit set means access baudrate register" is NYI */
 177        s->ier = value & (TX_INT | RX_INT);
 178        bcm2835_aux_update(s);
 179        break;
 180
 181    case AUX_MU_IIR_REG:
 182        if (value & 0x2) {
 183            s->read_count = 0;
 184        }
 185        break;
 186
 187    case AUX_MU_LCR_REG:
 188        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
 189        break;
 190
 191    case AUX_MU_MCR_REG:
 192        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
 193        break;
 194
 195    case AUX_MU_SCRATCH:
 196        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
 197        break;
 198
 199    case AUX_MU_CNTL_REG:
 200        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__);
 201        break;
 202
 203    case AUX_MU_BAUD_REG:
 204        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
 205        break;
 206
 207    default:
 208        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 209                      __func__, offset);
 210    }
 211
 212    bcm2835_aux_update(s);
 213}
 214
 215static int bcm2835_aux_can_receive(void *opaque)
 216{
 217    BCM2835AuxState *s = opaque;
 218
 219    return s->read_count < BCM2835_AUX_RX_FIFO_LEN;
 220}
 221
 222static void bcm2835_aux_put_fifo(void *opaque, uint8_t value)
 223{
 224    BCM2835AuxState *s = opaque;
 225    int slot;
 226
 227    slot = s->read_pos + s->read_count;
 228    if (slot >= BCM2835_AUX_RX_FIFO_LEN) {
 229        slot -= BCM2835_AUX_RX_FIFO_LEN;
 230    }
 231    s->read_fifo[slot] = value;
 232    s->read_count++;
 233    if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) {
 234        /* buffer full */
 235    }
 236    bcm2835_aux_update(s);
 237}
 238
 239static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size)
 240{
 241    bcm2835_aux_put_fifo(opaque, *buf);
 242}
 243
 244static const MemoryRegionOps bcm2835_aux_ops = {
 245    .read = bcm2835_aux_read,
 246    .write = bcm2835_aux_write,
 247    .endianness = DEVICE_NATIVE_ENDIAN,
 248    .valid.min_access_size = 4,
 249    .valid.max_access_size = 4,
 250};
 251
 252static const VMStateDescription vmstate_bcm2835_aux = {
 253    .name = TYPE_BCM2835_AUX,
 254    .version_id = 1,
 255    .minimum_version_id = 1,
 256    .fields = (VMStateField[]) {
 257        VMSTATE_UINT8_ARRAY(read_fifo, BCM2835AuxState,
 258                            BCM2835_AUX_RX_FIFO_LEN),
 259        VMSTATE_UINT8(read_pos, BCM2835AuxState),
 260        VMSTATE_UINT8(read_count, BCM2835AuxState),
 261        VMSTATE_UINT8(ier, BCM2835AuxState),
 262        VMSTATE_UINT8(iir, BCM2835AuxState),
 263        VMSTATE_END_OF_LIST()
 264    }
 265};
 266
 267static void bcm2835_aux_init(Object *obj)
 268{
 269    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 270    BCM2835AuxState *s = BCM2835_AUX(obj);
 271
 272    memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s,
 273                          TYPE_BCM2835_AUX, 0x100);
 274    sysbus_init_mmio(sbd, &s->iomem);
 275    sysbus_init_irq(sbd, &s->irq);
 276}
 277
 278static void bcm2835_aux_realize(DeviceState *dev, Error **errp)
 279{
 280    BCM2835AuxState *s = BCM2835_AUX(dev);
 281
 282    qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
 283                             bcm2835_aux_receive, NULL, NULL, s, NULL, true);
 284}
 285
 286static Property bcm2835_aux_props[] = {
 287    DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr),
 288    DEFINE_PROP_END_OF_LIST(),
 289};
 290
 291static void bcm2835_aux_class_init(ObjectClass *oc, void *data)
 292{
 293    DeviceClass *dc = DEVICE_CLASS(oc);
 294
 295    dc->realize = bcm2835_aux_realize;
 296    dc->vmsd = &vmstate_bcm2835_aux;
 297    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 298    dc->props = bcm2835_aux_props;
 299}
 300
 301static const TypeInfo bcm2835_aux_info = {
 302    .name          = TYPE_BCM2835_AUX,
 303    .parent        = TYPE_SYS_BUS_DEVICE,
 304    .instance_size = sizeof(BCM2835AuxState),
 305    .instance_init = bcm2835_aux_init,
 306    .class_init    = bcm2835_aux_class_init,
 307};
 308
 309static void bcm2835_aux_register_types(void)
 310{
 311    type_register_static(&bcm2835_aux_info);
 312}
 313
 314type_init(bcm2835_aux_register_types)
 315