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24#include "qemu/osdep.h"
25#include "hw/sysbus.h"
26#include "chardev/char-fe.h"
27#include "chardev/char-serial.h"
28#include "qemu/timer.h"
29#include "qemu/log.h"
30#include "qemu/module.h"
31#include "hw/char/cadence_uart.h"
32
33#ifdef CADENCE_UART_ERR_DEBUG
34#define DB_PRINT(...) do { \
35 fprintf(stderr, ": %s: ", __func__); \
36 fprintf(stderr, ## __VA_ARGS__); \
37 } while (0)
38#else
39 #define DB_PRINT(...)
40#endif
41
42#define UART_SR_INTR_RTRIG 0x00000001
43#define UART_SR_INTR_REMPTY 0x00000002
44#define UART_SR_INTR_RFUL 0x00000004
45#define UART_SR_INTR_TEMPTY 0x00000008
46#define UART_SR_INTR_TFUL 0x00000010
47
48#define UART_SR_TTRIG 0x00002000
49#define UART_INTR_TTRIG 0x00000400
50
51
52#define UART_SR_TO_CISR_MASK 0x0000001F
53
54#define UART_INTR_ROVR 0x00000020
55#define UART_INTR_FRAME 0x00000040
56#define UART_INTR_PARE 0x00000080
57#define UART_INTR_TIMEOUT 0x00000100
58#define UART_INTR_DMSI 0x00000200
59#define UART_INTR_TOVR 0x00001000
60
61#define UART_SR_RACTIVE 0x00000400
62#define UART_SR_TACTIVE 0x00000800
63#define UART_SR_FDELT 0x00001000
64
65#define UART_CR_RXRST 0x00000001
66#define UART_CR_TXRST 0x00000002
67#define UART_CR_RX_EN 0x00000004
68#define UART_CR_RX_DIS 0x00000008
69#define UART_CR_TX_EN 0x00000010
70#define UART_CR_TX_DIS 0x00000020
71#define UART_CR_RST_TO 0x00000040
72#define UART_CR_STARTBRK 0x00000080
73#define UART_CR_STOPBRK 0x00000100
74
75#define UART_MR_CLKS 0x00000001
76#define UART_MR_CHRL 0x00000006
77#define UART_MR_CHRL_SH 1
78#define UART_MR_PAR 0x00000038
79#define UART_MR_PAR_SH 3
80#define UART_MR_NBSTOP 0x000000C0
81#define UART_MR_NBSTOP_SH 6
82#define UART_MR_CHMODE 0x00000300
83#define UART_MR_CHMODE_SH 8
84#define UART_MR_UCLKEN 0x00000400
85#define UART_MR_IRMODE 0x00000800
86
87#define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
88#define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
89#define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
90#define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
91#define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
92#define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
93#define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
94#define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
95#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
96#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
97
98#define UART_INPUT_CLK 50000000
99
100#define R_CR (0x00/4)
101#define R_MR (0x04/4)
102#define R_IER (0x08/4)
103#define R_IDR (0x0C/4)
104#define R_IMR (0x10/4)
105#define R_CISR (0x14/4)
106#define R_BRGR (0x18/4)
107#define R_RTOR (0x1C/4)
108#define R_RTRIG (0x20/4)
109#define R_MCR (0x24/4)
110#define R_MSR (0x28/4)
111#define R_SR (0x2C/4)
112#define R_TX_RX (0x30/4)
113#define R_BDIV (0x34/4)
114#define R_FDEL (0x38/4)
115#define R_PMIN (0x3C/4)
116#define R_PWID (0x40/4)
117#define R_TTRIG (0x44/4)
118
119
120static void uart_update_status(CadenceUARTState *s)
121{
122 s->r[R_SR] = 0;
123
124 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
125 : 0;
126 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
127 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
128
129 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
130 : 0;
131 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
132 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
133
134 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
135 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
136 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
137}
138
139static void fifo_trigger_update(void *opaque)
140{
141 CadenceUARTState *s = opaque;
142
143 if (s->r[R_RTOR]) {
144 s->r[R_CISR] |= UART_INTR_TIMEOUT;
145 uart_update_status(s);
146 }
147}
148
149static void uart_rx_reset(CadenceUARTState *s)
150{
151 s->rx_wpos = 0;
152 s->rx_count = 0;
153 qemu_chr_fe_accept_input(&s->chr);
154}
155
156static void uart_tx_reset(CadenceUARTState *s)
157{
158 s->tx_count = 0;
159}
160
161static void uart_send_breaks(CadenceUARTState *s)
162{
163 int break_enabled = 1;
164
165 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
166 &break_enabled);
167}
168
169static void uart_parameters_setup(CadenceUARTState *s)
170{
171 QEMUSerialSetParams ssp;
172 unsigned int baud_rate, packet_size;
173
174 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
175 UART_INPUT_CLK / 8 : UART_INPUT_CLK;
176
177 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
178 packet_size = 1;
179
180 switch (s->r[R_MR] & UART_MR_PAR) {
181 case UART_PARITY_EVEN:
182 ssp.parity = 'E';
183 packet_size++;
184 break;
185 case UART_PARITY_ODD:
186 ssp.parity = 'O';
187 packet_size++;
188 break;
189 default:
190 ssp.parity = 'N';
191 break;
192 }
193
194 switch (s->r[R_MR] & UART_MR_CHRL) {
195 case UART_DATA_BITS_6:
196 ssp.data_bits = 6;
197 break;
198 case UART_DATA_BITS_7:
199 ssp.data_bits = 7;
200 break;
201 default:
202 ssp.data_bits = 8;
203 break;
204 }
205
206 switch (s->r[R_MR] & UART_MR_NBSTOP) {
207 case UART_STOP_BITS_1:
208 ssp.stop_bits = 1;
209 break;
210 default:
211 ssp.stop_bits = 2;
212 break;
213 }
214
215 packet_size += ssp.data_bits + ssp.stop_bits;
216 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
217 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
218}
219
220static int uart_can_receive(void *opaque)
221{
222 CadenceUARTState *s = opaque;
223 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
224 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
225
226 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
227 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
228 }
229 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
230 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
231 }
232 return ret;
233}
234
235static void uart_ctrl_update(CadenceUARTState *s)
236{
237 if (s->r[R_CR] & UART_CR_TXRST) {
238 uart_tx_reset(s);
239 }
240
241 if (s->r[R_CR] & UART_CR_RXRST) {
242 uart_rx_reset(s);
243 }
244
245 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
246
247 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
248 uart_send_breaks(s);
249 }
250}
251
252static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
253{
254 CadenceUARTState *s = opaque;
255 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
256 int i;
257
258 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
259 return;
260 }
261
262 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
263 s->r[R_CISR] |= UART_INTR_ROVR;
264 } else {
265 for (i = 0; i < size; i++) {
266 s->rx_fifo[s->rx_wpos] = buf[i];
267 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
268 s->rx_count++;
269 }
270 timer_mod(s->fifo_trigger_handle, new_rx_time +
271 (s->char_tx_time * 4));
272 }
273 uart_update_status(s);
274}
275
276static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
277 void *opaque)
278{
279 CadenceUARTState *s = opaque;
280 int ret;
281
282
283 if (!qemu_chr_fe_backend_connected(&s->chr)) {
284 s->tx_count = 0;
285 return FALSE;
286 }
287
288 if (!s->tx_count) {
289 return FALSE;
290 }
291
292 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);
293
294 if (ret >= 0) {
295 s->tx_count -= ret;
296 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
297 }
298
299 if (s->tx_count) {
300 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
301 cadence_uart_xmit, s);
302 if (!r) {
303 s->tx_count = 0;
304 return FALSE;
305 }
306 }
307
308 uart_update_status(s);
309 return FALSE;
310}
311
312static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
313 int size)
314{
315 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
316 return;
317 }
318
319 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
320 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
321
322
323
324
325
326 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
327 s->r[R_CISR] |= UART_INTR_ROVR;
328 }
329
330 memcpy(s->tx_fifo + s->tx_count, buf, size);
331 s->tx_count += size;
332
333 cadence_uart_xmit(NULL, G_IO_OUT, s);
334}
335
336static void uart_receive(void *opaque, const uint8_t *buf, int size)
337{
338 CadenceUARTState *s = opaque;
339 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
340
341 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
342 uart_write_rx_fifo(opaque, buf, size);
343 }
344 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
345 uart_write_tx_fifo(s, buf, size);
346 }
347}
348
349static void uart_event(void *opaque, int event)
350{
351 CadenceUARTState *s = opaque;
352 uint8_t buf = '\0';
353
354 if (event == CHR_EVENT_BREAK) {
355 uart_write_rx_fifo(opaque, &buf, 1);
356 }
357
358 uart_update_status(s);
359}
360
361static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
362{
363 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
364 return;
365 }
366
367 if (s->rx_count) {
368 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
369 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
370 *c = s->rx_fifo[rx_rpos];
371 s->rx_count--;
372
373 qemu_chr_fe_accept_input(&s->chr);
374 } else {
375 *c = 0;
376 }
377
378 uart_update_status(s);
379}
380
381static void uart_write(void *opaque, hwaddr offset,
382 uint64_t value, unsigned size)
383{
384 CadenceUARTState *s = opaque;
385
386 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
387 offset >>= 2;
388 if (offset >= CADENCE_UART_R_MAX) {
389 return;
390 }
391 switch (offset) {
392 case R_IER:
393 s->r[R_IMR] |= value;
394 break;
395 case R_IDR:
396 s->r[R_IMR] &= ~value;
397 break;
398 case R_IMR:
399 break;
400 case R_CISR:
401 s->r[R_CISR] &= ~value;
402 break;
403 case R_TX_RX:
404 switch (s->r[R_MR] & UART_MR_CHMODE) {
405 case NORMAL_MODE:
406 uart_write_tx_fifo(s, (uint8_t *) &value, 1);
407 break;
408 case LOCAL_LOOPBACK:
409 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
410 break;
411 }
412 break;
413 case R_BRGR:
414 if (value >= 0x01) {
415 s->r[offset] = value & 0xFFFF;
416 }
417 break;
418 case R_BDIV:
419 if (value >= 0x04) {
420 s->r[offset] = value & 0xFF;
421 }
422 break;
423 default:
424 s->r[offset] = value;
425 }
426
427 switch (offset) {
428 case R_CR:
429 uart_ctrl_update(s);
430 break;
431 case R_MR:
432 uart_parameters_setup(s);
433 break;
434 }
435 uart_update_status(s);
436}
437
438static uint64_t uart_read(void *opaque, hwaddr offset,
439 unsigned size)
440{
441 CadenceUARTState *s = opaque;
442 uint32_t c = 0;
443
444 offset >>= 2;
445 if (offset >= CADENCE_UART_R_MAX) {
446 c = 0;
447 } else if (offset == R_TX_RX) {
448 uart_read_rx_fifo(s, &c);
449 } else {
450 c = s->r[offset];
451 }
452
453 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
454 return c;
455}
456
457static const MemoryRegionOps uart_ops = {
458 .read = uart_read,
459 .write = uart_write,
460 .endianness = DEVICE_NATIVE_ENDIAN,
461};
462
463static void cadence_uart_reset(DeviceState *dev)
464{
465 CadenceUARTState *s = CADENCE_UART(dev);
466
467 s->r[R_CR] = 0x00000128;
468 s->r[R_IMR] = 0;
469 s->r[R_CISR] = 0;
470 s->r[R_RTRIG] = 0x00000020;
471 s->r[R_BRGR] = 0x0000028B;
472 s->r[R_BDIV] = 0x0000000F;
473 s->r[R_TTRIG] = 0x00000020;
474
475 uart_rx_reset(s);
476 uart_tx_reset(s);
477
478 uart_update_status(s);
479}
480
481static void cadence_uart_realize(DeviceState *dev, Error **errp)
482{
483 CadenceUARTState *s = CADENCE_UART(dev);
484
485 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
486 fifo_trigger_update, s);
487
488 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
489 uart_event, NULL, s, NULL, true);
490}
491
492static void cadence_uart_init(Object *obj)
493{
494 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
495 CadenceUARTState *s = CADENCE_UART(obj);
496
497 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
498 sysbus_init_mmio(sbd, &s->iomem);
499 sysbus_init_irq(sbd, &s->irq);
500
501 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
502}
503
504static int cadence_uart_post_load(void *opaque, int version_id)
505{
506 CadenceUARTState *s = opaque;
507
508
509 if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF ||
510 s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) {
511
512 return 1;
513 }
514
515 uart_parameters_setup(s);
516 uart_update_status(s);
517 return 0;
518}
519
520static const VMStateDescription vmstate_cadence_uart = {
521 .name = "cadence_uart",
522 .version_id = 2,
523 .minimum_version_id = 2,
524 .post_load = cadence_uart_post_load,
525 .fields = (VMStateField[]) {
526 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
527 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
528 CADENCE_UART_RX_FIFO_SIZE),
529 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
530 CADENCE_UART_TX_FIFO_SIZE),
531 VMSTATE_UINT32(rx_count, CadenceUARTState),
532 VMSTATE_UINT32(tx_count, CadenceUARTState),
533 VMSTATE_UINT32(rx_wpos, CadenceUARTState),
534 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
535 VMSTATE_END_OF_LIST()
536 }
537};
538
539static Property cadence_uart_properties[] = {
540 DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
541 DEFINE_PROP_END_OF_LIST(),
542};
543
544static void cadence_uart_class_init(ObjectClass *klass, void *data)
545{
546 DeviceClass *dc = DEVICE_CLASS(klass);
547
548 dc->realize = cadence_uart_realize;
549 dc->vmsd = &vmstate_cadence_uart;
550 dc->reset = cadence_uart_reset;
551 dc->props = cadence_uart_properties;
552 }
553
554static const TypeInfo cadence_uart_info = {
555 .name = TYPE_CADENCE_UART,
556 .parent = TYPE_SYS_BUS_DEVICE,
557 .instance_size = sizeof(CadenceUARTState),
558 .instance_init = cadence_uart_init,
559 .class_init = cadence_uart_class_init,
560};
561
562static void cadence_uart_register_types(void)
563{
564 type_register_static(&cadence_uart_info);
565}
566
567type_init(cadence_uart_register_types)
568