LXR qemu/hw/char/cmsdk-apb-uart.c

   1/*
   2 * ARM CMSDK APB UART emulation
   3 *
   4 * Copyright (c) 2017 Linaro Limited
   5 * Written by Peter Maydell
   6 *
   7 *  This program is free software; you can redistribute it and/or modify
   8 *  it under the terms of the GNU General Public License version 2 or
   9 *  (at your option) any later version.
  10 */
  11
  12/* This is a model of the "APB UART" which is part of the Cortex-M
  13 * System Design Kit (CMSDK) and documented in the Cortex-M System
  14 * Design Kit Technical Reference Manual (ARM DDI0479C):
  15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
  16 */
  17
  18#include "qemu/osdep.h"
  19#include "qemu/log.h"
  20#include "qemu/module.h"
  21#include "qapi/error.h"
  22#include "trace.h"
  23#include "hw/sysbus.h"
  24#include "hw/registerfields.h"
  25#include "chardev/char-fe.h"
  26#include "chardev/char-serial.h"
  27#include "hw/char/cmsdk-apb-uart.h"
  28
  29REG32(DATA, 0)
  30REG32(STATE, 4)
  31    FIELD(STATE, TXFULL, 0, 1)
  32    FIELD(STATE, RXFULL, 1, 1)
  33    FIELD(STATE, TXOVERRUN, 2, 1)
  34    FIELD(STATE, RXOVERRUN, 3, 1)
  35REG32(CTRL, 8)
  36    FIELD(CTRL, TX_EN, 0, 1)
  37    FIELD(CTRL, RX_EN, 1, 1)
  38    FIELD(CTRL, TX_INTEN, 2, 1)
  39    FIELD(CTRL, RX_INTEN, 3, 1)
  40    FIELD(CTRL, TXO_INTEN, 4, 1)
  41    FIELD(CTRL, RXO_INTEN, 5, 1)
  42    FIELD(CTRL, HSTEST, 6, 1)
  43REG32(INTSTATUS, 0xc)
  44    FIELD(INTSTATUS, TX, 0, 1)
  45    FIELD(INTSTATUS, RX, 1, 1)
  46    FIELD(INTSTATUS, TXO, 2, 1)
  47    FIELD(INTSTATUS, RXO, 3, 1)
  48REG32(BAUDDIV, 0x10)
  49REG32(PID4, 0xFD0)
  50REG32(PID5, 0xFD4)
  51REG32(PID6, 0xFD8)
  52REG32(PID7, 0xFDC)
  53REG32(PID0, 0xFE0)
  54REG32(PID1, 0xFE4)
  55REG32(PID2, 0xFE8)
  56REG32(PID3, 0xFEC)
  57REG32(CID0, 0xFF0)
  58REG32(CID1, 0xFF4)
  59REG32(CID2, 0xFF8)
  60REG32(CID3, 0xFFC)
  61
  62/* PID/CID values */
  63static const int uart_id[] = {
  64    0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
  65    0x21, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
  66    0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
  67};
  68
  69static bool uart_baudrate_ok(CMSDKAPBUART *s)
  70{
  71    /* The minimum permitted bauddiv setting is 16, so we just ignore
  72     * settings below that (usually this means the device has just
  73     * been reset and not yet programmed).
  74     */
  75    return s->bauddiv >= 16 && s->bauddiv <= s->pclk_frq;
  76}
  77
  78static void uart_update_parameters(CMSDKAPBUART *s)
  79{
  80    QEMUSerialSetParams ssp;
  81
  82    /* This UART is always 8N1 but the baud rate is programmable. */
  83    if (!uart_baudrate_ok(s)) {
  84        return;
  85    }
  86
  87    ssp.data_bits = 8;
  88    ssp.parity = 'N';
  89    ssp.stop_bits = 1;
  90    ssp.speed = s->pclk_frq / s->bauddiv;
  91    qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
  92    trace_cmsdk_apb_uart_set_params(ssp.speed);
  93}
  94
  95static void cmsdk_apb_uart_update(CMSDKAPBUART *s)
  96{
  97    /* update outbound irqs, including handling the way the rxo and txo
  98     * interrupt status bits are just logical AND of the overrun bit in
  99     * STATE and the overrun interrupt enable bit in CTRL.
 100     */
 101    uint32_t omask = (R_INTSTATUS_RXO_MASK | R_INTSTATUS_TXO_MASK);
 102    s->intstatus &= ~omask;
 103    s->intstatus |= (s->state & (s->ctrl >> 2) & omask);
 104
 105    qemu_set_irq(s->txint, !!(s->intstatus & R_INTSTATUS_TX_MASK));
 106    qemu_set_irq(s->rxint, !!(s->intstatus & R_INTSTATUS_RX_MASK));
 107    qemu_set_irq(s->txovrint, !!(s->intstatus & R_INTSTATUS_TXO_MASK));
 108    qemu_set_irq(s->rxovrint, !!(s->intstatus & R_INTSTATUS_RXO_MASK));
 109    qemu_set_irq(s->uartint, !!(s->intstatus));
 110}
 111
 112static int uart_can_receive(void *opaque)
 113{
 114    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
 115
 116    /* We can take a char if RX is enabled and the buffer is empty */
 117    if (s->ctrl & R_CTRL_RX_EN_MASK && !(s->state & R_STATE_RXFULL_MASK)) {
 118        return 1;
 119    }
 120    return 0;
 121}
 122
 123static void uart_receive(void *opaque, const uint8_t *buf, int size)
 124{
 125    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
 126
 127    trace_cmsdk_apb_uart_receive(*buf);
 128
 129    /* In fact uart_can_receive() ensures that we can't be
 130     * called unless RX is enabled and the buffer is empty,
 131     * but we include this logic as documentation of what the
 132     * hardware does if a character arrives in these circumstances.
 133     */
 134    if (!(s->ctrl & R_CTRL_RX_EN_MASK)) {
 135        /* Just drop the character on the floor */
 136        return;
 137    }
 138
 139    if (s->state & R_STATE_RXFULL_MASK) {
 140        s->state |= R_STATE_RXOVERRUN_MASK;
 141    }
 142
 143    s->rxbuf = *buf;
 144    s->state |= R_STATE_RXFULL_MASK;
 145    if (s->ctrl & R_CTRL_RX_INTEN_MASK) {
 146        s->intstatus |= R_INTSTATUS_RX_MASK;
 147    }
 148    cmsdk_apb_uart_update(s);
 149}
 150
 151static uint64_t uart_read(void *opaque, hwaddr offset, unsigned size)
 152{
 153    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
 154    uint64_t r;
 155
 156    switch (offset) {
 157    case A_DATA:
 158        r = s->rxbuf;
 159        s->state &= ~R_STATE_RXFULL_MASK;
 160        cmsdk_apb_uart_update(s);
 161        qemu_chr_fe_accept_input(&s->chr);
 162        break;
 163    case A_STATE:
 164        r = s->state;
 165        break;
 166    case A_CTRL:
 167        r = s->ctrl;
 168        break;
 169    case A_INTSTATUS:
 170        r = s->intstatus;
 171        break;
 172    case A_BAUDDIV:
 173        r = s->bauddiv;
 174        break;
 175    case A_PID4 ... A_CID3:
 176        r = uart_id[(offset - A_PID4) / 4];
 177        break;
 178    default:
 179        qemu_log_mask(LOG_GUEST_ERROR,
 180                      "CMSDK APB UART read: bad offset %x\n", (int) offset);
 181        r = 0;
 182        break;
 183    }
 184    trace_cmsdk_apb_uart_read(offset, r, size);
 185    return r;
 186}
 187
 188/* Try to send tx data, and arrange to be called back later if
 189 * we can't (ie the char backend is busy/blocking).
 190 */
 191static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque)
 192{
 193    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
 194    int ret;
 195
 196    s->watch_tag = 0;
 197
 198    if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK)) {
 199        return FALSE;
 200    }
 201
 202    ret = qemu_chr_fe_write(&s->chr, &s->txbuf, 1);
 203    if (ret <= 0) {
 204        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 205                                             uart_transmit, s);
 206        if (!s->watch_tag) {
 207            /* Most common reason to be here is "no chardev backend":
 208             * just insta-drain the buffer, so the serial output
 209             * goes into a void, rather than blocking the guest.
 210             */
 211            goto buffer_drained;
 212        }
 213        /* Transmit pending */
 214        trace_cmsdk_apb_uart_tx_pending();
 215        return FALSE;
 216    }
 217
 218buffer_drained:
 219    /* Character successfully sent */
 220    trace_cmsdk_apb_uart_tx(s->txbuf);
 221    s->state &= ~R_STATE_TXFULL_MASK;
 222    /* Going from TXFULL set to clear triggers the tx interrupt */
 223    if (s->ctrl & R_CTRL_TX_INTEN_MASK) {
 224        s->intstatus |= R_INTSTATUS_TX_MASK;
 225    }
 226    cmsdk_apb_uart_update(s);
 227    return FALSE;
 228}
 229
 230static void uart_cancel_transmit(CMSDKAPBUART *s)
 231{
 232    if (s->watch_tag) {
 233        g_source_remove(s->watch_tag);
 234        s->watch_tag = 0;
 235    }
 236}
 237
 238static void uart_write(void *opaque, hwaddr offset, uint64_t value,
 239                       unsigned size)
 240{
 241    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
 242
 243    trace_cmsdk_apb_uart_write(offset, value, size);
 244
 245    switch (offset) {
 246    case A_DATA:
 247        s->txbuf = value;
 248        if (s->state & R_STATE_TXFULL_MASK) {
 249            /* Buffer already full -- note the overrun and let the
 250             * existing pending transmit callback handle the new char.
 251             */
 252            s->state |= R_STATE_TXOVERRUN_MASK;
 253            cmsdk_apb_uart_update(s);
 254        } else {
 255            s->state |= R_STATE_TXFULL_MASK;
 256            uart_transmit(NULL, G_IO_OUT, s);
 257        }
 258        break;
 259    case A_STATE:
 260        /* Bits 0 and 1 are read only; bits 2 and 3 are W1C */
 261        s->state &= ~(value &
 262                      (R_STATE_TXOVERRUN_MASK | R_STATE_RXOVERRUN_MASK));
 263        cmsdk_apb_uart_update(s);
 264        break;
 265    case A_CTRL:
 266        s->ctrl = value & 0x7f;
 267        if ((s->ctrl & R_CTRL_TX_EN_MASK) && !uart_baudrate_ok(s)) {
 268            qemu_log_mask(LOG_GUEST_ERROR,
 269                          "CMSDK APB UART: Tx enabled with invalid baudrate\n");
 270        }
 271        cmsdk_apb_uart_update(s);
 272        break;
 273    case A_INTSTATUS:
 274        /* All bits are W1C. Clearing the overrun interrupt bits really
 275         * clears the overrun status bits in the STATE register (which
 276         * is then reflected into the intstatus value by the update function).
 277         */
 278        s->state &= ~(value & (R_INTSTATUS_TXO_MASK | R_INTSTATUS_RXO_MASK));
 279        s->intstatus &= ~value;
 280        cmsdk_apb_uart_update(s);
 281        break;
 282    case A_BAUDDIV:
 283        s->bauddiv = value & 0xFFFFF;
 284        uart_update_parameters(s);
 285        break;
 286    case A_PID4 ... A_CID3:
 287        qemu_log_mask(LOG_GUEST_ERROR,
 288                      "CMSDK APB UART write: write to RO offset 0x%x\n",
 289                      (int)offset);
 290        break;
 291    default:
 292        qemu_log_mask(LOG_GUEST_ERROR,
 293                      "CMSDK APB UART write: bad offset 0x%x\n", (int) offset);
 294        break;
 295    }
 296}
 297
 298static const MemoryRegionOps uart_ops = {
 299    .read = uart_read,
 300    .write = uart_write,
 301    .endianness = DEVICE_LITTLE_ENDIAN,
 302};
 303
 304static void cmsdk_apb_uart_reset(DeviceState *dev)
 305{
 306    CMSDKAPBUART *s = CMSDK_APB_UART(dev);
 307
 308    trace_cmsdk_apb_uart_reset();
 309    uart_cancel_transmit(s);
 310    s->state = 0;
 311    s->ctrl = 0;
 312    s->intstatus = 0;
 313    s->bauddiv = 0;
 314    s->txbuf = 0;
 315    s->rxbuf = 0;
 316}
 317
 318static void cmsdk_apb_uart_init(Object *obj)
 319{
 320    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 321    CMSDKAPBUART *s = CMSDK_APB_UART(obj);
 322
 323    memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
 324    sysbus_init_mmio(sbd, &s->iomem);
 325    sysbus_init_irq(sbd, &s->txint);
 326    sysbus_init_irq(sbd, &s->rxint);
 327    sysbus_init_irq(sbd, &s->txovrint);
 328    sysbus_init_irq(sbd, &s->rxovrint);
 329    sysbus_init_irq(sbd, &s->uartint);
 330}
 331
 332static void cmsdk_apb_uart_realize(DeviceState *dev, Error **errp)
 333{
 334    CMSDKAPBUART *s = CMSDK_APB_UART(dev);
 335
 336    if (s->pclk_frq == 0) {
 337        error_setg(errp, "CMSDK APB UART: pclk-frq property must be set");
 338        return;
 339    }
 340
 341    /* This UART has no flow control, so we do not need to register
 342     * an event handler to deal with CHR_EVENT_BREAK.
 343     */
 344    qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
 345                             NULL, NULL, s, NULL, true);
 346}
 347
 348static int cmsdk_apb_uart_post_load(void *opaque, int version_id)
 349{
 350    CMSDKAPBUART *s = CMSDK_APB_UART(opaque);
 351
 352    /* If we have a pending character, arrange to resend it. */
 353    if (s->state & R_STATE_TXFULL_MASK) {
 354        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 355                                             uart_transmit, s);
 356    }
 357    uart_update_parameters(s);
 358    return 0;
 359}
 360
 361static const VMStateDescription cmsdk_apb_uart_vmstate = {
 362    .name = "cmsdk-apb-uart",
 363    .version_id = 1,
 364    .minimum_version_id = 1,
 365    .post_load = cmsdk_apb_uart_post_load,
 366    .fields = (VMStateField[]) {
 367        VMSTATE_UINT32(state, CMSDKAPBUART),
 368        VMSTATE_UINT32(ctrl, CMSDKAPBUART),
 369        VMSTATE_UINT32(intstatus, CMSDKAPBUART),
 370        VMSTATE_UINT32(bauddiv, CMSDKAPBUART),
 371        VMSTATE_UINT8(txbuf, CMSDKAPBUART),
 372        VMSTATE_UINT8(rxbuf, CMSDKAPBUART),
 373        VMSTATE_END_OF_LIST()
 374    }
 375};
 376
 377static Property cmsdk_apb_uart_properties[] = {
 378    DEFINE_PROP_CHR("chardev", CMSDKAPBUART, chr),
 379    DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBUART, pclk_frq, 0),
 380    DEFINE_PROP_END_OF_LIST(),
 381};
 382
 383static void cmsdk_apb_uart_class_init(ObjectClass *klass, void *data)
 384{
 385    DeviceClass *dc = DEVICE_CLASS(klass);
 386
 387    dc->realize = cmsdk_apb_uart_realize;
 388    dc->vmsd = &cmsdk_apb_uart_vmstate;
 389    dc->reset = cmsdk_apb_uart_reset;
 390    dc->props = cmsdk_apb_uart_properties;
 391}
 392
 393static const TypeInfo cmsdk_apb_uart_info = {
 394    .name = TYPE_CMSDK_APB_UART,
 395    .parent = TYPE_SYS_BUS_DEVICE,
 396    .instance_size = sizeof(CMSDKAPBUART),
 397    .instance_init = cmsdk_apb_uart_init,
 398    .class_init = cmsdk_apb_uart_class_init,
 399};
 400
 401static void cmsdk_apb_uart_register_types(void)
 402{
 403    type_register_static(&cmsdk_apb_uart_info);
 404}
 405
 406type_init(cmsdk_apb_uart_register_types);
 407