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26#include "qemu/osdep.h"
27#include "hw/char/serial.h"
28#include "chardev/char-serial.h"
29#include "qapi/error.h"
30#include "qemu/timer.h"
31#include "qemu/error-report.h"
32#include "trace.h"
33
34
35
36#define UART_LCR_DLAB 0x80
37
38#define UART_IER_MSI 0x08
39#define UART_IER_RLSI 0x04
40#define UART_IER_THRI 0x02
41#define UART_IER_RDI 0x01
42
43#define UART_IIR_NO_INT 0x01
44#define UART_IIR_ID 0x06
45
46#define UART_IIR_MSI 0x00
47#define UART_IIR_THRI 0x02
48#define UART_IIR_RDI 0x04
49#define UART_IIR_RLSI 0x06
50#define UART_IIR_CTI 0x0C
51
52#define UART_IIR_FENF 0x80
53#define UART_IIR_FE 0xC0
54
55
56
57
58#define UART_MCR_LOOP 0x10
59#define UART_MCR_OUT2 0x08
60#define UART_MCR_OUT1 0x04
61#define UART_MCR_RTS 0x02
62#define UART_MCR_DTR 0x01
63
64
65
66
67#define UART_MSR_DCD 0x80
68#define UART_MSR_RI 0x40
69#define UART_MSR_DSR 0x20
70#define UART_MSR_CTS 0x10
71#define UART_MSR_DDCD 0x08
72#define UART_MSR_TERI 0x04
73#define UART_MSR_DDSR 0x02
74#define UART_MSR_DCTS 0x01
75#define UART_MSR_ANY_DELTA 0x0F
76
77#define UART_LSR_TEMT 0x40
78#define UART_LSR_THRE 0x20
79#define UART_LSR_BI 0x10
80#define UART_LSR_FE 0x08
81#define UART_LSR_PE 0x04
82#define UART_LSR_OE 0x02
83#define UART_LSR_DR 0x01
84#define UART_LSR_INT_ANY 0x1E
85
86
87
88#define UART_FCR_ITL_1 0x00
89#define UART_FCR_ITL_2 0x40
90#define UART_FCR_ITL_3 0x80
91#define UART_FCR_ITL_4 0xC0
92
93#define UART_FCR_DMS 0x08
94#define UART_FCR_XFR 0x04
95#define UART_FCR_RFR 0x02
96#define UART_FCR_FE 0x01
97
98#define MAX_XMIT_RETRY 4
99
100#ifdef DEBUG_SERIAL
101#define DPRINTF(fmt, ...) \
102do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
103#else
104#define DPRINTF(fmt, ...) \
105do {} while (0)
106#endif
107
108static void serial_receive1(void *opaque, const uint8_t *buf, int size);
109static void serial_xmit(SerialState *s);
110
111static inline void recv_fifo_put(SerialState *s, uint8_t chr)
112{
113
114 if (!fifo8_is_full(&s->recv_fifo)) {
115 fifo8_push(&s->recv_fifo, chr);
116 } else {
117 s->lsr |= UART_LSR_OE;
118 }
119}
120
121static void serial_update_irq(SerialState *s)
122{
123 uint8_t tmp_iir = UART_IIR_NO_INT;
124
125 if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
126 tmp_iir = UART_IIR_RLSI;
127 } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
128
129
130
131 tmp_iir = UART_IIR_CTI;
132 } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
133 (!(s->fcr & UART_FCR_FE) ||
134 s->recv_fifo.num >= s->recv_fifo_itl)) {
135 tmp_iir = UART_IIR_RDI;
136 } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
137 tmp_iir = UART_IIR_THRI;
138 } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
139 tmp_iir = UART_IIR_MSI;
140 }
141
142 s->iir = tmp_iir | (s->iir & 0xF0);
143
144 if (tmp_iir != UART_IIR_NO_INT) {
145 qemu_irq_raise(s->irq);
146 } else {
147 qemu_irq_lower(s->irq);
148 }
149}
150
151static void serial_update_parameters(SerialState *s)
152{
153 float speed;
154 int parity, data_bits, stop_bits, frame_size;
155 QEMUSerialSetParams ssp;
156
157
158 frame_size = 1;
159 if (s->lcr & 0x08) {
160
161 frame_size++;
162 if (s->lcr & 0x10)
163 parity = 'E';
164 else
165 parity = 'O';
166 } else {
167 parity = 'N';
168 }
169 if (s->lcr & 0x04) {
170 stop_bits = 2;
171 } else {
172 stop_bits = 1;
173 }
174
175 data_bits = (s->lcr & 0x03) + 5;
176 frame_size += data_bits + stop_bits;
177
178 speed = (s->divider == 0) ? 3500 : (float) s->baudbase / s->divider;
179 ssp.speed = speed;
180 ssp.parity = parity;
181 ssp.data_bits = data_bits;
182 ssp.stop_bits = stop_bits;
183 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size;
184 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
185
186 DPRINTF("speed=%.2f parity=%c data=%d stop=%d\n",
187 speed, parity, data_bits, stop_bits);
188}
189
190static void serial_update_msl(SerialState *s)
191{
192 uint8_t omsr;
193 int flags;
194
195 timer_del(s->modem_status_poll);
196
197 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM,
198 &flags) == -ENOTSUP) {
199 s->poll_msl = -1;
200 return;
201 }
202
203 omsr = s->msr;
204
205 s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
206 s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
207 s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
208 s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
209
210 if (s->msr != omsr) {
211
212 s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
213
214 if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
215 s->msr &= ~UART_MSR_TERI;
216 serial_update_irq(s);
217 }
218
219
220
221
222 if (s->poll_msl) {
223 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
224 NANOSECONDS_PER_SECOND / 100);
225 }
226}
227
228static gboolean serial_watch_cb(GIOChannel *chan, GIOCondition cond,
229 void *opaque)
230{
231 SerialState *s = opaque;
232 s->watch_tag = 0;
233 serial_xmit(s);
234 return FALSE;
235}
236
237static void serial_xmit(SerialState *s)
238{
239 do {
240 assert(!(s->lsr & UART_LSR_TEMT));
241 if (s->tsr_retry == 0) {
242 assert(!(s->lsr & UART_LSR_THRE));
243
244 if (s->fcr & UART_FCR_FE) {
245 assert(!fifo8_is_empty(&s->xmit_fifo));
246 s->tsr = fifo8_pop(&s->xmit_fifo);
247 if (!s->xmit_fifo.num) {
248 s->lsr |= UART_LSR_THRE;
249 }
250 } else {
251 s->tsr = s->thr;
252 s->lsr |= UART_LSR_THRE;
253 }
254 if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) {
255 s->thr_ipending = 1;
256 serial_update_irq(s);
257 }
258 }
259
260 if (s->mcr & UART_MCR_LOOP) {
261
262 serial_receive1(s, &s->tsr, 1);
263 } else {
264 int rc = qemu_chr_fe_write(&s->chr, &s->tsr, 1);
265
266 if ((rc == 0 ||
267 (rc == -1 && errno == EAGAIN)) &&
268 s->tsr_retry < MAX_XMIT_RETRY) {
269 assert(s->watch_tag == 0);
270 s->watch_tag =
271 qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
272 serial_watch_cb, s);
273 if (s->watch_tag > 0) {
274 s->tsr_retry++;
275 return;
276 }
277 }
278 }
279 s->tsr_retry = 0;
280
281
282
283 } while (!(s->lsr & UART_LSR_THRE));
284
285 s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
286 s->lsr |= UART_LSR_TEMT;
287}
288
289
290
291
292static void serial_write_fcr(SerialState *s, uint8_t val)
293{
294
295 s->fcr = val;
296
297 if (val & UART_FCR_FE) {
298 s->iir |= UART_IIR_FE;
299
300 switch (val & 0xC0) {
301 case UART_FCR_ITL_1:
302 s->recv_fifo_itl = 1;
303 break;
304 case UART_FCR_ITL_2:
305 s->recv_fifo_itl = 4;
306 break;
307 case UART_FCR_ITL_3:
308 s->recv_fifo_itl = 8;
309 break;
310 case UART_FCR_ITL_4:
311 s->recv_fifo_itl = 14;
312 break;
313 }
314 } else {
315 s->iir &= ~UART_IIR_FE;
316 }
317}
318
319static void serial_update_tiocm(SerialState *s)
320{
321 int flags;
322
323 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
324
325 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
326
327 if (s->mcr & UART_MCR_RTS) {
328 flags |= CHR_TIOCM_RTS;
329 }
330 if (s->mcr & UART_MCR_DTR) {
331 flags |= CHR_TIOCM_DTR;
332 }
333
334 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
335}
336
337static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
338 unsigned size)
339{
340 SerialState *s = opaque;
341
342 addr &= 7;
343 trace_serial_ioport_write(addr, val);
344 switch(addr) {
345 default:
346 case 0:
347 if (s->lcr & UART_LCR_DLAB) {
348 if (size == 1) {
349 s->divider = (s->divider & 0xff00) | val;
350 } else {
351 s->divider = val;
352 }
353 serial_update_parameters(s);
354 } else {
355 s->thr = (uint8_t) val;
356 if(s->fcr & UART_FCR_FE) {
357
358 if (fifo8_is_full(&s->xmit_fifo)) {
359 fifo8_pop(&s->xmit_fifo);
360 }
361 fifo8_push(&s->xmit_fifo, s->thr);
362 }
363 s->thr_ipending = 0;
364 s->lsr &= ~UART_LSR_THRE;
365 s->lsr &= ~UART_LSR_TEMT;
366 serial_update_irq(s);
367 if (s->tsr_retry == 0) {
368 serial_xmit(s);
369 }
370 }
371 break;
372 case 1:
373 if (s->lcr & UART_LCR_DLAB) {
374 s->divider = (s->divider & 0x00ff) | (val << 8);
375 serial_update_parameters(s);
376 } else {
377 uint8_t changed = (s->ier ^ val) & 0x0f;
378 s->ier = val & 0x0f;
379
380
381
382 if ((changed & UART_IER_MSI) && s->poll_msl >= 0) {
383 if (s->ier & UART_IER_MSI) {
384 s->poll_msl = 1;
385 serial_update_msl(s);
386 } else {
387 timer_del(s->modem_status_poll);
388 s->poll_msl = 0;
389 }
390 }
391
392
393
394
395
396
397
398
399
400
401
402
403 if (changed & UART_IER_THRI) {
404 if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) {
405 s->thr_ipending = 1;
406 } else {
407 s->thr_ipending = 0;
408 }
409 }
410
411 if (changed) {
412 serial_update_irq(s);
413 }
414 }
415 break;
416 case 2:
417
418 if ((val ^ s->fcr) & UART_FCR_FE) {
419 val |= UART_FCR_XFR | UART_FCR_RFR;
420 }
421
422
423
424 if (val & UART_FCR_RFR) {
425 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
426 timer_del(s->fifo_timeout_timer);
427 s->timeout_ipending = 0;
428 fifo8_reset(&s->recv_fifo);
429 }
430
431 if (val & UART_FCR_XFR) {
432 s->lsr |= UART_LSR_THRE;
433 s->thr_ipending = 1;
434 fifo8_reset(&s->xmit_fifo);
435 }
436
437 serial_write_fcr(s, val & 0xC9);
438 serial_update_irq(s);
439 break;
440 case 3:
441 {
442 int break_enable;
443 s->lcr = val;
444 serial_update_parameters(s);
445 break_enable = (val >> 6) & 1;
446 if (break_enable != s->last_break_enable) {
447 s->last_break_enable = break_enable;
448 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
449 &break_enable);
450 }
451 }
452 break;
453 case 4:
454 {
455 int old_mcr = s->mcr;
456 s->mcr = val & 0x1f;
457 if (val & UART_MCR_LOOP)
458 break;
459
460 if (s->poll_msl >= 0 && old_mcr != s->mcr) {
461 serial_update_tiocm(s);
462
463
464 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
465 }
466 }
467 break;
468 case 5:
469 break;
470 case 6:
471 break;
472 case 7:
473 s->scr = val;
474 break;
475 }
476}
477
478static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
479{
480 SerialState *s = opaque;
481 uint32_t ret;
482
483 addr &= 7;
484 switch(addr) {
485 default:
486 case 0:
487 if (s->lcr & UART_LCR_DLAB) {
488 ret = s->divider & 0xff;
489 } else {
490 if(s->fcr & UART_FCR_FE) {
491 ret = fifo8_is_empty(&s->recv_fifo) ?
492 0 : fifo8_pop(&s->recv_fifo);
493 if (s->recv_fifo.num == 0) {
494 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
495 } else {
496 timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
497 }
498 s->timeout_ipending = 0;
499 } else {
500 ret = s->rbr;
501 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
502 }
503 serial_update_irq(s);
504 if (!(s->mcr & UART_MCR_LOOP)) {
505
506 qemu_chr_fe_accept_input(&s->chr);
507 }
508 }
509 break;
510 case 1:
511 if (s->lcr & UART_LCR_DLAB) {
512 ret = (s->divider >> 8) & 0xff;
513 } else {
514 ret = s->ier;
515 }
516 break;
517 case 2:
518 ret = s->iir;
519 if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
520 s->thr_ipending = 0;
521 serial_update_irq(s);
522 }
523 break;
524 case 3:
525 ret = s->lcr;
526 break;
527 case 4:
528 ret = s->mcr;
529 break;
530 case 5:
531 ret = s->lsr;
532
533 if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
534 s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
535 serial_update_irq(s);
536 }
537 break;
538 case 6:
539 if (s->mcr & UART_MCR_LOOP) {
540
541
542 ret = (s->mcr & 0x0c) << 4;
543 ret |= (s->mcr & 0x02) << 3;
544 ret |= (s->mcr & 0x01) << 5;
545 } else {
546 if (s->poll_msl >= 0)
547 serial_update_msl(s);
548 ret = s->msr;
549
550 if (s->msr & UART_MSR_ANY_DELTA) {
551 s->msr &= 0xF0;
552 serial_update_irq(s);
553 }
554 }
555 break;
556 case 7:
557 ret = s->scr;
558 break;
559 }
560 trace_serial_ioport_read(addr, ret);
561 return ret;
562}
563
564static int serial_can_receive(SerialState *s)
565{
566 if(s->fcr & UART_FCR_FE) {
567 if (s->recv_fifo.num < UART_FIFO_LENGTH) {
568
569
570
571
572
573
574
575 return (s->recv_fifo.num <= s->recv_fifo_itl) ?
576 s->recv_fifo_itl - s->recv_fifo.num : 1;
577 } else {
578 return 0;
579 }
580 } else {
581 return !(s->lsr & UART_LSR_DR);
582 }
583}
584
585static void serial_receive_break(SerialState *s)
586{
587 s->rbr = 0;
588
589 recv_fifo_put(s, '\0');
590 s->lsr |= UART_LSR_BI | UART_LSR_DR;
591 serial_update_irq(s);
592}
593
594
595static void fifo_timeout_int (void *opaque) {
596 SerialState *s = opaque;
597 if (s->recv_fifo.num) {
598 s->timeout_ipending = 1;
599 serial_update_irq(s);
600 }
601}
602
603static int serial_can_receive1(void *opaque)
604{
605 SerialState *s = opaque;
606 return serial_can_receive(s);
607}
608
609static void serial_receive1(void *opaque, const uint8_t *buf, int size)
610{
611 SerialState *s = opaque;
612
613 if (s->wakeup) {
614 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER, NULL);
615 }
616 if(s->fcr & UART_FCR_FE) {
617 int i;
618 for (i = 0; i < size; i++) {
619 recv_fifo_put(s, buf[i]);
620 }
621 s->lsr |= UART_LSR_DR;
622
623 timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
624 } else {
625 if (s->lsr & UART_LSR_DR)
626 s->lsr |= UART_LSR_OE;
627 s->rbr = buf[0];
628 s->lsr |= UART_LSR_DR;
629 }
630 serial_update_irq(s);
631}
632
633static void serial_event(void *opaque, int event)
634{
635 SerialState *s = opaque;
636 DPRINTF("event %x\n", event);
637 if (event == CHR_EVENT_BREAK)
638 serial_receive_break(s);
639}
640
641static int serial_pre_save(void *opaque)
642{
643 SerialState *s = opaque;
644 s->fcr_vmstate = s->fcr;
645
646 return 0;
647}
648
649static int serial_pre_load(void *opaque)
650{
651 SerialState *s = opaque;
652 s->thr_ipending = -1;
653 s->poll_msl = -1;
654 return 0;
655}
656
657static int serial_post_load(void *opaque, int version_id)
658{
659 SerialState *s = opaque;
660
661 if (version_id < 3) {
662 s->fcr_vmstate = 0;
663 }
664 if (s->thr_ipending == -1) {
665 s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
666 }
667
668 if (s->tsr_retry > 0) {
669
670 if (s->lsr & UART_LSR_TEMT) {
671 error_report("inconsistent state in serial device "
672 "(tsr empty, tsr_retry=%d", s->tsr_retry);
673 return -1;
674 }
675
676 if (s->tsr_retry > MAX_XMIT_RETRY) {
677 s->tsr_retry = MAX_XMIT_RETRY;
678 }
679
680 assert(s->watch_tag == 0);
681 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
682 serial_watch_cb, s);
683 } else {
684
685 if (!(s->lsr & UART_LSR_TEMT)) {
686 error_report("inconsistent state in serial device "
687 "(tsr not empty, tsr_retry=0");
688 return -1;
689 }
690 }
691
692 s->last_break_enable = (s->lcr >> 6) & 1;
693
694 serial_write_fcr(s, s->fcr_vmstate);
695 serial_update_parameters(s);
696 return 0;
697}
698
699static bool serial_thr_ipending_needed(void *opaque)
700{
701 SerialState *s = opaque;
702
703 if (s->ier & UART_IER_THRI) {
704 bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
705 return s->thr_ipending != expected_value;
706 } else {
707
708
709
710
711 return false;
712 }
713}
714
715static const VMStateDescription vmstate_serial_thr_ipending = {
716 .name = "serial/thr_ipending",
717 .version_id = 1,
718 .minimum_version_id = 1,
719 .needed = serial_thr_ipending_needed,
720 .fields = (VMStateField[]) {
721 VMSTATE_INT32(thr_ipending, SerialState),
722 VMSTATE_END_OF_LIST()
723 }
724};
725
726static bool serial_tsr_needed(void *opaque)
727{
728 SerialState *s = (SerialState *)opaque;
729 return s->tsr_retry != 0;
730}
731
732static const VMStateDescription vmstate_serial_tsr = {
733 .name = "serial/tsr",
734 .version_id = 1,
735 .minimum_version_id = 1,
736 .needed = serial_tsr_needed,
737 .fields = (VMStateField[]) {
738 VMSTATE_UINT32(tsr_retry, SerialState),
739 VMSTATE_UINT8(thr, SerialState),
740 VMSTATE_UINT8(tsr, SerialState),
741 VMSTATE_END_OF_LIST()
742 }
743};
744
745static bool serial_recv_fifo_needed(void *opaque)
746{
747 SerialState *s = (SerialState *)opaque;
748 return !fifo8_is_empty(&s->recv_fifo);
749
750}
751
752static const VMStateDescription vmstate_serial_recv_fifo = {
753 .name = "serial/recv_fifo",
754 .version_id = 1,
755 .minimum_version_id = 1,
756 .needed = serial_recv_fifo_needed,
757 .fields = (VMStateField[]) {
758 VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
759 VMSTATE_END_OF_LIST()
760 }
761};
762
763static bool serial_xmit_fifo_needed(void *opaque)
764{
765 SerialState *s = (SerialState *)opaque;
766 return !fifo8_is_empty(&s->xmit_fifo);
767}
768
769static const VMStateDescription vmstate_serial_xmit_fifo = {
770 .name = "serial/xmit_fifo",
771 .version_id = 1,
772 .minimum_version_id = 1,
773 .needed = serial_xmit_fifo_needed,
774 .fields = (VMStateField[]) {
775 VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
776 VMSTATE_END_OF_LIST()
777 }
778};
779
780static bool serial_fifo_timeout_timer_needed(void *opaque)
781{
782 SerialState *s = (SerialState *)opaque;
783 return timer_pending(s->fifo_timeout_timer);
784}
785
786static const VMStateDescription vmstate_serial_fifo_timeout_timer = {
787 .name = "serial/fifo_timeout_timer",
788 .version_id = 1,
789 .minimum_version_id = 1,
790 .needed = serial_fifo_timeout_timer_needed,
791 .fields = (VMStateField[]) {
792 VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState),
793 VMSTATE_END_OF_LIST()
794 }
795};
796
797static bool serial_timeout_ipending_needed(void *opaque)
798{
799 SerialState *s = (SerialState *)opaque;
800 return s->timeout_ipending != 0;
801}
802
803static const VMStateDescription vmstate_serial_timeout_ipending = {
804 .name = "serial/timeout_ipending",
805 .version_id = 1,
806 .minimum_version_id = 1,
807 .needed = serial_timeout_ipending_needed,
808 .fields = (VMStateField[]) {
809 VMSTATE_INT32(timeout_ipending, SerialState),
810 VMSTATE_END_OF_LIST()
811 }
812};
813
814static bool serial_poll_needed(void *opaque)
815{
816 SerialState *s = (SerialState *)opaque;
817 return s->poll_msl >= 0;
818}
819
820static const VMStateDescription vmstate_serial_poll = {
821 .name = "serial/poll",
822 .version_id = 1,
823 .needed = serial_poll_needed,
824 .minimum_version_id = 1,
825 .fields = (VMStateField[]) {
826 VMSTATE_INT32(poll_msl, SerialState),
827 VMSTATE_TIMER_PTR(modem_status_poll, SerialState),
828 VMSTATE_END_OF_LIST()
829 }
830};
831
832const VMStateDescription vmstate_serial = {
833 .name = "serial",
834 .version_id = 3,
835 .minimum_version_id = 2,
836 .pre_save = serial_pre_save,
837 .pre_load = serial_pre_load,
838 .post_load = serial_post_load,
839 .fields = (VMStateField[]) {
840 VMSTATE_UINT16_V(divider, SerialState, 2),
841 VMSTATE_UINT8(rbr, SerialState),
842 VMSTATE_UINT8(ier, SerialState),
843 VMSTATE_UINT8(iir, SerialState),
844 VMSTATE_UINT8(lcr, SerialState),
845 VMSTATE_UINT8(mcr, SerialState),
846 VMSTATE_UINT8(lsr, SerialState),
847 VMSTATE_UINT8(msr, SerialState),
848 VMSTATE_UINT8(scr, SerialState),
849 VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
850 VMSTATE_END_OF_LIST()
851 },
852 .subsections = (const VMStateDescription*[]) {
853 &vmstate_serial_thr_ipending,
854 &vmstate_serial_tsr,
855 &vmstate_serial_recv_fifo,
856 &vmstate_serial_xmit_fifo,
857 &vmstate_serial_fifo_timeout_timer,
858 &vmstate_serial_timeout_ipending,
859 &vmstate_serial_poll,
860 NULL
861 }
862};
863
864static void serial_reset(void *opaque)
865{
866 SerialState *s = opaque;
867
868 if (s->watch_tag > 0) {
869 g_source_remove(s->watch_tag);
870 s->watch_tag = 0;
871 }
872
873 s->rbr = 0;
874 s->ier = 0;
875 s->iir = UART_IIR_NO_INT;
876 s->lcr = 0;
877 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
878 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
879
880 s->divider = 0x0C;
881 s->mcr = UART_MCR_OUT2;
882 s->scr = 0;
883 s->tsr_retry = 0;
884 s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
885 s->poll_msl = 0;
886
887 s->timeout_ipending = 0;
888 timer_del(s->fifo_timeout_timer);
889 timer_del(s->modem_status_poll);
890
891 fifo8_reset(&s->recv_fifo);
892 fifo8_reset(&s->xmit_fifo);
893
894 s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
895
896 s->thr_ipending = 0;
897 s->last_break_enable = 0;
898 qemu_irq_lower(s->irq);
899
900 serial_update_msl(s);
901 s->msr &= ~UART_MSR_ANY_DELTA;
902}
903
904static int serial_be_change(void *opaque)
905{
906 SerialState *s = opaque;
907
908 qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
909 serial_event, serial_be_change, s, NULL, true);
910
911 serial_update_parameters(s);
912
913 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
914 &s->last_break_enable);
915
916 s->poll_msl = (s->ier & UART_IER_MSI) ? 1 : 0;
917 serial_update_msl(s);
918
919 if (s->poll_msl >= 0 && !(s->mcr & UART_MCR_LOOP)) {
920 serial_update_tiocm(s);
921 }
922
923 if (s->watch_tag > 0) {
924 g_source_remove(s->watch_tag);
925 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
926 serial_watch_cb, s);
927 }
928
929 return 0;
930}
931
932void serial_realize_core(SerialState *s, Error **errp)
933{
934 s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
935
936 s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
937 qemu_register_reset(serial_reset, s);
938
939 qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
940 serial_event, serial_be_change, s, NULL, true);
941 fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
942 fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
943 serial_reset(s);
944}
945
946void serial_exit_core(SerialState *s)
947{
948 qemu_chr_fe_deinit(&s->chr, false);
949
950 timer_del(s->modem_status_poll);
951 timer_free(s->modem_status_poll);
952
953 timer_del(s->fifo_timeout_timer);
954 timer_free(s->fifo_timeout_timer);
955
956 fifo8_destroy(&s->recv_fifo);
957 fifo8_destroy(&s->xmit_fifo);
958
959 qemu_unregister_reset(serial_reset, s);
960}
961
962
963void serial_set_frequency(SerialState *s, uint32_t frequency)
964{
965 s->baudbase = frequency;
966 serial_update_parameters(s);
967}
968
969const MemoryRegionOps serial_io_ops = {
970 .read = serial_ioport_read,
971 .write = serial_ioport_write,
972 .impl = {
973 .min_access_size = 1,
974 .max_access_size = 1,
975 },
976 .endianness = DEVICE_LITTLE_ENDIAN,
977};
978
979SerialState *serial_init(int base, qemu_irq irq, int baudbase,
980 Chardev *chr, MemoryRegion *system_io)
981{
982 SerialState *s;
983
984 s = g_malloc0(sizeof(SerialState));
985
986 s->irq = irq;
987 s->baudbase = baudbase;
988 qemu_chr_fe_init(&s->chr, chr, &error_abort);
989 serial_realize_core(s, &error_fatal);
990
991 vmstate_register(NULL, base, &vmstate_serial, s);
992
993 memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
994 memory_region_add_subregion(system_io, base, &s->io);
995
996 return s;
997}
998
999
1000static uint64_t serial_mm_read(void *opaque, hwaddr addr,
1001 unsigned size)
1002{
1003 SerialState *s = opaque;
1004 return serial_ioport_read(s, addr >> s->it_shift, 1);
1005}
1006
1007static void serial_mm_write(void *opaque, hwaddr addr,
1008 uint64_t value, unsigned size)
1009{
1010 SerialState *s = opaque;
1011 value &= 255;
1012 serial_ioport_write(s, addr >> s->it_shift, value, 1);
1013}
1014
1015static const MemoryRegionOps serial_mm_ops[3] = {
1016 [DEVICE_NATIVE_ENDIAN] = {
1017 .read = serial_mm_read,
1018 .write = serial_mm_write,
1019 .endianness = DEVICE_NATIVE_ENDIAN,
1020 .valid.max_access_size = 8,
1021 .impl.max_access_size = 8,
1022 },
1023 [DEVICE_LITTLE_ENDIAN] = {
1024 .read = serial_mm_read,
1025 .write = serial_mm_write,
1026 .endianness = DEVICE_LITTLE_ENDIAN,
1027 .valid.max_access_size = 8,
1028 .impl.max_access_size = 8,
1029 },
1030 [DEVICE_BIG_ENDIAN] = {
1031 .read = serial_mm_read,
1032 .write = serial_mm_write,
1033 .endianness = DEVICE_BIG_ENDIAN,
1034 .valid.max_access_size = 8,
1035 .impl.max_access_size = 8,
1036 },
1037};
1038
1039SerialState *serial_mm_init(MemoryRegion *address_space,
1040 hwaddr base, int it_shift,
1041 qemu_irq irq, int baudbase,
1042 Chardev *chr, enum device_endian end)
1043{
1044 SerialState *s;
1045
1046 s = g_malloc0(sizeof(SerialState));
1047
1048 s->it_shift = it_shift;
1049 s->irq = irq;
1050 s->baudbase = baudbase;
1051 qemu_chr_fe_init(&s->chr, chr, &error_abort);
1052
1053 serial_realize_core(s, &error_fatal);
1054 vmstate_register(NULL, base, &vmstate_serial, s);
1055
1056 memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
1057 "serial", 8 << it_shift);
1058 memory_region_add_subregion(address_space, base, &s->io);
1059 return s;
1060}
1061