LXR qemu/hw/cpu/a9mpcore.c

   1/*
   2 * Cortex-A9MPCore internal peripheral emulation.
   3 *
   4 * Copyright (c) 2009 CodeSourcery.
   5 * Copyright (c) 2011 Linaro Limited.
   6 * Written by Paul Brook, Peter Maydell.
   7 *
   8 * This code is licensed under the GPL.
   9 */
  10
  11#include "qemu/osdep.h"
  12#include "qapi/error.h"
  13#include "qemu/module.h"
  14#include "hw/cpu/a9mpcore.h"
  15#include "qom/cpu.h"
  16
  17static void a9mp_priv_set_irq(void *opaque, int irq, int level)
  18{
  19    A9MPPrivState *s = (A9MPPrivState *)opaque;
  20
  21    qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  22}
  23
  24static void a9mp_priv_initfn(Object *obj)
  25{
  26    A9MPPrivState *s = A9MPCORE_PRIV(obj);
  27
  28    memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
  29    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
  30
  31    sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_A9_SCU);
  32
  33    sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC);
  34
  35    sysbus_init_child_obj(obj, "gtimer", &s->gtimer, sizeof(s->gtimer),
  36                          TYPE_A9_GTIMER);
  37
  38    sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer),
  39                          TYPE_ARM_MPTIMER);
  40
  41    sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt),
  42                          TYPE_ARM_MPTIMER);
  43}
  44
  45static void a9mp_priv_realize(DeviceState *dev, Error **errp)
  46{
  47    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  48    A9MPPrivState *s = A9MPCORE_PRIV(dev);
  49    DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev;
  50    SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev,
  51                 *wdtbusdev;
  52    Error *err = NULL;
  53    int i;
  54    bool has_el3;
  55    Object *cpuobj;
  56
  57    scudev = DEVICE(&s->scu);
  58    qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
  59    object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
  60    if (err != NULL) {
  61        error_propagate(errp, err);
  62        return;
  63    }
  64    scubusdev = SYS_BUS_DEVICE(&s->scu);
  65
  66    gicdev = DEVICE(&s->gic);
  67    qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  68    qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  69
  70    /* Make the GIC's TZ support match the CPUs. We assume that
  71     * either all the CPUs have TZ, or none do.
  72     */
  73    cpuobj = OBJECT(qemu_get_cpu(0));
  74    has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
  75        object_property_get_bool(cpuobj, "has_el3", &error_abort);
  76    qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
  77
  78    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  79    if (err != NULL) {
  80        error_propagate(errp, err);
  81        return;
  82    }
  83    gicbusdev = SYS_BUS_DEVICE(&s->gic);
  84
  85    /* Pass through outbound IRQ lines from the GIC */
  86    sysbus_pass_irq(sbd, gicbusdev);
  87
  88    /* Pass through inbound GPIO lines to the GIC */
  89    qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
  90
  91    gtimerdev = DEVICE(&s->gtimer);
  92    qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
  93    object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err);
  94    if (err != NULL) {
  95        error_propagate(errp, err);
  96        return;
  97    }
  98    gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer);
  99
 100    mptimerdev = DEVICE(&s->mptimer);
 101    qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
 102    object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
 103    if (err != NULL) {
 104        error_propagate(errp, err);
 105        return;
 106    }
 107    mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer);
 108
 109    wdtdev = DEVICE(&s->wdt);
 110    qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu);
 111    object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
 112    if (err != NULL) {
 113        error_propagate(errp, err);
 114        return;
 115    }
 116    wdtbusdev = SYS_BUS_DEVICE(&s->wdt);
 117
 118    /* Memory map (addresses are offsets from PERIPHBASE):
 119     *  0x0000-0x00ff -- Snoop Control Unit
 120     *  0x0100-0x01ff -- GIC CPU interface
 121     *  0x0200-0x02ff -- Global Timer
 122     *  0x0300-0x05ff -- nothing
 123     *  0x0600-0x06ff -- private timers and watchdogs
 124     *  0x0700-0x0fff -- nothing
 125     *  0x1000-0x1fff -- GIC Distributor
 126     */
 127    memory_region_add_subregion(&s->container, 0,
 128                                sysbus_mmio_get_region(scubusdev, 0));
 129    /* GIC CPU interface */
 130    memory_region_add_subregion(&s->container, 0x100,
 131                                sysbus_mmio_get_region(gicbusdev, 1));
 132    memory_region_add_subregion(&s->container, 0x200,
 133                                sysbus_mmio_get_region(gtimerbusdev, 0));
 134    /* Note that the A9 exposes only the "timer/watchdog for this core"
 135     * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
 136     */
 137    memory_region_add_subregion(&s->container, 0x600,
 138                                sysbus_mmio_get_region(mptimerbusdev, 0));
 139    memory_region_add_subregion(&s->container, 0x620,
 140                                sysbus_mmio_get_region(wdtbusdev, 0));
 141    memory_region_add_subregion(&s->container, 0x1000,
 142                                sysbus_mmio_get_region(gicbusdev, 0));
 143
 144    /* Wire up the interrupt from each watchdog and timer.
 145     * For each core the global timer is PPI 27, the private
 146     * timer is PPI 29 and the watchdog PPI 30.
 147     */
 148    for (i = 0; i < s->num_cpu; i++) {
 149        int ppibase = (s->num_irq - 32) + i * 32;
 150        sysbus_connect_irq(gtimerbusdev, i,
 151                           qdev_get_gpio_in(gicdev, ppibase + 27));
 152        sysbus_connect_irq(mptimerbusdev, i,
 153                           qdev_get_gpio_in(gicdev, ppibase + 29));
 154        sysbus_connect_irq(wdtbusdev, i,
 155                           qdev_get_gpio_in(gicdev, ppibase + 30));
 156    }
 157}
 158
 159static Property a9mp_priv_properties[] = {
 160    DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
 161    /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
 162     * IRQ lines (with another 32 internal). We default to 64+32, which
 163     * is the number provided by the Cortex-A9MP test chip in the
 164     * Realview PBX-A9 and Versatile Express A9 development boards.
 165     * Other boards may differ and should set this property appropriately.
 166     */
 167    DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
 168    DEFINE_PROP_END_OF_LIST(),
 169};
 170
 171static void a9mp_priv_class_init(ObjectClass *klass, void *data)
 172{
 173    DeviceClass *dc = DEVICE_CLASS(klass);
 174
 175    dc->realize = a9mp_priv_realize;
 176    dc->props = a9mp_priv_properties;
 177}
 178
 179static const TypeInfo a9mp_priv_info = {
 180    .name          = TYPE_A9MPCORE_PRIV,
 181    .parent        = TYPE_SYS_BUS_DEVICE,
 182    .instance_size = sizeof(A9MPPrivState),
 183    .instance_init = a9mp_priv_initfn,
 184    .class_init    = a9mp_priv_class_init,
 185};
 186
 187static void a9mp_register_types(void)
 188{
 189    type_register_static(&a9mp_priv_info);
 190}
 191
 192type_init(a9mp_register_types)
 193