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25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qapi/error.h"
28#include "cpu.h"
29#include "hw/sysbus.h"
30#include "net/net.h"
31#include "hw/block/flash.h"
32#include "hw/boards.h"
33#include "hw/cris/etraxfs.h"
34#include "hw/loader.h"
35#include "elf.h"
36#include "boot.h"
37#include "exec/address-spaces.h"
38#include "sysemu/qtest.h"
39#include "sysemu/sysemu.h"
40
41#define D(x)
42#define DNAND(x)
43
44struct nand_state_t
45{
46 DeviceState *nand;
47 MemoryRegion iomem;
48 unsigned int rdy:1;
49 unsigned int ale:1;
50 unsigned int cle:1;
51 unsigned int ce:1;
52};
53
54static struct nand_state_t nand_state;
55static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
56{
57 struct nand_state_t *s = opaque;
58 uint32_t r;
59 int rdy;
60
61 r = nand_getio(s->nand);
62 nand_getpins(s->nand, &rdy);
63 s->rdy = rdy;
64
65 DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
66 return r;
67}
68
69static void
70nand_write(void *opaque, hwaddr addr, uint64_t value,
71 unsigned size)
72{
73 struct nand_state_t *s = opaque;
74 int rdy;
75
76 DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
77 nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
78 nand_setio(s->nand, value);
79 nand_getpins(s->nand, &rdy);
80 s->rdy = rdy;
81}
82
83static const MemoryRegionOps nand_ops = {
84 .read = nand_read,
85 .write = nand_write,
86 .endianness = DEVICE_NATIVE_ENDIAN,
87};
88
89struct tempsensor_t
90{
91 unsigned int shiftreg;
92 unsigned int count;
93 enum {
94 ST_OUT, ST_IN, ST_Z
95 } state;
96
97 uint16_t regs[3];
98};
99
100static void tempsensor_clkedge(struct tempsensor_t *s,
101 unsigned int clk, unsigned int data_in)
102{
103 D(printf("%s clk=%d state=%d sr=%x\n", __func__,
104 clk, s->state, s->shiftreg));
105 if (s->count == 0) {
106 s->count = 16;
107 s->state = ST_OUT;
108 }
109 switch (s->state) {
110 case ST_OUT:
111
112 if (!clk) {
113 s->count--;
114 s->shiftreg <<= 1;
115 if (s->count == 0) {
116 s->shiftreg = 0;
117 s->state = ST_IN;
118 s->count = 16;
119 }
120 }
121 break;
122 case ST_Z:
123 if (clk) {
124 s->count--;
125 if (s->count == 0) {
126 s->shiftreg = 0;
127 s->state = ST_OUT;
128 s->count = 16;
129 }
130 }
131 break;
132 case ST_IN:
133
134 if (clk) {
135 s->count--;
136 s->shiftreg <<= 1;
137 s->shiftreg |= data_in & 1;
138 if (s->count == 0) {
139 D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
140 s->regs[0] = s->shiftreg;
141 s->state = ST_OUT;
142 s->count = 16;
143
144 if ((s->regs[0] & 0xff) == 0) {
145
146 s->shiftreg = 0x0b9f;
147 } else if ((s->regs[0] & 0xff) == 0xff) {
148
149 s->shiftreg = 0x8100;
150 } else
151 printf("Invalid tempsens state %x\n", s->regs[0]);
152 }
153 }
154 break;
155 }
156}
157
158
159#define RW_PA_DOUT 0x00
160#define R_PA_DIN 0x01
161#define RW_PA_OE 0x02
162#define RW_PD_DOUT 0x10
163#define R_PD_DIN 0x11
164#define RW_PD_OE 0x12
165
166static struct gpio_state_t
167{
168 MemoryRegion iomem;
169 struct nand_state_t *nand;
170 struct tempsensor_t tempsensor;
171 uint32_t regs[0x5c / 4];
172} gpio_state;
173
174static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
175{
176 struct gpio_state_t *s = opaque;
177 uint32_t r = 0;
178
179 addr >>= 2;
180 switch (addr)
181 {
182 case R_PA_DIN:
183 r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
184
185
186 r |= s->nand->rdy << 7;
187 break;
188 case R_PD_DIN:
189 r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
190
191
192 r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
193 break;
194
195 default:
196 r = s->regs[addr];
197 break;
198 }
199 return r;
200 D(printf("%s %x=%x\n", __func__, addr, r));
201}
202
203static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
204 unsigned size)
205{
206 struct gpio_state_t *s = opaque;
207 D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
208
209 addr >>= 2;
210 switch (addr)
211 {
212 case RW_PA_DOUT:
213
214 s->nand->ale = !!(value & (1 << 6));
215 s->nand->cle = !!(value & (1 << 5));
216 s->nand->ce = !!(value & (1 << 4));
217
218 s->regs[addr] = value;
219 break;
220
221 case RW_PD_DOUT:
222
223 if ((s->regs[addr] ^ value) & 2)
224 tempsensor_clkedge(&s->tempsensor, !!(value & 2),
225 !!(value & 16));
226 s->regs[addr] = value;
227 break;
228
229 default:
230 s->regs[addr] = value;
231 break;
232 }
233}
234
235static const MemoryRegionOps gpio_ops = {
236 .read = gpio_read,
237 .write = gpio_write,
238 .endianness = DEVICE_NATIVE_ENDIAN,
239 .valid = {
240 .min_access_size = 4,
241 .max_access_size = 4,
242 },
243};
244
245#define INTMEM_SIZE (128 * KiB)
246
247static struct cris_load_info li;
248
249static
250void axisdev88_init(MachineState *machine)
251{
252 ram_addr_t ram_size = machine->ram_size;
253 const char *kernel_filename = machine->kernel_filename;
254 const char *kernel_cmdline = machine->kernel_cmdline;
255 CRISCPU *cpu;
256 CPUCRISState *env;
257 DeviceState *dev;
258 SysBusDevice *s;
259 DriveInfo *nand;
260 qemu_irq irq[30], nmi[2];
261 void *etraxfs_dmac;
262 struct etraxfs_dma_client *dma_eth;
263 int i;
264 MemoryRegion *address_space_mem = get_system_memory();
265 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
266 MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
267
268
269 cpu = CRIS_CPU(cpu_create(machine->cpu_type));
270 env = &cpu->env;
271
272
273 memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram",
274 ram_size);
275 memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
276
277
278
279 memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram",
280 INTMEM_SIZE, &error_fatal);
281 memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
282
283
284 nand = drive_get(IF_MTD, 0, 0);
285 nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
286 NAND_MFR_STMICRO, 0x39);
287 memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
288 "nand", 0x05000000);
289 memory_region_add_subregion(address_space_mem, 0x10000000,
290 &nand_state.iomem);
291
292 gpio_state.nand = &nand_state;
293 memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
294 "gpio", 0x5c);
295 memory_region_add_subregion(address_space_mem, 0x3001a000,
296 &gpio_state.iomem);
297
298
299 dev = qdev_create(NULL, "etraxfs,pic");
300
301 qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
302 qdev_init_nofail(dev);
303 s = SYS_BUS_DEVICE(dev);
304 sysbus_mmio_map(s, 0, 0x3001c000);
305 sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
306 sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
307 for (i = 0; i < 30; i++) {
308 irq[i] = qdev_get_gpio_in(dev, i);
309 }
310 nmi[0] = qdev_get_gpio_in(dev, 30);
311 nmi[1] = qdev_get_gpio_in(dev, 31);
312
313 etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
314 for (i = 0; i < 10; i++) {
315
316 etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
317 }
318
319
320 dma_eth = g_malloc0(sizeof dma_eth[0] * 4);
321 etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
322 if (nb_nics > 1) {
323 etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
324 }
325
326
327 etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
328 etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
329 if (nb_nics > 1) {
330 etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
331 etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
332 }
333
334
335 sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
336 sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
337
338 for (i = 0; i < 4; i++) {
339 etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hd(i));
340 }
341
342 if (kernel_filename) {
343 li.image_filename = kernel_filename;
344 li.cmdline = kernel_cmdline;
345 cris_load_image(cpu, &li);
346 } else if (!qtest_enabled()) {
347 fprintf(stderr, "Kernel image must be specified\n");
348 exit(1);
349 }
350}
351
352static void axisdev88_machine_init(MachineClass *mc)
353{
354 mc->desc = "AXIS devboard 88";
355 mc->init = axisdev88_init;
356 mc->is_default = 1;
357 mc->default_cpu_type = CRIS_CPU_TYPE_NAME("crisv32");
358}
359
360DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)
361
