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25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "qemu/log.h"
28#include "qemu/module.h"
29#include "hw/display/xlnx_dp.h"
30
31#ifndef DEBUG_DP
32#define DEBUG_DP 0
33#endif
34
35#define DPRINTF(fmt, ...) do { \
36 if (DEBUG_DP) { \
37 qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \
38 } \
39} while (0)
40
41
42
43
44#define DP_LINK_BW_SET (0x0000 >> 2)
45#define DP_LANE_COUNT_SET (0x0004 >> 2)
46#define DP_ENHANCED_FRAME_EN (0x0008 >> 2)
47#define DP_TRAINING_PATTERN_SET (0x000C >> 2)
48#define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2)
49#define DP_SCRAMBLING_DISABLE (0x0014 >> 2)
50#define DP_DOWNSPREAD_CTRL (0x0018 >> 2)
51#define DP_SOFTWARE_RESET (0x001C >> 2)
52#define DP_TRANSMITTER_ENABLE (0x0080 >> 2)
53#define DP_MAIN_STREAM_ENABLE (0x0084 >> 2)
54#define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2)
55#define DP_VERSION_REGISTER (0x00F8 >> 2)
56#define DP_CORE_ID (0x00FC >> 2)
57
58#define DP_AUX_COMMAND_REGISTER (0x0100 >> 2)
59#define AUX_ADDR_ONLY_MASK (0x1000)
60#define AUX_COMMAND_MASK (0x0F00)
61#define AUX_COMMAND_SHIFT (8)
62#define AUX_COMMAND_NBYTES (0x000F)
63
64#define DP_AUX_WRITE_FIFO (0x0104 >> 2)
65#define DP_AUX_ADDRESS (0x0108 >> 2)
66#define DP_AUX_CLOCK_DIVIDER (0x010C >> 2)
67#define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2)
68#define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2)
69#define DP_AUX_REPLY_DATA (0x0134 >> 2)
70#define DP_AUX_REPLY_CODE (0x0138 >> 2)
71#define DP_AUX_REPLY_COUNT (0x013C >> 2)
72#define DP_REPLY_DATA_COUNT (0x0148 >> 2)
73#define DP_REPLY_STATUS (0x014C >> 2)
74#define DP_HPD_DURATION (0x0150 >> 2)
75#define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2)
76#define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2)
77#define DP_MAIN_STREAM_POLARITY (0x0188 >> 2)
78#define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2)
79#define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2)
80#define DP_MAIN_STREAM_HRES (0x0194 >> 2)
81#define DP_MAIN_STREAM_VRES (0x0198 >> 2)
82#define DP_MAIN_STREAM_HSTART (0x019C >> 2)
83#define DP_MAIN_STREAM_VSTART (0x01A0 >> 2)
84#define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2)
85#define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2)
86#define DP_MAIN_STREAM_M_VID (0x01AC >> 2)
87#define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2)
88#define DP_MAIN_STREAM_N_VID (0x01B4 >> 2)
89#define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2)
90#define DP_MIN_BYTES_PER_TU (0x01C4 >> 2)
91#define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2)
92#define DP_INIT_WAIT (0x01CC >> 2)
93#define DP_PHY_RESET (0x0200 >> 2)
94#define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2)
95#define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2)
96#define DP_TRANSMIT_PRBS7 (0x0230 >> 2)
97#define DP_PHY_CLOCK_SELECT (0x0234 >> 2)
98#define DP_TX_PHY_POWER_DOWN (0x0238 >> 2)
99#define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2)
100#define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2)
101#define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2)
102#define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2)
103#define DP_PHY_STATUS (0x0280 >> 2)
104
105#define DP_TX_AUDIO_CONTROL (0x0300 >> 2)
106#define DP_TX_AUD_CTRL (1)
107
108#define DP_TX_AUDIO_CHANNELS (0x0304 >> 2)
109#define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2)
110#define DP_TX_M_AUD (0x0328 >> 2)
111#define DP_TX_N_AUD (0x032C >> 2)
112#define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2)
113#define DP_INT_STATUS (0x03A0 >> 2)
114#define DP_INT_MASK (0x03A4 >> 2)
115#define DP_INT_EN (0x03A8 >> 2)
116#define DP_INT_DS (0x03AC >> 2)
117
118
119
120
121#define V_BLEND_OFFSET (0xA000)
122#define V_BLEND_BG_CLR_0 (0x0000 >> 2)
123#define V_BLEND_BG_CLR_1 (0x0004 >> 2)
124#define V_BLEND_BG_CLR_2 (0x0008 >> 2)
125#define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2)
126#define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2)
127#define V_BLEND_LAYER0_CONTROL (0x0018 >> 2)
128#define V_BLEND_LAYER1_CONTROL (0x001C >> 2)
129
130#define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2)
131#define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2)
132
133#define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2)
134#define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2)
135#define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2)
136#define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2)
137#define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2)
138#define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2)
139
140#define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2)
141
142#define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2)
143#define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2)
144#define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2)
145#define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2)
146#define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2)
147#define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2)
148#define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2)
149
150
151
152
153#define AV_BUF_MANAGER_OFFSET (0xB000)
154#define AV_BUF_FORMAT (0x0000 >> 2)
155#define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2)
156#define AV_CHBUF0 (0x0010 >> 2)
157#define AV_CHBUF1 (0x0014 >> 2)
158#define AV_CHBUF2 (0x0018 >> 2)
159#define AV_CHBUF3 (0x001C >> 2)
160#define AV_CHBUF4 (0x0020 >> 2)
161#define AV_CHBUF5 (0x0024 >> 2)
162#define AV_BUF_STC_CONTROL (0x002C >> 2)
163#define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2)
164#define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2)
165#define AV_BUF_STC_ADJ (0x0038 >> 2)
166#define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2)
167#define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2)
168#define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2)
169#define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2)
170#define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2)
171#define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2)
172#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2)
173#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2)
174#define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2)
175#define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2)
176#define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2)
177#define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2)
178#define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2)
179#define AV_BUF_DITHER_CONFIG (0x007C >> 2)
180#define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2)
181#define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2)
182#define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2)
183#define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2)
184#define AV_BUF_SRST_REG (0x0124 >> 2)
185#define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2)
186#define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2)
187
188#define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2)
189
190#define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2)
191
192#define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2)
193
194#define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2)
195
196#define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2)
197
198#define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2)
199
200#define AUDIO_MIXER_REGISTER_OFFSET (0xC000)
201#define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2)
202#define AUDIO_MIXER_META_DATA (0x0004 >> 2)
203#define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2)
204#define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2)
205#define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2)
206
207#define DP_AUDIO_DMA_CHANNEL(n) (4 + n)
208#define DP_GRAPHIC_DMA_CHANNEL (3)
209#define DP_VIDEO_DMA_CHANNEL (0)
210
211enum DPGraphicFmt {
212 DP_GRAPHIC_RGBA8888 = 0 << 8,
213 DP_GRAPHIC_ABGR8888 = 1 << 8,
214 DP_GRAPHIC_RGB888 = 2 << 8,
215 DP_GRAPHIC_BGR888 = 3 << 8,
216 DP_GRAPHIC_RGBA5551 = 4 << 8,
217 DP_GRAPHIC_RGBA4444 = 5 << 8,
218 DP_GRAPHIC_RGB565 = 6 << 8,
219 DP_GRAPHIC_8BPP = 7 << 8,
220 DP_GRAPHIC_4BPP = 8 << 8,
221 DP_GRAPHIC_2BPP = 9 << 8,
222 DP_GRAPHIC_1BPP = 10 << 8,
223 DP_GRAPHIC_MASK = 0xF << 8
224};
225
226enum DPVideoFmt {
227 DP_NL_VID_CB_Y0_CR_Y1 = 0,
228 DP_NL_VID_CR_Y0_CB_Y1 = 1,
229 DP_NL_VID_Y0_CR_Y1_CB = 2,
230 DP_NL_VID_Y0_CB_Y1_CR = 3,
231 DP_NL_VID_YV16 = 4,
232 DP_NL_VID_YV24 = 5,
233 DP_NL_VID_YV16CL = 6,
234 DP_NL_VID_MONO = 7,
235 DP_NL_VID_YV16CL2 = 8,
236 DP_NL_VID_YUV444 = 9,
237 DP_NL_VID_RGB888 = 10,
238 DP_NL_VID_RGBA8880 = 11,
239 DP_NL_VID_RGB888_10BPC = 12,
240 DP_NL_VID_YUV444_10BPC = 13,
241 DP_NL_VID_YV16CL2_10BPC = 14,
242 DP_NL_VID_YV16CL_10BPC = 15,
243 DP_NL_VID_YV16_10BPC = 16,
244 DP_NL_VID_YV24_10BPC = 17,
245 DP_NL_VID_Y_ONLY_10BPC = 18,
246 DP_NL_VID_YV16_420 = 19,
247 DP_NL_VID_YV16CL_420 = 20,
248 DP_NL_VID_YV16CL2_420 = 21,
249 DP_NL_VID_YV16_420_10BPC = 22,
250 DP_NL_VID_YV16CL_420_10BPC = 23,
251 DP_NL_VID_YV16CL2_420_10BPC = 24,
252 DP_NL_VID_FMT_MASK = 0x1F
253};
254
255typedef enum DPGraphicFmt DPGraphicFmt;
256typedef enum DPVideoFmt DPVideoFmt;
257
258static const VMStateDescription vmstate_dp = {
259 .name = TYPE_XLNX_DP,
260 .version_id = 1,
261 .fields = (VMStateField[]){
262 VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState,
263 DP_CORE_REG_ARRAY_SIZE),
264 VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState,
265 DP_AVBUF_REG_ARRAY_SIZE),
266 VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState,
267 DP_VBLEND_REG_ARRAY_SIZE),
268 VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState,
269 DP_AUDIO_REG_ARRAY_SIZE),
270 VMSTATE_END_OF_LIST()
271 }
272};
273
274static void xlnx_dp_update_irq(XlnxDPState *s);
275
276static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size)
277{
278 XlnxDPState *s = XLNX_DP(opaque);
279
280 offset = offset >> 2;
281 return s->audio_registers[offset];
282}
283
284static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
285 unsigned size)
286{
287 XlnxDPState *s = XLNX_DP(opaque);
288
289 offset = offset >> 2;
290
291 switch (offset) {
292 case AUDIO_MIXER_META_DATA:
293 s->audio_registers[offset] = value & 0x00000001;
294 break;
295 default:
296 s->audio_registers[offset] = value;
297 break;
298 }
299}
300
301static const MemoryRegionOps audio_ops = {
302 .read = xlnx_dp_audio_read,
303 .write = xlnx_dp_audio_write,
304 .endianness = DEVICE_NATIVE_ENDIAN,
305};
306
307static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s,
308 uint8_t channel)
309{
310 switch (channel) {
311 case 0:
312 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16);
313 case 1:
314 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16,
315 16);
316 default:
317 return 0;
318 }
319}
320
321static inline void xlnx_dp_audio_activate(XlnxDPState *s)
322{
323 bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL]
324 & DP_TX_AUD_CTRL) != 0);
325 AUD_set_active_out(s->amixer_output_stream, activated);
326 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0),
327 &s->audio_buffer_0);
328 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1),
329 &s->audio_buffer_1);
330}
331
332static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s)
333{
334
335
336
337
338
339
340
341 int i;
342
343 if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) {
344 for (i = 0; i < s->audio_data_available[0] / 2; i++) {
345 s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i])
346 * xlnx_dp_audio_get_volume(s, 0) / 8192;
347 }
348 s->byte_left = s->audio_data_available[0];
349 } else {
350 memset(s->temp_buffer, 0, s->audio_data_available[1] / 2);
351 }
352
353 if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) {
354 if ((s->audio_data_available[0] == 0)
355 || (s->audio_data_available[1] == s->audio_data_available[0])) {
356 for (i = 0; i < s->audio_data_available[1] / 2; i++) {
357 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i])
358 * xlnx_dp_audio_get_volume(s, 1) / 8192;
359 }
360 s->byte_left = s->audio_data_available[1];
361 }
362 }
363
364 for (i = 0; i < s->byte_left / 2; i++) {
365 s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767));
366 }
367
368 s->data_ptr = 0;
369}
370
371static void xlnx_dp_audio_callback(void *opaque, int avail)
372{
373
374
375
376
377 XlnxDPState *s = XLNX_DP(opaque);
378 size_t written = 0;
379
380
381 if (s->byte_left == 0) {
382 s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4,
383 true);
384 s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5,
385 true);
386 xlnx_dp_audio_mix_buffer(s);
387 }
388
389
390 if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) {
391 if (s->byte_left != 0) {
392 written = AUD_write(s->amixer_output_stream,
393 &s->out_buffer[s->data_ptr], s->byte_left);
394 } else {
395
396
397
398
399 written = 0;
400 memset(s->out_buffer, 0, 1024);
401 AUD_write(s->amixer_output_stream, s->out_buffer, 1024);
402 }
403 } else {
404 written = AUD_write(s->amixer_output_stream,
405 &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE);
406 }
407 s->byte_left -= written;
408 s->data_ptr += written;
409}
410
411
412
413
414static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s)
415{
416 fifo8_reset(&s->rx_fifo);
417}
418
419static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
420{
421 DPRINTF("Push %u data in rx_fifo\n", (unsigned)len);
422 fifo8_push_all(&s->rx_fifo, buf, len);
423}
424
425static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
426{
427 uint8_t ret;
428
429 if (fifo8_is_empty(&s->rx_fifo)) {
430 qemu_log_mask(LOG_GUEST_ERROR,
431 "%s: Reading empty RX_FIFO\n",
432 __func__);
433
434
435
436
437 ret = 0;
438 } else {
439 ret = fifo8_pop(&s->rx_fifo);
440 DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
441 }
442 return ret;
443}
444
445static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s)
446{
447 fifo8_reset(&s->tx_fifo);
448}
449
450static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
451{
452 DPRINTF("Push %u data in tx_fifo\n", (unsigned)len);
453 fifo8_push_all(&s->tx_fifo, buf, len);
454}
455
456static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s)
457{
458 uint8_t ret;
459
460 if (fifo8_is_empty(&s->tx_fifo)) {
461 DPRINTF("tx_fifo underflow..\n");
462 abort();
463 }
464 ret = fifo8_pop(&s->tx_fifo);
465 DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret);
466 return ret;
467}
468
469static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s)
470{
471 return s->core_registers[DP_AUX_ADDRESS];
472}
473
474
475
476
477static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value)
478{
479 bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0;
480 AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT;
481 uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1;
482 uint8_t buf[16];
483 int i;
484
485
486
487
488
489 if (address_only) {
490 nbytes = 0;
491 }
492
493 switch (cmd) {
494 case READ_AUX:
495 case READ_I2C:
496 case READ_I2C_MOT:
497 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
498 xlnx_dp_aux_get_address(s),
499 nbytes, buf);
500 s->core_registers[DP_REPLY_DATA_COUNT] = nbytes;
501
502 if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) {
503 xlnx_dp_aux_push_rx_fifo(s, buf, nbytes);
504 }
505 break;
506 case WRITE_AUX:
507 case WRITE_I2C:
508 case WRITE_I2C_MOT:
509 for (i = 0; i < nbytes; i++) {
510 buf[i] = xlnx_dp_aux_pop_tx_fifo(s);
511 }
512 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
513 xlnx_dp_aux_get_address(s),
514 nbytes, buf);
515 xlnx_dp_aux_clear_tx_fifo(s);
516 break;
517 case WRITE_I2C_STATUS:
518 qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n");
519 break;
520 default:
521 abort();
522 }
523
524 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
525}
526
527static void xlnx_dp_set_dpdma(const Object *obj, const char *name, Object *val,
528 Error **errp)
529{
530 XlnxDPState *s = XLNX_DP(obj);
531 if (s->console) {
532 DisplaySurface *surface = qemu_console_surface(s->console);
533 XlnxDPDMAState *dma = XLNX_DPDMA(val);
534 xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL,
535 surface_data(surface));
536 }
537}
538
539static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s)
540{
541 return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1;
542}
543
544static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s)
545{
546
547
548
549
550 return ((xlnx_dp_global_alpha_value(s) != 0xFF) &&
551 ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0));
552}
553
554static void xlnx_dp_recreate_surface(XlnxDPState *s)
555{
556
557
558
559
560 uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES];
561 uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES];
562 DisplaySurface *current_console_surface = qemu_console_surface(s->console);
563
564 if ((width != 0) && (height != 0)) {
565
566
567
568
569
570 if (s->bout_plane.surface != current_console_surface) {
571 qemu_free_displaysurface(s->bout_plane.surface);
572 }
573 if (s->v_plane.surface != current_console_surface) {
574 qemu_free_displaysurface(s->v_plane.surface);
575 }
576 if (s->g_plane.surface != current_console_surface) {
577 qemu_free_displaysurface(s->g_plane.surface);
578 }
579
580 s->g_plane.surface
581 = qemu_create_displaysurface_from(width, height,
582 s->g_plane.format, 0, NULL);
583 s->v_plane.surface
584 = qemu_create_displaysurface_from(width, height,
585 s->v_plane.format, 0, NULL);
586 if (xlnx_dp_global_alpha_enabled(s)) {
587 s->bout_plane.surface =
588 qemu_create_displaysurface_from(width,
589 height,
590 s->g_plane.format,
591 0, NULL);
592 dpy_gfx_replace_surface(s->console, s->bout_plane.surface);
593 } else {
594 s->bout_plane.surface = NULL;
595 dpy_gfx_replace_surface(s->console, s->g_plane.surface);
596 }
597
598 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
599 surface_data(s->g_plane.surface));
600 xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL,
601 surface_data(s->v_plane.surface));
602 }
603}
604
605
606
607
608static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
609{
610 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
611 case DP_GRAPHIC_RGBA8888:
612 s->g_plane.format = PIXMAN_r8g8b8a8;
613 break;
614 case DP_GRAPHIC_ABGR8888:
615 s->g_plane.format = PIXMAN_a8b8g8r8;
616 break;
617 case DP_GRAPHIC_RGB565:
618 s->g_plane.format = PIXMAN_r5g6b5;
619 break;
620 case DP_GRAPHIC_RGB888:
621 s->g_plane.format = PIXMAN_r8g8b8;
622 break;
623 case DP_GRAPHIC_BGR888:
624 s->g_plane.format = PIXMAN_b8g8r8;
625 break;
626 default:
627 DPRINTF("error: unsupported graphic format %u.\n",
628 s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
629 abort();
630 }
631
632 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
633 case 0:
634 s->v_plane.format = PIXMAN_x8b8g8r8;
635 break;
636 case DP_NL_VID_Y0_CB_Y1_CR:
637 s->v_plane.format = PIXMAN_yuy2;
638 break;
639 case DP_NL_VID_RGBA8880:
640 s->v_plane.format = PIXMAN_x8b8g8r8;
641 break;
642 default:
643 DPRINTF("error: unsupported video format %u.\n",
644 s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
645 abort();
646 }
647
648 xlnx_dp_recreate_surface(s);
649}
650
651static void xlnx_dp_update_irq(XlnxDPState *s)
652{
653 uint32_t flags;
654
655 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK];
656 DPRINTF("update IRQ value = %" PRIx32 "\n", flags);
657 qemu_set_irq(s->irq, flags != 0);
658}
659
660static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size)
661{
662 XlnxDPState *s = XLNX_DP(opaque);
663 uint64_t ret = 0;
664
665 offset = offset >> 2;
666
667 switch (offset) {
668 case DP_TX_USER_FIFO_OVERFLOW:
669
670 ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW];
671 s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0;
672 break;
673 case DP_AUX_REPLY_DATA:
674 ret = xlnx_dp_aux_pop_rx_fifo(s);
675 break;
676 case DP_INTERRUPT_SIGNAL_STATE:
677
678
679
680
681
682 ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE];
683 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04;
684 break;
685 case DP_AUX_WRITE_FIFO:
686 case DP_TX_AUDIO_INFO_DATA(0):
687 case DP_TX_AUDIO_INFO_DATA(1):
688 case DP_TX_AUDIO_INFO_DATA(2):
689 case DP_TX_AUDIO_INFO_DATA(3):
690 case DP_TX_AUDIO_INFO_DATA(4):
691 case DP_TX_AUDIO_INFO_DATA(5):
692 case DP_TX_AUDIO_INFO_DATA(6):
693 case DP_TX_AUDIO_INFO_DATA(7):
694 case DP_TX_AUDIO_EXT_DATA(0):
695 case DP_TX_AUDIO_EXT_DATA(1):
696 case DP_TX_AUDIO_EXT_DATA(2):
697 case DP_TX_AUDIO_EXT_DATA(3):
698 case DP_TX_AUDIO_EXT_DATA(4):
699 case DP_TX_AUDIO_EXT_DATA(5):
700 case DP_TX_AUDIO_EXT_DATA(6):
701 case DP_TX_AUDIO_EXT_DATA(7):
702 case DP_TX_AUDIO_EXT_DATA(8):
703
704 ret = 0;
705 break;
706 default:
707 assert(offset <= (0x3AC >> 2));
708 ret = s->core_registers[offset];
709 break;
710 }
711
712 DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset << 2, ret);
713 return ret;
714}
715
716static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value,
717 unsigned size)
718{
719 XlnxDPState *s = XLNX_DP(opaque);
720
721 DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value);
722
723 offset = offset >> 2;
724
725 switch (offset) {
726
727
728
729 case DP_LINK_BW_SET:
730 s->core_registers[offset] = value & 0x000000FF;
731 break;
732 case DP_LANE_COUNT_SET:
733 case DP_MAIN_STREAM_MISC0:
734 s->core_registers[offset] = value & 0x0000000F;
735 break;
736 case DP_TRAINING_PATTERN_SET:
737 case DP_LINK_QUAL_PATTERN_SET:
738 case DP_MAIN_STREAM_POLARITY:
739 case DP_PHY_VOLTAGE_DIFF_LANE_0:
740 case DP_PHY_VOLTAGE_DIFF_LANE_1:
741 s->core_registers[offset] = value & 0x00000003;
742 break;
743 case DP_ENHANCED_FRAME_EN:
744 case DP_SCRAMBLING_DISABLE:
745 case DP_DOWNSPREAD_CTRL:
746 case DP_MAIN_STREAM_ENABLE:
747 case DP_TRANSMIT_PRBS7:
748 s->core_registers[offset] = value & 0x00000001;
749 break;
750 case DP_PHY_CLOCK_SELECT:
751 s->core_registers[offset] = value & 0x00000007;
752 break;
753 case DP_SOFTWARE_RESET:
754
755
756
757
758
759
760 break;
761 case DP_TRANSMITTER_ENABLE:
762 s->core_registers[offset] = value & 0x01;
763 break;
764 case DP_FORCE_SCRAMBLER_RESET:
765
766
767
768
769
770
771 break;
772 case DP_AUX_COMMAND_REGISTER:
773 s->core_registers[offset] = value & 0x00001F0F;
774 xlnx_dp_aux_set_command(s, s->core_registers[offset]);
775 break;
776 case DP_MAIN_STREAM_HTOTAL:
777 case DP_MAIN_STREAM_VTOTAL:
778 case DP_MAIN_STREAM_HSTART:
779 case DP_MAIN_STREAM_VSTART:
780 s->core_registers[offset] = value & 0x0000FFFF;
781 break;
782 case DP_MAIN_STREAM_HRES:
783 case DP_MAIN_STREAM_VRES:
784 s->core_registers[offset] = value & 0x0000FFFF;
785 xlnx_dp_recreate_surface(s);
786 break;
787 case DP_MAIN_STREAM_HSWIDTH:
788 case DP_MAIN_STREAM_VSWIDTH:
789 s->core_registers[offset] = value & 0x00007FFF;
790 break;
791 case DP_MAIN_STREAM_MISC1:
792 s->core_registers[offset] = value & 0x00000086;
793 break;
794 case DP_MAIN_STREAM_M_VID:
795 case DP_MAIN_STREAM_N_VID:
796 s->core_registers[offset] = value & 0x00FFFFFF;
797 break;
798 case DP_MSA_TRANSFER_UNIT_SIZE:
799 case DP_MIN_BYTES_PER_TU:
800 case DP_INIT_WAIT:
801 s->core_registers[offset] = value & 0x00000007;
802 break;
803 case DP_USER_DATA_COUNT_PER_LANE:
804 s->core_registers[offset] = value & 0x0003FFFF;
805 break;
806 case DP_FRAC_BYTES_PER_TU:
807 s->core_registers[offset] = value & 0x000003FF;
808 break;
809 case DP_PHY_RESET:
810 s->core_registers[offset] = value & 0x00010003;
811
812
813
814 break;
815 case DP_TX_PHY_POWER_DOWN:
816 s->core_registers[offset] = value & 0x0000000F;
817
818
819
820 break;
821 case DP_AUX_WRITE_FIFO: {
822 uint8_t c = value;
823 xlnx_dp_aux_push_tx_fifo(s, &c, 1);
824 break;
825 }
826 case DP_AUX_CLOCK_DIVIDER:
827 break;
828 case DP_AUX_REPLY_COUNT:
829
830
831
832 s->core_registers[offset] = 0x00000000;
833 break;
834 case DP_AUX_ADDRESS:
835 s->core_registers[offset] = value & 0x000FFFFF;
836 break;
837 case DP_VERSION_REGISTER:
838 case DP_CORE_ID:
839 case DP_TX_USER_FIFO_OVERFLOW:
840 case DP_AUX_REPLY_DATA:
841 case DP_AUX_REPLY_CODE:
842 case DP_REPLY_DATA_COUNT:
843 case DP_REPLY_STATUS:
844 case DP_HPD_DURATION:
845
846
847
848 break;
849 case DP_TX_AUDIO_CONTROL:
850 s->core_registers[offset] = value & 0x00000001;
851 xlnx_dp_audio_activate(s);
852 break;
853 case DP_TX_AUDIO_CHANNELS:
854 s->core_registers[offset] = value & 0x00000007;
855 xlnx_dp_audio_activate(s);
856 break;
857 case DP_INT_STATUS:
858 s->core_registers[DP_INT_STATUS] &= ~value;
859 xlnx_dp_update_irq(s);
860 break;
861 case DP_INT_EN:
862 s->core_registers[DP_INT_MASK] &= ~value;
863 xlnx_dp_update_irq(s);
864 break;
865 case DP_INT_DS:
866 s->core_registers[DP_INT_MASK] |= ~value;
867 xlnx_dp_update_irq(s);
868 break;
869 default:
870 assert(offset <= (0x504C >> 2));
871 s->core_registers[offset] = value;
872 break;
873 }
874}
875
876static const MemoryRegionOps dp_ops = {
877 .read = xlnx_dp_read,
878 .write = xlnx_dp_write,
879 .endianness = DEVICE_NATIVE_ENDIAN,
880 .valid = {
881 .min_access_size = 4,
882 .max_access_size = 4,
883 },
884 .impl = {
885 .min_access_size = 4,
886 .max_access_size = 4,
887 },
888};
889
890
891
892
893static void xlnx_dp_vblend_write(void *opaque, hwaddr offset,
894 uint64_t value, unsigned size)
895{
896 XlnxDPState *s = XLNX_DP(opaque);
897 bool alpha_was_enabled;
898
899 DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
900 (uint32_t)value);
901 offset = offset >> 2;
902
903 switch (offset) {
904 case V_BLEND_BG_CLR_0:
905 case V_BLEND_BG_CLR_1:
906 case V_BLEND_BG_CLR_2:
907 s->vblend_registers[offset] = value & 0x00000FFF;
908 break;
909 case V_BLEND_SET_GLOBAL_ALPHA_REG:
910
911
912
913
914 alpha_was_enabled = xlnx_dp_global_alpha_enabled(s);
915 s->vblend_registers[offset] = value & 0x000001FF;
916 if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) {
917 xlnx_dp_recreate_surface(s);
918 }
919 break;
920 case V_BLEND_OUTPUT_VID_FORMAT:
921 s->vblend_registers[offset] = value & 0x00000017;
922 break;
923 case V_BLEND_LAYER0_CONTROL:
924 case V_BLEND_LAYER1_CONTROL:
925 s->vblend_registers[offset] = value & 0x00000103;
926 break;
927 case V_BLEND_RGB2YCBCR_COEFF(0):
928 case V_BLEND_RGB2YCBCR_COEFF(1):
929 case V_BLEND_RGB2YCBCR_COEFF(2):
930 case V_BLEND_RGB2YCBCR_COEFF(3):
931 case V_BLEND_RGB2YCBCR_COEFF(4):
932 case V_BLEND_RGB2YCBCR_COEFF(5):
933 case V_BLEND_RGB2YCBCR_COEFF(6):
934 case V_BLEND_RGB2YCBCR_COEFF(7):
935 case V_BLEND_RGB2YCBCR_COEFF(8):
936 case V_BLEND_IN1CSC_COEFF(0):
937 case V_BLEND_IN1CSC_COEFF(1):
938 case V_BLEND_IN1CSC_COEFF(2):
939 case V_BLEND_IN1CSC_COEFF(3):
940 case V_BLEND_IN1CSC_COEFF(4):
941 case V_BLEND_IN1CSC_COEFF(5):
942 case V_BLEND_IN1CSC_COEFF(6):
943 case V_BLEND_IN1CSC_COEFF(7):
944 case V_BLEND_IN1CSC_COEFF(8):
945 case V_BLEND_IN2CSC_COEFF(0):
946 case V_BLEND_IN2CSC_COEFF(1):
947 case V_BLEND_IN2CSC_COEFF(2):
948 case V_BLEND_IN2CSC_COEFF(3):
949 case V_BLEND_IN2CSC_COEFF(4):
950 case V_BLEND_IN2CSC_COEFF(5):
951 case V_BLEND_IN2CSC_COEFF(6):
952 case V_BLEND_IN2CSC_COEFF(7):
953 case V_BLEND_IN2CSC_COEFF(8):
954 s->vblend_registers[offset] = value & 0x0000FFFF;
955 break;
956 case V_BLEND_LUMA_IN1CSC_OFFSET:
957 case V_BLEND_CR_IN1CSC_OFFSET:
958 case V_BLEND_CB_IN1CSC_OFFSET:
959 case V_BLEND_LUMA_IN2CSC_OFFSET:
960 case V_BLEND_CR_IN2CSC_OFFSET:
961 case V_BLEND_CB_IN2CSC_OFFSET:
962 case V_BLEND_LUMA_OUTCSC_OFFSET:
963 case V_BLEND_CR_OUTCSC_OFFSET:
964 case V_BLEND_CB_OUTCSC_OFFSET:
965 s->vblend_registers[offset] = value & 0x3FFF7FFF;
966 break;
967 case V_BLEND_CHROMA_KEY_ENABLE:
968 s->vblend_registers[offset] = value & 0x00000003;
969 break;
970 case V_BLEND_CHROMA_KEY_COMP1:
971 case V_BLEND_CHROMA_KEY_COMP2:
972 case V_BLEND_CHROMA_KEY_COMP3:
973 s->vblend_registers[offset] = value & 0x0FFF0FFF;
974 break;
975 default:
976 s->vblend_registers[offset] = value;
977 break;
978 }
979}
980
981static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset,
982 unsigned size)
983{
984 XlnxDPState *s = XLNX_DP(opaque);
985
986 DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
987 s->vblend_registers[offset >> 2]);
988 return s->vblend_registers[offset >> 2];
989}
990
991static const MemoryRegionOps vblend_ops = {
992 .read = xlnx_dp_vblend_read,
993 .write = xlnx_dp_vblend_write,
994 .endianness = DEVICE_NATIVE_ENDIAN,
995 .valid = {
996 .min_access_size = 4,
997 .max_access_size = 4,
998 },
999 .impl = {
1000 .min_access_size = 4,
1001 .max_access_size = 4,
1002 },
1003};
1004
1005
1006
1007
1008static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
1009 unsigned size)
1010{
1011 XlnxDPState *s = XLNX_DP(opaque);
1012
1013 DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
1014 (uint32_t)value);
1015 offset = offset >> 2;
1016
1017 switch (offset) {
1018 case AV_BUF_FORMAT:
1019 s->avbufm_registers[offset] = value & 0x00000FFF;
1020 xlnx_dp_change_graphic_fmt(s);
1021 break;
1022 case AV_CHBUF0:
1023 case AV_CHBUF1:
1024 case AV_CHBUF2:
1025 case AV_CHBUF3:
1026 case AV_CHBUF4:
1027 case AV_CHBUF5:
1028 s->avbufm_registers[offset] = value & 0x0000007F;
1029 break;
1030 case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT:
1031 s->avbufm_registers[offset] = value & 0x0000007F;
1032 break;
1033 case AV_BUF_DITHER_CONFIG:
1034 s->avbufm_registers[offset] = value & 0x000007FF;
1035 break;
1036 case AV_BUF_DITHER_CONFIG_MAX:
1037 case AV_BUF_DITHER_CONFIG_MIN:
1038 s->avbufm_registers[offset] = value & 0x00000FFF;
1039 break;
1040 case AV_BUF_PATTERN_GEN_SELECT:
1041 s->avbufm_registers[offset] = value & 0xFFFFFF03;
1042 break;
1043 case AV_BUF_AUD_VID_CLK_SOURCE:
1044 s->avbufm_registers[offset] = value & 0x00000007;
1045 break;
1046 case AV_BUF_SRST_REG:
1047 s->avbufm_registers[offset] = value & 0x00000002;
1048 break;
1049 case AV_BUF_AUDIO_CH_CONFIG:
1050 s->avbufm_registers[offset] = value & 0x00000003;
1051 break;
1052 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0):
1053 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1):
1054 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2):
1055 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0):
1056 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1):
1057 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2):
1058 s->avbufm_registers[offset] = value & 0x0000FFFF;
1059 break;
1060 case AV_BUF_LIVE_VIDEO_COMP_SF(0):
1061 case AV_BUF_LIVE_VIDEO_COMP_SF(1):
1062 case AV_BUF_LIVE_VIDEO_COMP_SF(2):
1063 case AV_BUF_LIVE_VID_CONFIG:
1064 case AV_BUF_LIVE_GFX_COMP_SF(0):
1065 case AV_BUF_LIVE_GFX_COMP_SF(1):
1066 case AV_BUF_LIVE_GFX_COMP_SF(2):
1067 case AV_BUF_LIVE_GFX_CONFIG:
1068 case AV_BUF_NON_LIVE_LATENCY:
1069 case AV_BUF_STC_CONTROL:
1070 case AV_BUF_STC_INIT_VALUE0:
1071 case AV_BUF_STC_INIT_VALUE1:
1072 case AV_BUF_STC_ADJ:
1073 case AV_BUF_STC_VIDEO_VSYNC_TS_REG0:
1074 case AV_BUF_STC_VIDEO_VSYNC_TS_REG1:
1075 case AV_BUF_STC_EXT_VSYNC_TS_REG0:
1076 case AV_BUF_STC_EXT_VSYNC_TS_REG1:
1077 case AV_BUF_STC_CUSTOM_EVENT_TS_REG0:
1078 case AV_BUF_STC_CUSTOM_EVENT_TS_REG1:
1079 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0:
1080 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1:
1081 case AV_BUF_STC_SNAPSHOT0:
1082 case AV_BUF_STC_SNAPSHOT1:
1083 case AV_BUF_HCOUNT_VCOUNT_INT0:
1084 case AV_BUF_HCOUNT_VCOUNT_INT1:
1085 qemu_log_mask(LOG_UNIMP, "avbufm: unimplemented register 0x%04"
1086 PRIx64 "\n",
1087 offset << 2);
1088 break;
1089 default:
1090 s->avbufm_registers[offset] = value;
1091 break;
1092 }
1093}
1094
1095static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset,
1096 unsigned size)
1097{
1098 XlnxDPState *s = XLNX_DP(opaque);
1099
1100 offset = offset >> 2;
1101 return s->avbufm_registers[offset];
1102}
1103
1104static const MemoryRegionOps avbufm_ops = {
1105 .read = xlnx_dp_avbufm_read,
1106 .write = xlnx_dp_avbufm_write,
1107 .endianness = DEVICE_NATIVE_ENDIAN,
1108 .valid = {
1109 .min_access_size = 4,
1110 .max_access_size = 4,
1111 },
1112 .impl = {
1113 .min_access_size = 4,
1114 .max_access_size = 4,
1115 },
1116};
1117
1118
1119
1120
1121
1122
1123static inline void xlnx_dp_blend_surface(XlnxDPState *s)
1124{
1125 pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1),
1126 pixman_double_to_fixed(1),
1127 pixman_double_to_fixed(1.0) };
1128 pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1),
1129 pixman_double_to_fixed(1),
1130 pixman_double_to_fixed(1.0) };
1131
1132 if ((surface_width(s->g_plane.surface)
1133 != surface_width(s->v_plane.surface)) ||
1134 (surface_height(s->g_plane.surface)
1135 != surface_height(s->v_plane.surface))) {
1136 return;
1137 }
1138
1139 alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s))
1140 / 256.0);
1141 alpha2[2] = pixman_double_to_fixed((255.0
1142 - (double)xlnx_dp_global_alpha_value(s))
1143 / 256.0);
1144
1145 pixman_image_set_filter(s->g_plane.surface->image,
1146 PIXMAN_FILTER_CONVOLUTION, alpha1, 3);
1147 pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0,
1148 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1149 surface_width(s->g_plane.surface),
1150 surface_height(s->g_plane.surface));
1151 pixman_image_set_filter(s->v_plane.surface->image,
1152 PIXMAN_FILTER_CONVOLUTION, alpha2, 3);
1153 pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0,
1154 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1155 surface_width(s->g_plane.surface),
1156 surface_height(s->g_plane.surface));
1157}
1158
1159static void xlnx_dp_update_display(void *opaque)
1160{
1161 XlnxDPState *s = XLNX_DP(opaque);
1162
1163 if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) {
1164 return;
1165 }
1166
1167 s->core_registers[DP_INT_STATUS] |= (1 << 13);
1168 xlnx_dp_update_irq(s);
1169
1170 xlnx_dpdma_trigger_vsync_irq(s->dpdma);
1171
1172
1173
1174
1175 if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) {
1176
1177
1178
1179
1180 s->core_registers[DP_INT_STATUS] |= (1 << 21);
1181 xlnx_dp_update_irq(s);
1182 return;
1183 }
1184
1185 if (xlnx_dp_global_alpha_enabled(s)) {
1186 if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) {
1187 s->core_registers[DP_INT_STATUS] |= (1 << 21);
1188 xlnx_dp_update_irq(s);
1189 return;
1190 }
1191 xlnx_dp_blend_surface(s);
1192 }
1193
1194
1195
1196
1197 dpy_gfx_update_full(s->console);
1198}
1199
1200static const GraphicHwOps xlnx_dp_gfx_ops = {
1201 .gfx_update = xlnx_dp_update_display,
1202};
1203
1204static void xlnx_dp_init(Object *obj)
1205{
1206 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1207 XlnxDPState *s = XLNX_DP(obj);
1208
1209 memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050);
1210
1211 memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP
1212 ".core", 0x3AF);
1213 memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem);
1214
1215 memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP
1216 ".v_blend", 0x1DF);
1217 memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem);
1218
1219 memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP
1220 ".av_buffer_manager", 0x238);
1221 memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem);
1222
1223 memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP
1224 ".audio", sizeof(s->audio_registers));
1225 memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem);
1226
1227 sysbus_init_mmio(sbd, &s->container);
1228 sysbus_init_irq(sbd, &s->irq);
1229
1230 object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA,
1231 (Object **) &s->dpdma,
1232 xlnx_dp_set_dpdma,
1233 OBJ_PROP_LINK_STRONG,
1234 &error_abort);
1235
1236
1237
1238
1239 s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
1240
1241
1242
1243
1244 s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd"));
1245 object_property_add_child(OBJECT(s), "dpcd", OBJECT(s->dpcd), NULL);
1246
1247 s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
1248 i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
1249 object_property_add_child(OBJECT(s), "edid", OBJECT(s->edid), NULL);
1250
1251 fifo8_create(&s->rx_fifo, 16);
1252 fifo8_create(&s->tx_fifo, 16);
1253}
1254
1255static void xlnx_dp_realize(DeviceState *dev, Error **errp)
1256{
1257 XlnxDPState *s = XLNX_DP(dev);
1258 DisplaySurface *surface;
1259 struct audsettings as;
1260
1261 qdev_init_nofail(DEVICE(s->dpcd));
1262 aux_map_slave(AUX_SLAVE(s->dpcd), 0x0000);
1263
1264 s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s);
1265 surface = qemu_console_surface(s->console);
1266 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
1267 surface_data(surface));
1268
1269 as.freq = 44100;
1270 as.nchannels = 2;
1271 as.fmt = AUDIO_FORMAT_S16;
1272 as.endianness = 0;
1273
1274 AUD_register_card("xlnx_dp.audio", &s->aud_card);
1275
1276 s->amixer_output_stream = AUD_open_out(&s->aud_card,
1277 s->amixer_output_stream,
1278 "xlnx_dp.audio.out",
1279 s,
1280 xlnx_dp_audio_callback,
1281 &as);
1282 AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255);
1283 xlnx_dp_audio_activate(s);
1284}
1285
1286static void xlnx_dp_reset(DeviceState *dev)
1287{
1288 XlnxDPState *s = XLNX_DP(dev);
1289
1290 memset(s->core_registers, 0, sizeof(s->core_registers));
1291 s->core_registers[DP_VERSION_REGISTER] = 0x04010000;
1292 s->core_registers[DP_CORE_ID] = 0x01020000;
1293 s->core_registers[DP_REPLY_STATUS] = 0x00000010;
1294 s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040;
1295 s->core_registers[DP_INIT_WAIT] = 0x00000020;
1296 s->core_registers[DP_PHY_RESET] = 0x00010003;
1297 s->core_registers[DP_INT_MASK] = 0xFFFFF03F;
1298 s->core_registers[DP_PHY_STATUS] = 0x00000043;
1299 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001;
1300
1301 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000;
1302 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000;
1303 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000;
1304 s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000;
1305 s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000;
1306 s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000;
1307 s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000;
1308 s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000;
1309 s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000;
1310
1311 s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180;
1312 s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008;
1313 s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF;
1314 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101;
1315 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101;
1316 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101;
1317 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101;
1318 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101;
1319 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101;
1320 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101;
1321 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101;
1322 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101;
1323 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101;
1324 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101;
1325 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101;
1326
1327 memset(s->audio_registers, 0, sizeof(s->audio_registers));
1328 s->byte_left = 0;
1329
1330 xlnx_dp_aux_clear_rx_fifo(s);
1331 xlnx_dp_change_graphic_fmt(s);
1332 xlnx_dp_update_irq(s);
1333}
1334
1335static void xlnx_dp_class_init(ObjectClass *oc, void *data)
1336{
1337 DeviceClass *dc = DEVICE_CLASS(oc);
1338
1339 dc->realize = xlnx_dp_realize;
1340 dc->vmsd = &vmstate_dp;
1341 dc->reset = xlnx_dp_reset;
1342}
1343
1344static const TypeInfo xlnx_dp_info = {
1345 .name = TYPE_XLNX_DP,
1346 .parent = TYPE_SYS_BUS_DEVICE,
1347 .instance_size = sizeof(XlnxDPState),
1348 .instance_init = xlnx_dp_init,
1349 .class_init = xlnx_dp_class_init,
1350};
1351
1352static void xlnx_dp_register_types(void)
1353{
1354 type_register_static(&xlnx_dp_info);
1355}
1356
1357type_init(xlnx_dp_register_types)
1358