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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/isa/isa.h"
28#include "hw/dma/i8257.h"
29#include "qemu/main-loop.h"
30#include "qemu/module.h"
31#include "qemu/log.h"
32#include "trace.h"
33
34#define I8257(obj) \
35 OBJECT_CHECK(I8257State, (obj), TYPE_I8257)
36
37
38
39#define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
40#ifdef DEBUG_DMA
41#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
42#define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
43#else
44#define linfo(...)
45#define ldebug(...)
46#endif
47
48#define ADDR 0
49#define COUNT 1
50
51enum {
52 CMD_MEMORY_TO_MEMORY = 0x01,
53 CMD_FIXED_ADDRESS = 0x02,
54 CMD_BLOCK_CONTROLLER = 0x04,
55 CMD_COMPRESSED_TIME = 0x08,
56 CMD_CYCLIC_PRIORITY = 0x10,
57 CMD_EXTENDED_WRITE = 0x20,
58 CMD_LOW_DREQ = 0x40,
59 CMD_LOW_DACK = 0x80,
60 CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
61 | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
62 | CMD_LOW_DREQ | CMD_LOW_DACK
63
64};
65
66static void i8257_dma_run(void *opaque);
67
68static const int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
69
70static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data)
71{
72 I8257State *d = opaque;
73 int ichan;
74
75 ichan = channels[nport & 7];
76 if (-1 == ichan) {
77 dolog ("invalid channel %#x %#x\n", nport, data);
78 return;
79 }
80 d->regs[ichan].page = data;
81}
82
83static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data)
84{
85 I8257State *d = opaque;
86 int ichan;
87
88 ichan = channels[nport & 7];
89 if (-1 == ichan) {
90 dolog ("invalid channel %#x %#x\n", nport, data);
91 return;
92 }
93 d->regs[ichan].pageh = data;
94}
95
96static uint32_t i8257_read_page(void *opaque, uint32_t nport)
97{
98 I8257State *d = opaque;
99 int ichan;
100
101 ichan = channels[nport & 7];
102 if (-1 == ichan) {
103 dolog ("invalid channel read %#x\n", nport);
104 return 0;
105 }
106 return d->regs[ichan].page;
107}
108
109static uint32_t i8257_read_pageh(void *opaque, uint32_t nport)
110{
111 I8257State *d = opaque;
112 int ichan;
113
114 ichan = channels[nport & 7];
115 if (-1 == ichan) {
116 dolog ("invalid channel read %#x\n", nport);
117 return 0;
118 }
119 return d->regs[ichan].pageh;
120}
121
122static inline void i8257_init_chan(I8257State *d, int ichan)
123{
124 I8257Regs *r;
125
126 r = d->regs + ichan;
127 r->now[ADDR] = r->base[ADDR] << d->dshift;
128 r->now[COUNT] = 0;
129}
130
131static inline int i8257_getff(I8257State *d)
132{
133 int ff;
134
135 ff = d->flip_flop;
136 d->flip_flop = !ff;
137 return ff;
138}
139
140static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size)
141{
142 I8257State *d = opaque;
143 int ichan, nreg, iport, ff, val, dir;
144 I8257Regs *r;
145
146 iport = (nport >> d->dshift) & 0x0f;
147 ichan = iport >> 1;
148 nreg = iport & 1;
149 r = d->regs + ichan;
150
151 dir = ((r->mode >> 5) & 1) ? -1 : 1;
152 ff = i8257_getff(d);
153 if (nreg)
154 val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
155 else
156 val = r->now[ADDR] + r->now[COUNT] * dir;
157
158 ldebug ("read_chan %#x -> %d\n", iport, val);
159 return (val >> (d->dshift + (ff << 3))) & 0xff;
160}
161
162static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data,
163 unsigned int size)
164{
165 I8257State *d = opaque;
166 int iport, ichan, nreg;
167 I8257Regs *r;
168
169 iport = (nport >> d->dshift) & 0x0f;
170 ichan = iport >> 1;
171 nreg = iport & 1;
172 r = d->regs + ichan;
173 if (i8257_getff(d)) {
174 r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
175 i8257_init_chan(d, ichan);
176 } else {
177 r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
178 }
179}
180
181static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data,
182 unsigned int size)
183{
184 I8257State *d = opaque;
185 int iport, ichan = 0;
186
187 iport = (nport >> d->dshift) & 0x0f;
188 switch (iport) {
189 case 0x00:
190 if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
191 qemu_log_mask(LOG_UNIMP, "%s: cmd 0x%02"PRIx64" not supported\n",
192 __func__, data);
193 return;
194 }
195 d->command = data;
196 break;
197
198 case 0x01:
199 ichan = data & 3;
200 if (data & 4) {
201 d->status |= 1 << (ichan + 4);
202 }
203 else {
204 d->status &= ~(1 << (ichan + 4));
205 }
206 d->status &= ~(1 << ichan);
207 i8257_dma_run(d);
208 break;
209
210 case 0x02:
211 if (data & 4)
212 d->mask |= 1 << (data & 3);
213 else
214 d->mask &= ~(1 << (data & 3));
215 i8257_dma_run(d);
216 break;
217
218 case 0x03:
219 {
220 ichan = data & 3;
221#ifdef DEBUG_DMA
222 {
223 int op, ai, dir, opmode;
224 op = (data >> 2) & 3;
225 ai = (data >> 4) & 1;
226 dir = (data >> 5) & 1;
227 opmode = (data >> 6) & 3;
228
229 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
230 ichan, op, ai, dir, opmode);
231 }
232#endif
233 d->regs[ichan].mode = data;
234 break;
235 }
236
237 case 0x04:
238 d->flip_flop = 0;
239 break;
240
241 case 0x05:
242 d->flip_flop = 0;
243 d->mask = ~0;
244 d->status = 0;
245 d->command = 0;
246 break;
247
248 case 0x06:
249 d->mask = 0;
250 i8257_dma_run(d);
251 break;
252
253 case 0x07:
254 d->mask = data;
255 i8257_dma_run(d);
256 break;
257
258 default:
259 dolog ("unknown iport %#x\n", iport);
260 break;
261 }
262
263#ifdef DEBUG_DMA
264 if (0xc != iport) {
265 linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
266 nport, ichan, data);
267 }
268#endif
269}
270
271static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size)
272{
273 I8257State *d = opaque;
274 int iport, val;
275
276 iport = (nport >> d->dshift) & 0x0f;
277 switch (iport) {
278 case 0x00:
279 val = d->status;
280 d->status &= 0xf0;
281 break;
282 case 0x01:
283 val = d->mask;
284 break;
285 default:
286 val = 0;
287 break;
288 }
289
290 ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
291 return val;
292}
293
294static IsaDmaTransferMode i8257_dma_get_transfer_mode(IsaDma *obj, int nchan)
295{
296 I8257State *d = I8257(obj);
297 return (d->regs[nchan & 3].mode >> 2) & 3;
298}
299
300static bool i8257_dma_has_autoinitialization(IsaDma *obj, int nchan)
301{
302 I8257State *d = I8257(obj);
303 return (d->regs[nchan & 3].mode >> 4) & 1;
304}
305
306static void i8257_dma_hold_DREQ(IsaDma *obj, int nchan)
307{
308 I8257State *d = I8257(obj);
309 int ichan;
310
311 ichan = nchan & 3;
312 d->status |= 1 << (ichan + 4);
313 i8257_dma_run(d);
314}
315
316static void i8257_dma_release_DREQ(IsaDma *obj, int nchan)
317{
318 I8257State *d = I8257(obj);
319 int ichan;
320
321 ichan = nchan & 3;
322 d->status &= ~(1 << (ichan + 4));
323 i8257_dma_run(d);
324}
325
326static void i8257_channel_run(I8257State *d, int ichan)
327{
328 int ncont = d->dshift;
329 int n;
330 I8257Regs *r = &d->regs[ichan];
331#ifdef DEBUG_DMA
332 int dir, opmode;
333
334 dir = (r->mode >> 5) & 1;
335 opmode = (r->mode >> 6) & 3;
336
337 if (dir) {
338 dolog ("DMA in address decrement mode\n");
339 }
340 if (opmode != 1) {
341 dolog ("DMA not in single mode select %#x\n", opmode);
342 }
343#endif
344
345 n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
346 r->now[COUNT], (r->base[COUNT] + 1) << ncont);
347 r->now[COUNT] = n;
348 ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
349 if (n == (r->base[COUNT] + 1) << ncont) {
350 ldebug("transfer done\n");
351 d->status |= (1 << ichan);
352 }
353}
354
355static void i8257_dma_run(void *opaque)
356{
357 I8257State *d = opaque;
358 int ichan;
359 int rearm = 0;
360
361 if (d->running) {
362 rearm = 1;
363 goto out;
364 } else {
365 d->running = 1;
366 }
367
368 for (ichan = 0; ichan < 4; ichan++) {
369 int mask;
370
371 mask = 1 << ichan;
372
373 if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
374 i8257_channel_run(d, ichan);
375 rearm = 1;
376 }
377 }
378
379 d->running = 0;
380out:
381 if (rearm) {
382 qemu_bh_schedule_idle(d->dma_bh);
383 d->dma_bh_scheduled = true;
384 }
385}
386
387static void i8257_dma_register_channel(IsaDma *obj, int nchan,
388 IsaDmaTransferHandler transfer_handler,
389 void *opaque)
390{
391 I8257State *d = I8257(obj);
392 I8257Regs *r;
393 int ichan;
394
395 ichan = nchan & 3;
396
397 r = d->regs + ichan;
398 r->transfer_handler = transfer_handler;
399 r->opaque = opaque;
400}
401
402static int i8257_dma_read_memory(IsaDma *obj, int nchan, void *buf, int pos,
403 int len)
404{
405 I8257State *d = I8257(obj);
406 I8257Regs *r = &d->regs[nchan & 3];
407 hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
408
409 if (r->mode & 0x20) {
410 int i;
411 uint8_t *p = buf;
412
413 cpu_physical_memory_read (addr - pos - len, buf, len);
414
415 for (i = 0; i < len >> 1; i++) {
416 uint8_t b = p[len - i - 1];
417 p[i] = b;
418 }
419 }
420 else
421 cpu_physical_memory_read (addr + pos, buf, len);
422
423 return len;
424}
425
426static int i8257_dma_write_memory(IsaDma *obj, int nchan, void *buf, int pos,
427 int len)
428{
429 I8257State *s = I8257(obj);
430 I8257Regs *r = &s->regs[nchan & 3];
431 hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
432
433 if (r->mode & 0x20) {
434 int i;
435 uint8_t *p = buf;
436
437 cpu_physical_memory_write (addr - pos - len, buf, len);
438
439 for (i = 0; i < len; i++) {
440 uint8_t b = p[len - i - 1];
441 p[i] = b;
442 }
443 }
444 else
445 cpu_physical_memory_write (addr + pos, buf, len);
446
447 return len;
448}
449
450
451
452
453static void i8257_dma_schedule(IsaDma *obj)
454{
455 I8257State *d = I8257(obj);
456 if (d->dma_bh_scheduled) {
457 qemu_notify_event();
458 }
459}
460
461static void i8257_reset(DeviceState *dev)
462{
463 I8257State *d = I8257(dev);
464 i8257_write_cont(d, (0x05 << d->dshift), 0, 1);
465}
466
467static int i8257_phony_handler(void *opaque, int nchan, int dma_pos,
468 int dma_len)
469{
470 trace_i8257_unregistered_dma(nchan, dma_pos, dma_len);
471 return dma_pos;
472}
473
474
475static const MemoryRegionOps channel_io_ops = {
476 .read = i8257_read_chan,
477 .write = i8257_write_chan,
478 .endianness = DEVICE_NATIVE_ENDIAN,
479 .impl = {
480 .min_access_size = 1,
481 .max_access_size = 1,
482 },
483};
484
485
486static const MemoryRegionPortio page_portio_list[] = {
487 { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, },
488 { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, },
489 PORTIO_END_OF_LIST(),
490};
491
492
493static const MemoryRegionPortio pageh_portio_list[] = {
494 { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
495 { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
496 PORTIO_END_OF_LIST(),
497};
498
499static const MemoryRegionOps cont_io_ops = {
500 .read = i8257_read_cont,
501 .write = i8257_write_cont,
502 .endianness = DEVICE_NATIVE_ENDIAN,
503 .impl = {
504 .min_access_size = 1,
505 .max_access_size = 1,
506 },
507};
508
509static const VMStateDescription vmstate_i8257_regs = {
510 .name = "dma_regs",
511 .version_id = 1,
512 .minimum_version_id = 1,
513 .fields = (VMStateField[]) {
514 VMSTATE_INT32_ARRAY(now, I8257Regs, 2),
515 VMSTATE_UINT16_ARRAY(base, I8257Regs, 2),
516 VMSTATE_UINT8(mode, I8257Regs),
517 VMSTATE_UINT8(page, I8257Regs),
518 VMSTATE_UINT8(pageh, I8257Regs),
519 VMSTATE_UINT8(dack, I8257Regs),
520 VMSTATE_UINT8(eop, I8257Regs),
521 VMSTATE_END_OF_LIST()
522 }
523};
524
525static int i8257_post_load(void *opaque, int version_id)
526{
527 I8257State *d = opaque;
528 i8257_dma_run(d);
529
530 return 0;
531}
532
533static const VMStateDescription vmstate_i8257 = {
534 .name = "dma",
535 .version_id = 1,
536 .minimum_version_id = 1,
537 .post_load = i8257_post_load,
538 .fields = (VMStateField[]) {
539 VMSTATE_UINT8(command, I8257State),
540 VMSTATE_UINT8(mask, I8257State),
541 VMSTATE_UINT8(flip_flop, I8257State),
542 VMSTATE_INT32(dshift, I8257State),
543 VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs,
544 I8257Regs),
545 VMSTATE_END_OF_LIST()
546 }
547};
548
549static void i8257_realize(DeviceState *dev, Error **errp)
550{
551 ISADevice *isa = ISA_DEVICE(dev);
552 I8257State *d = I8257(dev);
553 int i;
554
555 memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d,
556 "dma-chan", 8 << d->dshift);
557 memory_region_add_subregion(isa_address_space_io(isa),
558 d->base, &d->channel_io);
559
560 isa_register_portio_list(isa, &d->portio_page,
561 d->page_base, page_portio_list, d,
562 "dma-page");
563 if (d->pageh_base >= 0) {
564 isa_register_portio_list(isa, &d->portio_pageh,
565 d->pageh_base, pageh_portio_list, d,
566 "dma-pageh");
567 }
568
569 memory_region_init_io(&d->cont_io, OBJECT(isa), &cont_io_ops, d,
570 "dma-cont", 8 << d->dshift);
571 memory_region_add_subregion(isa_address_space_io(isa),
572 d->base + (8 << d->dshift), &d->cont_io);
573
574 for (i = 0; i < ARRAY_SIZE(d->regs); ++i) {
575 d->regs[i].transfer_handler = i8257_phony_handler;
576 }
577
578 d->dma_bh = qemu_bh_new(i8257_dma_run, d);
579}
580
581static Property i8257_properties[] = {
582 DEFINE_PROP_INT32("base", I8257State, base, 0x00),
583 DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
584 DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
585 DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
586 DEFINE_PROP_END_OF_LIST()
587};
588
589static void i8257_class_init(ObjectClass *klass, void *data)
590{
591 DeviceClass *dc = DEVICE_CLASS(klass);
592 IsaDmaClass *idc = ISADMA_CLASS(klass);
593
594 dc->realize = i8257_realize;
595 dc->reset = i8257_reset;
596 dc->vmsd = &vmstate_i8257;
597 dc->props = i8257_properties;
598
599 idc->get_transfer_mode = i8257_dma_get_transfer_mode;
600 idc->has_autoinitialization = i8257_dma_has_autoinitialization;
601 idc->read_memory = i8257_dma_read_memory;
602 idc->write_memory = i8257_dma_write_memory;
603 idc->hold_DREQ = i8257_dma_hold_DREQ;
604 idc->release_DREQ = i8257_dma_release_DREQ;
605 idc->schedule = i8257_dma_schedule;
606 idc->register_channel = i8257_dma_register_channel;
607
608 dc->user_creatable = false;
609}
610
611static const TypeInfo i8257_info = {
612 .name = TYPE_I8257,
613 .parent = TYPE_ISA_DEVICE,
614 .instance_size = sizeof(I8257State),
615 .class_init = i8257_class_init,
616 .interfaces = (InterfaceInfo[]) {
617 { TYPE_ISADMA },
618 { }
619 }
620};
621
622static void i8257_register_types(void)
623{
624 type_register_static(&i8257_info);
625}
626
627type_init(i8257_register_types)
628
629void i8257_dma_init(ISABus *bus, bool high_page_enable)
630{
631 ISADevice *isa1, *isa2;
632 DeviceState *d;
633
634 isa1 = isa_create(bus, TYPE_I8257);
635 d = DEVICE(isa1);
636 qdev_prop_set_int32(d, "base", 0x00);
637 qdev_prop_set_int32(d, "page-base", 0x80);
638 qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1);
639 qdev_prop_set_int32(d, "dshift", 0);
640 qdev_init_nofail(d);
641
642 isa2 = isa_create(bus, TYPE_I8257);
643 d = DEVICE(isa2);
644 qdev_prop_set_int32(d, "base", 0xc0);
645 qdev_prop_set_int32(d, "page-base", 0x88);
646 qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1);
647 qdev_prop_set_int32(d, "dshift", 1);
648 qdev_init_nofail(d);
649
650 isa_bus_dma(bus, ISADMA(isa1), ISADMA(isa2));
651}
652
