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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "qapi/error.h"
28#include "qemu/timer.h"
29#include "hw/ptimer.h"
30#include "qemu/log.h"
31#include "qemu/main-loop.h"
32#include "qemu/module.h"
33
34#include "hw/stream.h"
35
36#define D(x)
37
38#define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
39#define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
40#define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
41
42#define XILINX_AXI_DMA(obj) \
43 OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
44
45#define XILINX_AXI_DMA_DATA_STREAM(obj) \
46 OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
47 TYPE_XILINX_AXI_DMA_DATA_STREAM)
48
49#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
50 OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
51 TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
52
53#define R_DMACR (0x00 / 4)
54#define R_DMASR (0x04 / 4)
55#define R_CURDESC (0x08 / 4)
56#define R_TAILDESC (0x10 / 4)
57#define R_MAX (0x30 / 4)
58
59#define CONTROL_PAYLOAD_WORDS 5
60#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
61
62typedef struct XilinxAXIDMA XilinxAXIDMA;
63typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
64
65enum {
66 DMACR_RUNSTOP = 1,
67 DMACR_TAILPTR_MODE = 2,
68 DMACR_RESET = 4
69};
70
71enum {
72 DMASR_HALTED = 1,
73 DMASR_IDLE = 2,
74 DMASR_IOC_IRQ = 1 << 12,
75 DMASR_DLY_IRQ = 1 << 13,
76
77 DMASR_IRQ_MASK = 7 << 12
78};
79
80struct SDesc {
81 uint64_t nxtdesc;
82 uint64_t buffer_address;
83 uint64_t reserved;
84 uint32_t control;
85 uint32_t status;
86 uint8_t app[CONTROL_PAYLOAD_SIZE];
87};
88
89enum {
90 SDESC_CTRL_EOF = (1 << 26),
91 SDESC_CTRL_SOF = (1 << 27),
92
93 SDESC_CTRL_LEN_MASK = (1 << 23) - 1
94};
95
96enum {
97 SDESC_STATUS_EOF = (1 << 26),
98 SDESC_STATUS_SOF_BIT = 27,
99 SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
100 SDESC_STATUS_COMPLETE = (1 << 31)
101};
102
103struct Stream {
104 QEMUBH *bh;
105 ptimer_state *ptimer;
106 qemu_irq irq;
107
108 int nr;
109
110 struct SDesc desc;
111 int pos;
112 unsigned int complete_cnt;
113 uint32_t regs[R_MAX];
114 uint8_t app[20];
115 unsigned char txbuf[16 * 1024];
116};
117
118struct XilinxAXIDMAStreamSlave {
119 Object parent;
120
121 struct XilinxAXIDMA *dma;
122};
123
124struct XilinxAXIDMA {
125 SysBusDevice busdev;
126 MemoryRegion iomem;
127 uint32_t freqhz;
128 StreamSlave *tx_data_dev;
129 StreamSlave *tx_control_dev;
130 XilinxAXIDMAStreamSlave rx_data_dev;
131 XilinxAXIDMAStreamSlave rx_control_dev;
132
133 struct Stream streams[2];
134
135 StreamCanPushNotifyFn notify;
136 void *notify_opaque;
137};
138
139
140
141
142
143static inline int stream_desc_sof(struct SDesc *d)
144{
145 return d->control & SDESC_CTRL_SOF;
146}
147
148static inline int stream_desc_eof(struct SDesc *d)
149{
150 return d->control & SDESC_CTRL_EOF;
151}
152
153static inline int stream_resetting(struct Stream *s)
154{
155 return !!(s->regs[R_DMACR] & DMACR_RESET);
156}
157
158static inline int stream_running(struct Stream *s)
159{
160 return s->regs[R_DMACR] & DMACR_RUNSTOP;
161}
162
163static inline int stream_idle(struct Stream *s)
164{
165 return !!(s->regs[R_DMASR] & DMASR_IDLE);
166}
167
168static void stream_reset(struct Stream *s)
169{
170 s->regs[R_DMASR] = DMASR_HALTED;
171 s->regs[R_DMACR] = 1 << 16;
172}
173
174
175static inline int streamid_from_addr(hwaddr addr)
176{
177 int sid;
178
179 sid = addr / (0x30);
180 sid &= 1;
181 return sid;
182}
183
184static void stream_desc_load(struct Stream *s, hwaddr addr)
185{
186 struct SDesc *d = &s->desc;
187
188 cpu_physical_memory_read(addr, d, sizeof *d);
189
190
191 d->buffer_address = le64_to_cpu(d->buffer_address);
192 d->nxtdesc = le64_to_cpu(d->nxtdesc);
193 d->control = le32_to_cpu(d->control);
194 d->status = le32_to_cpu(d->status);
195}
196
197static void stream_desc_store(struct Stream *s, hwaddr addr)
198{
199 struct SDesc *d = &s->desc;
200
201
202 d->buffer_address = cpu_to_le64(d->buffer_address);
203 d->nxtdesc = cpu_to_le64(d->nxtdesc);
204 d->control = cpu_to_le32(d->control);
205 d->status = cpu_to_le32(d->status);
206 cpu_physical_memory_write(addr, d, sizeof *d);
207}
208
209static void stream_update_irq(struct Stream *s)
210{
211 unsigned int pending, mask, irq;
212
213 pending = s->regs[R_DMASR] & DMASR_IRQ_MASK;
214 mask = s->regs[R_DMACR] & DMASR_IRQ_MASK;
215
216 irq = pending & mask;
217
218 qemu_set_irq(s->irq, !!irq);
219}
220
221static void stream_reload_complete_cnt(struct Stream *s)
222{
223 unsigned int comp_th;
224 comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
225 s->complete_cnt = comp_th;
226}
227
228static void timer_hit(void *opaque)
229{
230 struct Stream *s = opaque;
231
232 stream_reload_complete_cnt(s);
233 s->regs[R_DMASR] |= DMASR_DLY_IRQ;
234 stream_update_irq(s);
235}
236
237static void stream_complete(struct Stream *s)
238{
239 unsigned int comp_delay;
240
241
242 comp_delay = s->regs[R_DMACR] >> 24;
243 if (comp_delay) {
244 ptimer_stop(s->ptimer);
245 ptimer_set_count(s->ptimer, comp_delay);
246 ptimer_run(s->ptimer, 1);
247 }
248
249 s->complete_cnt--;
250 if (s->complete_cnt == 0) {
251
252 s->regs[R_DMASR] |= DMASR_IOC_IRQ;
253 stream_reload_complete_cnt(s);
254 }
255}
256
257static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
258 StreamSlave *tx_control_dev)
259{
260 uint32_t prev_d;
261 unsigned int txlen;
262
263 if (!stream_running(s) || stream_idle(s)) {
264 return;
265 }
266
267 while (1) {
268 stream_desc_load(s, s->regs[R_CURDESC]);
269
270 if (s->desc.status & SDESC_STATUS_COMPLETE) {
271 s->regs[R_DMASR] |= DMASR_HALTED;
272 break;
273 }
274
275 if (stream_desc_sof(&s->desc)) {
276 s->pos = 0;
277 stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app));
278 }
279
280 txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
281 if ((txlen + s->pos) > sizeof s->txbuf) {
282 hw_error("%s: too small internal txbuf! %d\n", __func__,
283 txlen + s->pos);
284 }
285
286 cpu_physical_memory_read(s->desc.buffer_address,
287 s->txbuf + s->pos, txlen);
288 s->pos += txlen;
289
290 if (stream_desc_eof(&s->desc)) {
291 stream_push(tx_data_dev, s->txbuf, s->pos);
292 s->pos = 0;
293 stream_complete(s);
294 }
295
296
297 s->desc.status = txlen | SDESC_STATUS_COMPLETE;
298 stream_desc_store(s, s->regs[R_CURDESC]);
299
300
301 prev_d = s->regs[R_CURDESC];
302 s->regs[R_CURDESC] = s->desc.nxtdesc;
303 if (prev_d == s->regs[R_TAILDESC]) {
304 s->regs[R_DMASR] |= DMASR_IDLE;
305 break;
306 }
307 }
308}
309
310static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
311 size_t len)
312{
313 uint32_t prev_d;
314 unsigned int rxlen;
315 size_t pos = 0;
316 int sof = 1;
317
318 if (!stream_running(s) || stream_idle(s)) {
319 return 0;
320 }
321
322 while (len) {
323 stream_desc_load(s, s->regs[R_CURDESC]);
324
325 if (s->desc.status & SDESC_STATUS_COMPLETE) {
326 s->regs[R_DMASR] |= DMASR_HALTED;
327 break;
328 }
329
330 rxlen = s->desc.control & SDESC_CTRL_LEN_MASK;
331 if (rxlen > len) {
332
333 rxlen = len;
334 }
335
336 cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen);
337 len -= rxlen;
338 pos += rxlen;
339
340
341 if (!len) {
342 stream_complete(s);
343 memcpy(s->desc.app, s->app, sizeof(s->desc.app));
344 s->desc.status |= SDESC_STATUS_EOF;
345 }
346
347 s->desc.status |= sof << SDESC_STATUS_SOF_BIT;
348 s->desc.status |= SDESC_STATUS_COMPLETE;
349 stream_desc_store(s, s->regs[R_CURDESC]);
350 sof = 0;
351
352
353 prev_d = s->regs[R_CURDESC];
354 s->regs[R_CURDESC] = s->desc.nxtdesc;
355 if (prev_d == s->regs[R_TAILDESC]) {
356 s->regs[R_DMASR] |= DMASR_IDLE;
357 break;
358 }
359 }
360
361 return pos;
362}
363
364static void xilinx_axidma_reset(DeviceState *dev)
365{
366 int i;
367 XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
368
369 for (i = 0; i < 2; i++) {
370 stream_reset(&s->streams[i]);
371 }
372}
373
374static size_t
375xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
376 size_t len)
377{
378 XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
379 struct Stream *s = &cs->dma->streams[1];
380
381 if (len != CONTROL_PAYLOAD_SIZE) {
382 hw_error("AXI DMA requires %d byte control stream payload\n",
383 (int)CONTROL_PAYLOAD_SIZE);
384 }
385
386 memcpy(s->app, buf, len);
387 return len;
388}
389
390static bool
391xilinx_axidma_data_stream_can_push(StreamSlave *obj,
392 StreamCanPushNotifyFn notify,
393 void *notify_opaque)
394{
395 XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
396 struct Stream *s = &ds->dma->streams[1];
397
398 if (!stream_running(s) || stream_idle(s)) {
399 ds->dma->notify = notify;
400 ds->dma->notify_opaque = notify_opaque;
401 return false;
402 }
403
404 return true;
405}
406
407static size_t
408xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len)
409{
410 XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
411 struct Stream *s = &ds->dma->streams[1];
412 size_t ret;
413
414 ret = stream_process_s2mem(s, buf, len);
415 stream_update_irq(s);
416 return ret;
417}
418
419static uint64_t axidma_read(void *opaque, hwaddr addr,
420 unsigned size)
421{
422 XilinxAXIDMA *d = opaque;
423 struct Stream *s;
424 uint32_t r = 0;
425 int sid;
426
427 sid = streamid_from_addr(addr);
428 s = &d->streams[sid];
429
430 addr = addr % 0x30;
431 addr >>= 2;
432 switch (addr) {
433 case R_DMACR:
434
435 s->regs[addr] &= ~DMACR_RESET;
436 r = s->regs[addr];
437 break;
438 case R_DMASR:
439 s->regs[addr] &= 0xffff;
440 s->regs[addr] |= (s->complete_cnt & 0xff) << 16;
441 s->regs[addr] |= (ptimer_get_count(s->ptimer) & 0xff) << 24;
442 r = s->regs[addr];
443 break;
444 default:
445 r = s->regs[addr];
446 D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
447 __func__, sid, addr * 4, r));
448 break;
449 }
450 return r;
451
452}
453
454static void axidma_write(void *opaque, hwaddr addr,
455 uint64_t value, unsigned size)
456{
457 XilinxAXIDMA *d = opaque;
458 struct Stream *s;
459 int sid;
460
461 sid = streamid_from_addr(addr);
462 s = &d->streams[sid];
463
464 addr = addr % 0x30;
465 addr >>= 2;
466 switch (addr) {
467 case R_DMACR:
468
469 value |= DMACR_TAILPTR_MODE;
470
471 value |= (s->regs[addr] & DMACR_RESET);
472 s->regs[addr] = value;
473
474 if (value & DMACR_RESET) {
475 stream_reset(s);
476 }
477
478 if ((value & 1) && !stream_resetting(s)) {
479
480 s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);
481 }
482 stream_reload_complete_cnt(s);
483 break;
484
485 case R_DMASR:
486
487 value &= ~(value & DMASR_IRQ_MASK);
488 s->regs[addr] = value;
489 break;
490
491 case R_TAILDESC:
492 s->regs[addr] = value;
493 s->regs[R_DMASR] &= ~DMASR_IDLE;
494 if (!sid) {
495 stream_process_mem2s(s, d->tx_data_dev, d->tx_control_dev);
496 }
497 break;
498 default:
499 D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
500 __func__, sid, addr * 4, (unsigned)value));
501 s->regs[addr] = value;
502 break;
503 }
504 if (sid == 1 && d->notify) {
505 StreamCanPushNotifyFn notifytmp = d->notify;
506 d->notify = NULL;
507 notifytmp(d->notify_opaque);
508 }
509 stream_update_irq(s);
510}
511
512static const MemoryRegionOps axidma_ops = {
513 .read = axidma_read,
514 .write = axidma_write,
515 .endianness = DEVICE_NATIVE_ENDIAN,
516};
517
518static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
519{
520 XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
521 XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
522 XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
523 &s->rx_control_dev);
524 Error *local_err = NULL;
525
526 object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA,
527 (Object **)&ds->dma,
528 object_property_allow_set_link,
529 OBJ_PROP_LINK_STRONG,
530 &local_err);
531 object_property_add_link(OBJECT(cs), "dma", TYPE_XILINX_AXI_DMA,
532 (Object **)&cs->dma,
533 object_property_allow_set_link,
534 OBJ_PROP_LINK_STRONG,
535 &local_err);
536 if (local_err) {
537 goto xilinx_axidma_realize_fail;
538 }
539 object_property_set_link(OBJECT(ds), OBJECT(s), "dma", &local_err);
540 object_property_set_link(OBJECT(cs), OBJECT(s), "dma", &local_err);
541 if (local_err) {
542 goto xilinx_axidma_realize_fail;
543 }
544
545 int i;
546
547 for (i = 0; i < 2; i++) {
548 struct Stream *st = &s->streams[i];
549
550 st->nr = i;
551 st->bh = qemu_bh_new(timer_hit, st);
552 st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
553 ptimer_set_freq(st->ptimer, s->freqhz);
554 }
555 return;
556
557xilinx_axidma_realize_fail:
558 error_propagate(errp, local_err);
559}
560
561static void xilinx_axidma_init(Object *obj)
562{
563 XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
564 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
565
566 object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
567 TYPE_XILINX_AXI_DMA_DATA_STREAM);
568 object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
569 TYPE_XILINX_AXI_DMA_CONTROL_STREAM);
570 object_property_add_child(OBJECT(s), "axistream-connected-target",
571 (Object *)&s->rx_data_dev, &error_abort);
572 object_property_add_child(OBJECT(s), "axistream-control-connected-target",
573 (Object *)&s->rx_control_dev, &error_abort);
574
575 sysbus_init_irq(sbd, &s->streams[0].irq);
576 sysbus_init_irq(sbd, &s->streams[1].irq);
577
578 memory_region_init_io(&s->iomem, obj, &axidma_ops, s,
579 "xlnx.axi-dma", R_MAX * 4 * 2);
580 sysbus_init_mmio(sbd, &s->iomem);
581}
582
583static Property axidma_properties[] = {
584 DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
585 DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA,
586 tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
587 DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA,
588 tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
589 DEFINE_PROP_END_OF_LIST(),
590};
591
592static void axidma_class_init(ObjectClass *klass, void *data)
593{
594 DeviceClass *dc = DEVICE_CLASS(klass);
595
596 dc->realize = xilinx_axidma_realize,
597 dc->reset = xilinx_axidma_reset;
598 dc->props = axidma_properties;
599}
600
601static StreamSlaveClass xilinx_axidma_data_stream_class = {
602 .push = xilinx_axidma_data_stream_push,
603 .can_push = xilinx_axidma_data_stream_can_push,
604};
605
606static StreamSlaveClass xilinx_axidma_control_stream_class = {
607 .push = xilinx_axidma_control_stream_push,
608};
609
610static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data)
611{
612 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
613
614 ssc->push = ((StreamSlaveClass *)data)->push;
615 ssc->can_push = ((StreamSlaveClass *)data)->can_push;
616}
617
618static const TypeInfo axidma_info = {
619 .name = TYPE_XILINX_AXI_DMA,
620 .parent = TYPE_SYS_BUS_DEVICE,
621 .instance_size = sizeof(XilinxAXIDMA),
622 .class_init = axidma_class_init,
623 .instance_init = xilinx_axidma_init,
624};
625
626static const TypeInfo xilinx_axidma_data_stream_info = {
627 .name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
628 .parent = TYPE_OBJECT,
629 .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
630 .class_init = xilinx_axidma_stream_class_init,
631 .class_data = &xilinx_axidma_data_stream_class,
632 .interfaces = (InterfaceInfo[]) {
633 { TYPE_STREAM_SLAVE },
634 { }
635 }
636};
637
638static const TypeInfo xilinx_axidma_control_stream_info = {
639 .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
640 .parent = TYPE_OBJECT,
641 .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
642 .class_init = xilinx_axidma_stream_class_init,
643 .class_data = &xilinx_axidma_control_stream_class,
644 .interfaces = (InterfaceInfo[]) {
645 { TYPE_STREAM_SLAVE },
646 { }
647 }
648};
649
650static void xilinx_axidma_register_types(void)
651{
652 type_register_static(&axidma_info);
653 type_register_static(&xilinx_axidma_data_stream_info);
654 type_register_static(&xilinx_axidma_control_stream_info);
655}
656
657type_init(xilinx_axidma_register_types)
658