LXR qemu/hw/gpio/puv3

   1/*
   2 * GPIO device simulation in PKUnity SoC
   3 *
   4 * Copyright (C) 2010-2012 Guan Xuetao
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation, or any later version.
   9 * See the COPYING file in the top-level directory.
  10 */
  11
  12#include "qemu/osdep.h"
  13#include "hw/hw.h"
  14#include "hw/sysbus.h"
  15
  16#undef DEBUG_PUV3
  17#include "hw/unicore32/puv3.h"
  18#include "qemu/module.h"
  19
  20#define TYPE_PUV3_GPIO "puv3_gpio"
  21#define PUV3_GPIO(obj) OBJECT_CHECK(PUV3GPIOState, (obj), TYPE_PUV3_GPIO)
  22
  23typedef struct PUV3GPIOState {
  24    SysBusDevice parent_obj;
  25
  26    MemoryRegion iomem;
  27    qemu_irq irq[9];
  28
  29    uint32_t reg_GPLR;
  30    uint32_t reg_GPDR;
  31    uint32_t reg_GPIR;
  32} PUV3GPIOState;
  33
  34static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
  35        unsigned size)
  36{
  37    PUV3GPIOState *s = opaque;
  38    uint32_t ret = 0;
  39
  40    switch (offset) {
  41    case 0x00:
  42        ret = s->reg_GPLR;
  43        break;
  44    case 0x04:
  45        ret = s->reg_GPDR;
  46        break;
  47    case 0x20:
  48        ret = s->reg_GPIR;
  49        break;
  50    default:
  51        DPRINTF("Bad offset 0x%x\n", offset);
  52    }
  53    DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  54
  55    return ret;
  56}
  57
  58static void puv3_gpio_write(void *opaque, hwaddr offset,
  59        uint64_t value, unsigned size)
  60{
  61    PUV3GPIOState *s = opaque;
  62
  63    DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  64    switch (offset) {
  65    case 0x04:
  66        s->reg_GPDR = value;
  67        break;
  68    case 0x08:
  69        if (s->reg_GPDR & value) {
  70            s->reg_GPLR |= value;
  71        } else {
  72            DPRINTF("Write gpio input port error!");
  73        }
  74        break;
  75    case 0x0c:
  76        if (s->reg_GPDR & value) {
  77            s->reg_GPLR &= ~value;
  78        } else {
  79            DPRINTF("Write gpio input port error!");
  80        }
  81        break;
  82    case 0x10: /* GRER */
  83    case 0x14: /* GFER */
  84    case 0x18: /* GEDR */
  85        break;
  86    case 0x20: /* GPIR */
  87        s->reg_GPIR = value;
  88        break;
  89    default:
  90        DPRINTF("Bad offset 0x%x\n", offset);
  91    }
  92}
  93
  94static const MemoryRegionOps puv3_gpio_ops = {
  95    .read = puv3_gpio_read,
  96    .write = puv3_gpio_write,
  97    .impl = {
  98        .min_access_size = 4,
  99        .max_access_size = 4,
 100    },
 101    .endianness = DEVICE_NATIVE_ENDIAN,
 102};
 103
 104static void puv3_gpio_realize(DeviceState *dev, Error **errp)
 105{
 106    PUV3GPIOState *s = PUV3_GPIO(dev);
 107    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 108
 109    s->reg_GPLR = 0;
 110    s->reg_GPDR = 0;
 111
 112    /* FIXME: these irqs not handled yet */
 113    sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW0]);
 114    sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW1]);
 115    sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW2]);
 116    sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW3]);
 117    sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW4]);
 118    sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW5]);
 119    sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW6]);
 120    sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW7]);
 121    sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOHIGH]);
 122
 123    memory_region_init_io(&s->iomem, OBJECT(s), &puv3_gpio_ops, s, "puv3_gpio",
 124            PUV3_REGS_OFFSET);
 125    sysbus_init_mmio(sbd, &s->iomem);
 126}
 127
 128static void puv3_gpio_class_init(ObjectClass *klass, void *data)
 129{
 130    DeviceClass *dc = DEVICE_CLASS(klass);
 131
 132    dc->realize = puv3_gpio_realize;
 133}
 134
 135static const TypeInfo puv3_gpio_info = {
 136    .name = TYPE_PUV3_GPIO,
 137    .parent = TYPE_SYS_BUS_DEVICE,
 138    .instance_size = sizeof(PUV3GPIOState),
 139    .class_init = puv3_gpio_class_init,
 140};
 141
 142static void puv3_gpio_register_type(void)
 143{
 144    type_register_static(&puv3_gpio_info);
 145}
 146
 147type_init(puv3_gpio_register_type)
 148