LXR qemu/hw/i2c/smbus

   1/*
   2 * ACPI implementation
   3 *
   4 * Copyright (c) 2006 Fabrice Bellard
   5 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   6 *               VA Linux Systems Japan K.K.
   7 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License, or
  12 * (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17 * General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, see <http://www.gnu.org/licenses/>
  21 */
  22
  23#include "qemu/osdep.h"
  24#include "hw/hw.h"
  25#include "hw/i2c/pm_smbus.h"
  26#include "hw/pci/pci.h"
  27#include "qemu/module.h"
  28#include "sysemu/sysemu.h"
  29
  30#include "hw/i386/ich9.h"
  31
  32#define ICH9_SMB_DEVICE(obj) \
  33     OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE)
  34
  35typedef struct ICH9SMBState {
  36    PCIDevice dev;
  37
  38    bool irq_enabled;
  39
  40    PMSMBus smb;
  41} ICH9SMBState;
  42
  43static bool ich9_vmstate_need_smbus(void *opaque, int version_id)
  44{
  45    return pm_smbus_vmstate_needed();
  46}
  47
  48static const VMStateDescription vmstate_ich9_smbus = {
  49    .name = "ich9_smb",
  50    .version_id = 1,
  51    .minimum_version_id = 1,
  52    .fields = (VMStateField[]) {
  53        VMSTATE_PCI_DEVICE(dev, ICH9SMBState),
  54        VMSTATE_BOOL_TEST(irq_enabled, ICH9SMBState, ich9_vmstate_need_smbus),
  55        VMSTATE_STRUCT_TEST(smb, ICH9SMBState, ich9_vmstate_need_smbus, 1,
  56                            pmsmb_vmstate, PMSMBus),
  57        VMSTATE_END_OF_LIST()
  58    }
  59};
  60
  61static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
  62                                    uint32_t val, int len)
  63{
  64    ICH9SMBState *s = ICH9_SMB_DEVICE(d);
  65
  66    pci_default_write_config(d, address, val, len);
  67    if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) {
  68        uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
  69        if (hostc & ICH9_SMB_HOSTC_HST_EN) {
  70            memory_region_set_enabled(&s->smb.io, true);
  71        } else {
  72            memory_region_set_enabled(&s->smb.io, false);
  73        }
  74        s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0;
  75        if (hostc & ICH9_SMB_HOSTC_SSRESET) {
  76            s->smb.reset(&s->smb);
  77            s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET;
  78        }
  79    }
  80}
  81
  82static void ich9_smbus_realize(PCIDevice *d, Error **errp)
  83{
  84    ICH9SMBState *s = ICH9_SMB_DEVICE(d);
  85
  86    /* TODO? D31IP.SMIP in chipset configuration space */
  87    pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
  88
  89    pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
  90    /* TODO bar0, bar1: 64bit BAR support*/
  91
  92    pm_smbus_init(&d->qdev, &s->smb, false);
  93    pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
  94                     &s->smb.io);
  95}
  96
  97static void ich9_smb_class_init(ObjectClass *klass, void *data)
  98{
  99    DeviceClass *dc = DEVICE_CLASS(klass);
 100    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 101
 102    k->vendor_id = PCI_VENDOR_ID_INTEL;
 103    k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
 104    k->revision = ICH9_A2_SMB_REVISION;
 105    k->class_id = PCI_CLASS_SERIAL_SMBUS;
 106    dc->vmsd = &vmstate_ich9_smbus;
 107    dc->desc = "ICH9 SMBUS Bridge";
 108    k->realize = ich9_smbus_realize;
 109    k->config_write = ich9_smbus_write_config;
 110    /*
 111     * Reason: part of ICH9 southbridge, needs to be wired up by
 112     * pc_q35_init()
 113     */
 114    dc->user_creatable = false;
 115}
 116
 117static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
 118{
 119    ICH9SMBState *s = pmsmb->opaque;
 120
 121    if (enabled == s->irq_enabled) {
 122        return;
 123    }
 124
 125    s->irq_enabled = enabled;
 126    pci_set_irq(&s->dev, enabled);
 127}
 128
 129I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
 130{
 131    PCIDevice *d =
 132        pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
 133    ICH9SMBState *s = ICH9_SMB_DEVICE(d);
 134    s->smb.set_irq = ich9_smb_set_irq;
 135    s->smb.opaque = s;
 136    return s->smb.smbus;
 137}
 138
 139static const TypeInfo ich9_smb_info = {
 140    .name   = TYPE_ICH9_SMB_DEVICE,
 141    .parent = TYPE_PCI_DEVICE,
 142    .instance_size = sizeof(ICH9SMBState),
 143    .class_init = ich9_smb_class_init,
 144    .interfaces = (InterfaceInfo[]) {
 145        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 146        { },
 147    },
 148};
 149
 150static void ich9_smb_register(void)
 151{
 152    type_register_static(&ich9_smb_info);
 153}
 154
 155type_init(ich9_smb_register);
 156