LXR qemu/hw/i386/amd

   1/*
   2 * QEMU emulation of an AMD IOMMU (AMD-Vi)
   3 *
   4 * Copyright (C) 2011 Eduard - Gabriel Munteanu
   5 * Copyright (C) 2015, 2016 David Kiarie Kahurani
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16
  17 * You should have received a copy of the GNU General Public License along
  18 * with this program; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#ifndef AMD_IOMMU_H
  22#define AMD_IOMMU_H
  23
  24#include "hw/hw.h"
  25#include "hw/pci/pci.h"
  26#include "hw/i386/x86-iommu.h"
  27
  28/* Capability registers */
  29#define AMDVI_CAPAB_BAR_LOW           0x04
  30#define AMDVI_CAPAB_BAR_HIGH          0x08
  31#define AMDVI_CAPAB_RANGE             0x0C
  32#define AMDVI_CAPAB_MISC              0x10
  33
  34#define AMDVI_CAPAB_SIZE              0x18
  35#define AMDVI_CAPAB_REG_SIZE          0x04
  36
  37/* Capability header data */
  38#define AMDVI_CAPAB_ID_SEC            0xf
  39#define AMDVI_CAPAB_FLAT_EXT          (1 << 28)
  40#define AMDVI_CAPAB_EFR_SUP           (1 << 27)
  41#define AMDVI_CAPAB_FLAG_NPCACHE      (1 << 26)
  42#define AMDVI_CAPAB_FLAG_HTTUNNEL     (1 << 25)
  43#define AMDVI_CAPAB_FLAG_IOTLBSUP     (1 << 24)
  44#define AMDVI_CAPAB_INIT_TYPE         (3 << 16)
  45
  46/* No. of used MMIO registers */
  47#define AMDVI_MMIO_REGS_HIGH  7
  48#define AMDVI_MMIO_REGS_LOW   8
  49
  50/* MMIO registers */
  51#define AMDVI_MMIO_DEVICE_TABLE       0x0000
  52#define AMDVI_MMIO_COMMAND_BASE       0x0008
  53#define AMDVI_MMIO_EVENT_BASE         0x0010
  54#define AMDVI_MMIO_CONTROL            0x0018
  55#define AMDVI_MMIO_EXCL_BASE          0x0020
  56#define AMDVI_MMIO_EXCL_LIMIT         0x0028
  57#define AMDVI_MMIO_EXT_FEATURES       0x0030
  58#define AMDVI_MMIO_COMMAND_HEAD       0x2000
  59#define AMDVI_MMIO_COMMAND_TAIL       0x2008
  60#define AMDVI_MMIO_EVENT_HEAD         0x2010
  61#define AMDVI_MMIO_EVENT_TAIL         0x2018
  62#define AMDVI_MMIO_STATUS             0x2020
  63#define AMDVI_MMIO_PPR_BASE           0x0038
  64#define AMDVI_MMIO_PPR_HEAD           0x2030
  65#define AMDVI_MMIO_PPR_TAIL           0x2038
  66
  67#define AMDVI_MMIO_SIZE               0x4000
  68
  69#define AMDVI_MMIO_DEVTAB_SIZE_MASK   ((1ULL << 12) - 1)
  70#define AMDVI_MMIO_DEVTAB_BASE_MASK   (((1ULL << 52) - 1) & ~ \
  71                                       AMDVI_MMIO_DEVTAB_SIZE_MASK)
  72#define AMDVI_MMIO_DEVTAB_ENTRY_SIZE  32
  73#define AMDVI_MMIO_DEVTAB_SIZE_UNIT   4096
  74
  75/* some of this are similar but just for readability */
  76#define AMDVI_MMIO_CMDBUF_SIZE_BYTE       (AMDVI_MMIO_COMMAND_BASE + 7)
  77#define AMDVI_MMIO_CMDBUF_SIZE_MASK       0x0f
  78#define AMDVI_MMIO_CMDBUF_BASE_MASK       AMDVI_MMIO_DEVTAB_BASE_MASK
  79#define AMDVI_MMIO_CMDBUF_HEAD_MASK       (((1ULL << 19) - 1) & ~0x0f)
  80#define AMDVI_MMIO_CMDBUF_TAIL_MASK       AMDVI_MMIO_EVTLOG_HEAD_MASK
  81
  82#define AMDVI_MMIO_EVTLOG_SIZE_BYTE       (AMDVI_MMIO_EVENT_BASE + 7)
  83#define AMDVI_MMIO_EVTLOG_SIZE_MASK       AMDVI_MMIO_CMDBUF_SIZE_MASK
  84#define AMDVI_MMIO_EVTLOG_BASE_MASK       AMDVI_MMIO_CMDBUF_BASE_MASK
  85#define AMDVI_MMIO_EVTLOG_HEAD_MASK       (((1ULL << 19) - 1) & ~0x0f)
  86#define AMDVI_MMIO_EVTLOG_TAIL_MASK       AMDVI_MMIO_EVTLOG_HEAD_MASK
  87
  88#define AMDVI_MMIO_PPRLOG_SIZE_BYTE       (AMDVI_MMIO_EVENT_BASE + 7)
  89#define AMDVI_MMIO_PPRLOG_HEAD_MASK       AMDVI_MMIO_EVTLOG_HEAD_MASK
  90#define AMDVI_MMIO_PPRLOG_TAIL_MASK       AMDVI_MMIO_EVTLOG_HEAD_MASK
  91#define AMDVI_MMIO_PPRLOG_BASE_MASK       AMDVI_MMIO_EVTLOG_BASE_MASK
  92#define AMDVI_MMIO_PPRLOG_SIZE_MASK       AMDVI_MMIO_EVTLOG_SIZE_MASK
  93
  94#define AMDVI_MMIO_EXCL_ENABLED_MASK      (1ULL << 0)
  95#define AMDVI_MMIO_EXCL_ALLOW_MASK        (1ULL << 1)
  96#define AMDVI_MMIO_EXCL_LIMIT_MASK        AMDVI_MMIO_DEVTAB_BASE_MASK
  97#define AMDVI_MMIO_EXCL_LIMIT_LOW         0xfff
  98
  99/* mmio control register flags */
 100#define AMDVI_MMIO_CONTROL_AMDVIEN        (1ULL << 0)
 101#define AMDVI_MMIO_CONTROL_HTTUNEN        (1ULL << 1)
 102#define AMDVI_MMIO_CONTROL_EVENTLOGEN     (1ULL << 2)
 103#define AMDVI_MMIO_CONTROL_EVENTINTEN     (1ULL << 3)
 104#define AMDVI_MMIO_CONTROL_COMWAITINTEN   (1ULL << 4)
 105#define AMDVI_MMIO_CONTROL_CMDBUFLEN      (1ULL << 12)
 106#define AMDVI_MMIO_CONTROL_GAEN           (1ULL << 17)
 107
 108/* MMIO status register bits */
 109#define AMDVI_MMIO_STATUS_CMDBUF_RUN  (1 << 4)
 110#define AMDVI_MMIO_STATUS_EVT_RUN     (1 << 3)
 111#define AMDVI_MMIO_STATUS_COMP_INT    (1 << 2)
 112#define AMDVI_MMIO_STATUS_EVT_OVF     (1 << 0)
 113
 114#define AMDVI_CMDBUF_ID_BYTE              0x07
 115#define AMDVI_CMDBUF_ID_RSHIFT            4
 116
 117#define AMDVI_CMD_COMPLETION_WAIT         0x01
 118#define AMDVI_CMD_INVAL_DEVTAB_ENTRY      0x02
 119#define AMDVI_CMD_INVAL_AMDVI_PAGES       0x03
 120#define AMDVI_CMD_INVAL_IOTLB_PAGES       0x04
 121#define AMDVI_CMD_INVAL_INTR_TABLE        0x05
 122#define AMDVI_CMD_PREFETCH_AMDVI_PAGES    0x06
 123#define AMDVI_CMD_COMPLETE_PPR_REQUEST    0x07
 124#define AMDVI_CMD_INVAL_AMDVI_ALL         0x08
 125
 126#define AMDVI_DEVTAB_ENTRY_SIZE           32
 127
 128/* Device table entry bits 0:63 */
 129#define AMDVI_DEV_VALID                   (1ULL << 0)
 130#define AMDVI_DEV_TRANSLATION_VALID       (1ULL << 1)
 131#define AMDVI_DEV_MODE_MASK               0x7
 132#define AMDVI_DEV_MODE_RSHIFT             9
 133#define AMDVI_DEV_PT_ROOT_MASK            0xffffffffff000
 134#define AMDVI_DEV_PT_ROOT_RSHIFT          12
 135#define AMDVI_DEV_PERM_SHIFT              61
 136#define AMDVI_DEV_PERM_READ               (1ULL << 61)
 137#define AMDVI_DEV_PERM_WRITE              (1ULL << 62)
 138
 139/* Device table entry bits 64:127 */
 140#define AMDVI_DEV_DOMID_ID_MASK          ((1ULL << 16) - 1)
 141
 142/* Event codes and flags, as stored in the info field */
 143#define AMDVI_EVENT_ILLEGAL_DEVTAB_ENTRY  (0x1U << 12)
 144#define AMDVI_EVENT_IOPF                  (0x2U << 12)
 145#define   AMDVI_EVENT_IOPF_I              (1U << 3)
 146#define AMDVI_EVENT_DEV_TAB_HW_ERROR      (0x3U << 12)
 147#define AMDVI_EVENT_PAGE_TAB_HW_ERROR     (0x4U << 12)
 148#define AMDVI_EVENT_ILLEGAL_COMMAND_ERROR (0x5U << 12)
 149#define AMDVI_EVENT_COMMAND_HW_ERROR      (0x6U << 12)
 150
 151#define AMDVI_EVENT_LEN                  16
 152#define AMDVI_PERM_READ             (1 << 0)
 153#define AMDVI_PERM_WRITE            (1 << 1)
 154
 155#define AMDVI_FEATURE_PREFETCH            (1ULL << 0) /* page prefetch       */
 156#define AMDVI_FEATURE_PPR                 (1ULL << 1) /* PPR Support         */
 157#define AMDVI_FEATURE_GT                  (1ULL << 4) /* Guest Translation   */
 158#define AMDVI_FEATURE_IA                  (1ULL << 6) /* inval all support   */
 159#define AMDVI_FEATURE_GA                  (1ULL << 7) /* guest VAPIC support */
 160#define AMDVI_FEATURE_HE                  (1ULL << 8) /* hardware error regs */
 161#define AMDVI_FEATURE_PC                  (1ULL << 9) /* Perf counters       */
 162
 163/* reserved DTE bits */
 164#define AMDVI_DTE_LOWER_QUAD_RESERVED  0x80300000000000fc
 165#define AMDVI_DTE_MIDDLE_QUAD_RESERVED 0x0000000000000100
 166#define AMDVI_DTE_UPPER_QUAD_RESERVED  0x08f0000000000000
 167
 168/* AMDVI paging mode */
 169#define AMDVI_GATS_MODE                 (2ULL <<  12)
 170#define AMDVI_HATS_MODE                 (2ULL <<  10)
 171
 172/* IOTLB */
 173#define AMDVI_IOTLB_MAX_SIZE 1024
 174#define AMDVI_DEVID_SHIFT    36
 175
 176/* extended feature support */
 177#define AMDVI_EXT_FEATURES (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \
 178        AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \
 179        AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA)
 180
 181/* capabilities header */
 182#define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \
 183        AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \
 184        | AMDVI_CAPAB_ID_SEC | AMDVI_CAPAB_INIT_TYPE | \
 185        AMDVI_CAPAB_FLAG_HTTUNNEL |  AMDVI_CAPAB_EFR_SUP)
 186
 187/* AMDVI default address */
 188#define AMDVI_BASE_ADDR 0xfed80000
 189
 190/* page management constants */
 191#define AMDVI_PAGE_SHIFT 12
 192#define AMDVI_PAGE_SIZE  (1ULL << AMDVI_PAGE_SHIFT)
 193
 194#define AMDVI_PAGE_SHIFT_4K 12
 195#define AMDVI_PAGE_MASK_4K  (~((1ULL << AMDVI_PAGE_SHIFT_4K) - 1))
 196
 197#define AMDVI_MAX_VA_ADDR          (48UL << 5)
 198#define AMDVI_MAX_PH_ADDR          (40UL << 8)
 199#define AMDVI_MAX_GVA_ADDR         (48UL << 15)
 200
 201/* Completion Wait data size */
 202#define AMDVI_COMPLETION_DATA_SIZE    8
 203
 204#define AMDVI_COMMAND_SIZE   16
 205/* Completion Wait data size */
 206#define AMDVI_COMPLETION_DATA_SIZE    8
 207
 208#define AMDVI_COMMAND_SIZE   16
 209
 210#define AMDVI_INT_ADDR_FIRST    0xfee00000
 211#define AMDVI_INT_ADDR_LAST     0xfeefffff
 212#define AMDVI_INT_ADDR_SIZE     (AMDVI_INT_ADDR_LAST - AMDVI_INT_ADDR_FIRST + 1)
 213#define AMDVI_MSI_ADDR_HI_MASK  (0xffffffff00000000ULL)
 214#define AMDVI_MSI_ADDR_LO_MASK  (0x00000000ffffffffULL)
 215
 216/* SB IOAPIC is always on this device in AMD systems */
 217#define AMDVI_IOAPIC_SB_DEVID   PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
 218
 219/* Interrupt remapping errors */
 220#define AMDVI_IR_ERR            0x1
 221#define AMDVI_IR_GET_IRTE       0x2
 222#define AMDVI_IR_TARGET_ABORT   0x3
 223
 224/* Interrupt remapping */
 225#define AMDVI_IR_REMAP_ENABLE           1ULL
 226#define AMDVI_IR_INTCTL_SHIFT           60
 227#define AMDVI_IR_INTCTL_ABORT           0
 228#define AMDVI_IR_INTCTL_PASS            1
 229#define AMDVI_IR_INTCTL_REMAP           2
 230
 231#define AMDVI_IR_PHYS_ADDR_MASK         (((1ULL << 45) - 1) << 6)
 232
 233/* MSI data 10:0 bits (section 2.2.5.1 Fig 14) */
 234#define AMDVI_IRTE_OFFSET               0x7ff
 235
 236/* Delivery mode of MSI data (same as IOAPIC deilver mode encoding) */
 237#define AMDVI_IOAPIC_INT_TYPE_FIXED          0x0
 238#define AMDVI_IOAPIC_INT_TYPE_ARBITRATED     0x1
 239#define AMDVI_IOAPIC_INT_TYPE_SMI            0x2
 240#define AMDVI_IOAPIC_INT_TYPE_NMI            0x4
 241#define AMDVI_IOAPIC_INT_TYPE_INIT           0x5
 242#define AMDVI_IOAPIC_INT_TYPE_EINT           0x7
 243
 244/* Pass through interrupt */
 245#define AMDVI_DEV_INT_PASS_MASK         (1ULL << 56)
 246#define AMDVI_DEV_EINT_PASS_MASK        (1ULL << 57)
 247#define AMDVI_DEV_NMI_PASS_MASK         (1ULL << 58)
 248#define AMDVI_DEV_LINT0_PASS_MASK       (1ULL << 62)
 249#define AMDVI_DEV_LINT1_PASS_MASK       (1ULL << 63)
 250
 251/* Interrupt remapping table fields (Guest VAPIC not enabled) */
 252union irte {
 253    uint32_t val;
 254    struct {
 255        uint32_t valid:1,
 256                 no_fault:1,
 257                 int_type:3,
 258                 rq_eoi:1,
 259                 dm:1,
 260                 guest_mode:1,
 261                 destination:8,
 262                 vector:8,
 263                 rsvd:8;
 264    } fields;
 265};
 266
 267/* Interrupt remapping table fields (Guest VAPIC is enabled) */
 268union irte_ga_lo {
 269  uint64_t val;
 270
 271  /* For int remapping */
 272  struct {
 273      uint64_t  valid:1,
 274                no_fault:1,
 275                /* ------ */
 276                int_type:3,
 277                rq_eoi:1,
 278                dm:1,
 279                /* ------ */
 280                guest_mode:1,
 281                destination:8,
 282                rsvd_1:48;
 283  } fields_remap;
 284};
 285
 286union irte_ga_hi {
 287  uint64_t val;
 288  struct {
 289      uint64_t  vector:8,
 290                rsvd_2:56;
 291  } fields;
 292};
 293
 294struct irte_ga {
 295  union irte_ga_lo lo;
 296  union irte_ga_hi hi;
 297};
 298
 299#define TYPE_AMD_IOMMU_DEVICE "amd-iommu"
 300#define AMD_IOMMU_DEVICE(obj)\
 301    OBJECT_CHECK(AMDVIState, (obj), TYPE_AMD_IOMMU_DEVICE)
 302
 303#define TYPE_AMD_IOMMU_PCI "AMDVI-PCI"
 304
 305#define TYPE_AMD_IOMMU_MEMORY_REGION "amd-iommu-iommu-memory-region"
 306
 307typedef struct AMDVIAddressSpace AMDVIAddressSpace;
 308
 309/* functions to steal PCI config space */
 310typedef struct AMDVIPCIState {
 311    PCIDevice dev;               /* The PCI device itself        */
 312} AMDVIPCIState;
 313
 314typedef struct AMDVIState {
 315    X86IOMMUState iommu;        /* IOMMU bus device             */
 316    AMDVIPCIState pci;          /* IOMMU PCI device             */
 317
 318    uint32_t version;
 319    uint32_t capab_offset;       /* capability offset pointer    */
 320
 321    uint64_t mmio_addr;
 322
 323    uint32_t devid;              /* auto-assigned devid          */
 324
 325    bool enabled;                /* IOMMU enabled                */
 326    bool ats_enabled;            /* address translation enabled  */
 327    bool cmdbuf_enabled;         /* command buffer enabled       */
 328    bool evtlog_enabled;         /* event log enabled            */
 329    bool excl_enabled;
 330
 331    hwaddr devtab;               /* base address device table    */
 332    size_t devtab_len;           /* device table length          */
 333
 334    hwaddr cmdbuf;               /* command buffer base address  */
 335    uint64_t cmdbuf_len;         /* command buffer length        */
 336    uint32_t cmdbuf_head;        /* current IOMMU read position  */
 337    uint32_t cmdbuf_tail;        /* next Software write position */
 338    bool completion_wait_intr;
 339
 340    hwaddr evtlog;               /* base address event log       */
 341    bool evtlog_intr;
 342    uint32_t evtlog_len;         /* event log length             */
 343    uint32_t evtlog_head;        /* current IOMMU write position */
 344    uint32_t evtlog_tail;        /* current Software read position */
 345
 346    /* unused for now */
 347    hwaddr excl_base;            /* base DVA - IOMMU exclusion range */
 348    hwaddr excl_limit;           /* limit of IOMMU exclusion range   */
 349    bool excl_allow;             /* translate accesses to the exclusion range */
 350    bool excl_enable;            /* exclusion range enabled          */
 351
 352    hwaddr ppr_log;              /* base address ppr log */
 353    uint32_t pprlog_len;         /* ppr log len  */
 354    uint32_t pprlog_head;        /* ppr log head */
 355    uint32_t pprlog_tail;        /* ppr log tail */
 356
 357    MemoryRegion mmio;                 /* MMIO region                  */
 358    uint8_t mmior[AMDVI_MMIO_SIZE];    /* read/write MMIO              */
 359    uint8_t w1cmask[AMDVI_MMIO_SIZE];  /* read/write 1 clear mask      */
 360    uint8_t romask[AMDVI_MMIO_SIZE];   /* MMIO read/only mask          */
 361    bool mmio_enabled;
 362
 363    /* for each served device */
 364    AMDVIAddressSpace **address_spaces[PCI_BUS_MAX];
 365
 366    /* IOTLB */
 367    GHashTable *iotlb;
 368
 369    /* Interrupt remapping */
 370    bool ga_enabled;
 371} AMDVIState;
 372
 373#endif
 374