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26#include "qemu/osdep.h"
27#include "hw/hw.h"
28#include "hw/pci/pci.h"
29#include "qemu/module.h"
30#include "hw/isa/isa.h"
31#include "sysemu/sysemu.h"
32#include "sysemu/dma.h"
33
34#include "hw/ide/pci.h"
35#include "trace.h"
36
37
38#define CFR 0x50
39#define CFR_INTR_CH0 0x04
40#define CNTRL 0x51
41#define CNTRL_EN_CH0 0x04
42#define CNTRL_EN_CH1 0x08
43#define ARTTIM23 0x57
44#define ARTTIM23_INTR_CH1 0x10
45#define MRDMODE 0x71
46#define MRDMODE_INTR_CH0 0x04
47#define MRDMODE_INTR_CH1 0x08
48#define MRDMODE_BLK_CH0 0x10
49#define MRDMODE_BLK_CH1 0x20
50#define UDIDETCR0 0x73
51#define UDIDETCR1 0x7B
52
53static void cmd646_update_irq(PCIDevice *pd);
54
55static void cmd646_update_dma_interrupts(PCIDevice *pd)
56{
57
58 if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
59 pd->config[CFR] |= CFR_INTR_CH0;
60 } else {
61 pd->config[CFR] &= ~CFR_INTR_CH0;
62 }
63
64 if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
65 pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
66 } else {
67 pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
68 }
69}
70
71static void cmd646_update_udma_interrupts(PCIDevice *pd)
72{
73
74 if (pd->config[CFR] & CFR_INTR_CH0) {
75 pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
76 } else {
77 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
78 }
79
80 if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
81 pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
82 } else {
83 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
84 }
85}
86
87static uint64_t bmdma_read(void *opaque, hwaddr addr,
88 unsigned size)
89{
90 BMDMAState *bm = opaque;
91 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
92 uint32_t val;
93
94 if (size != 1) {
95 return ((uint64_t)1 << (size * 8)) - 1;
96 }
97
98 switch(addr & 3) {
99 case 0:
100 val = bm->cmd;
101 break;
102 case 1:
103 val = pci_dev->config[MRDMODE];
104 break;
105 case 2:
106 val = bm->status;
107 break;
108 case 3:
109 if (bm == &bm->pci_dev->bmdma[0]) {
110 val = pci_dev->config[UDIDETCR0];
111 } else {
112 val = pci_dev->config[UDIDETCR1];
113 }
114 break;
115 default:
116 val = 0xff;
117 break;
118 }
119
120 trace_bmdma_read_cmd646(addr, val);
121 return val;
122}
123
124static void bmdma_write(void *opaque, hwaddr addr,
125 uint64_t val, unsigned size)
126{
127 BMDMAState *bm = opaque;
128 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
129
130 if (size != 1) {
131 return;
132 }
133
134 trace_bmdma_write_cmd646(addr, val);
135 switch(addr & 3) {
136 case 0:
137 bmdma_cmd_writeb(bm, val);
138 break;
139 case 1:
140 pci_dev->config[MRDMODE] =
141 (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
142 cmd646_update_dma_interrupts(pci_dev);
143 cmd646_update_irq(pci_dev);
144 break;
145 case 2:
146 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
147 break;
148 case 3:
149 if (bm == &bm->pci_dev->bmdma[0]) {
150 pci_dev->config[UDIDETCR0] = val;
151 } else {
152 pci_dev->config[UDIDETCR1] = val;
153 }
154 break;
155 }
156}
157
158static const MemoryRegionOps cmd646_bmdma_ops = {
159 .read = bmdma_read,
160 .write = bmdma_write,
161};
162
163static void bmdma_setup_bar(PCIIDEState *d)
164{
165 BMDMAState *bm;
166 int i;
167
168 memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
169 for(i = 0;i < 2; i++) {
170 bm = &d->bmdma[i];
171 memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
172 "cmd646-bmdma-bus", 4);
173 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
174 memory_region_init_io(&bm->addr_ioport, OBJECT(d),
175 &bmdma_addr_ioport_ops, bm,
176 "cmd646-bmdma-ioport", 4);
177 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
178 }
179}
180
181static void cmd646_update_irq(PCIDevice *pd)
182{
183 int pci_level;
184
185 pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
186 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
187 ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
188 !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
189 pci_set_irq(pd, pci_level);
190}
191
192
193static void cmd646_set_irq(void *opaque, int channel, int level)
194{
195 PCIIDEState *d = opaque;
196 PCIDevice *pd = PCI_DEVICE(d);
197 int irq_mask;
198
199 irq_mask = MRDMODE_INTR_CH0 << channel;
200 if (level) {
201 pd->config[MRDMODE] |= irq_mask;
202 } else {
203 pd->config[MRDMODE] &= ~irq_mask;
204 }
205 cmd646_update_dma_interrupts(pd);
206 cmd646_update_irq(pd);
207}
208
209static void cmd646_reset(void *opaque)
210{
211 PCIIDEState *d = opaque;
212 unsigned int i;
213
214 for (i = 0; i < 2; i++) {
215 ide_bus_reset(&d->bus[i]);
216 }
217}
218
219static uint32_t cmd646_pci_config_read(PCIDevice *d,
220 uint32_t address, int len)
221{
222 return pci_default_read_config(d, address, len);
223}
224
225static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
226 int l)
227{
228 uint32_t i;
229
230 pci_default_write_config(d, addr, val, l);
231
232 for (i = addr; i < addr + l; i++) {
233 switch (i) {
234 case CFR:
235 case ARTTIM23:
236 cmd646_update_udma_interrupts(d);
237 break;
238 case MRDMODE:
239 cmd646_update_dma_interrupts(d);
240 break;
241 }
242 }
243
244 cmd646_update_irq(d);
245}
246
247
248static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
249{
250 PCIIDEState *d = PCI_IDE(dev);
251 uint8_t *pci_conf = dev->config;
252 qemu_irq *irq;
253 int i;
254
255 pci_conf[PCI_CLASS_PROG] = 0x8f;
256
257 pci_conf[CNTRL] = CNTRL_EN_CH0;
258 if (d->secondary) {
259
260 pci_conf[CNTRL] |= CNTRL_EN_CH1;
261 }
262
263
264 dev->wmask[CFR] = 0x0;
265 dev->w1cmask[CFR] = CFR_INTR_CH0;
266 dev->wmask[ARTTIM23] = 0x0;
267 dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
268 dev->wmask[MRDMODE] = 0x0;
269 dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;
270
271 memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
272 &d->bus[0], "cmd646-data0", 8);
273 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
274
275 memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
276 &d->bus[0], "cmd646-cmd0", 4);
277 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
278
279 memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
280 &d->bus[1], "cmd646-data1", 8);
281 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
282
283 memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
284 &d->bus[1], "cmd646-cmd1", 4);
285 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
286
287 bmdma_setup_bar(d);
288 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
289
290
291 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
292
293 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
294 for (i = 0; i < 2; i++) {
295 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
296 ide_init2(&d->bus[i], irq[i]);
297
298 bmdma_init(&d->bus[i], &d->bmdma[i], d);
299 d->bmdma[i].bus = &d->bus[i];
300 ide_register_restart_cb(&d->bus[i]);
301 }
302
303 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
304 qemu_register_reset(cmd646_reset, d);
305}
306
307static void pci_cmd646_ide_exitfn(PCIDevice *dev)
308{
309 PCIIDEState *d = PCI_IDE(dev);
310 unsigned i;
311
312 for (i = 0; i < 2; ++i) {
313 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
314 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
315 }
316}
317
318void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
319 int secondary_ide_enabled)
320{
321 PCIDevice *dev;
322
323 dev = pci_create(bus, -1, "cmd646-ide");
324 qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
325 qdev_init_nofail(&dev->qdev);
326
327 pci_ide_create_devs(dev, hd_table);
328}
329
330static Property cmd646_ide_properties[] = {
331 DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
332 DEFINE_PROP_END_OF_LIST(),
333};
334
335static void cmd646_ide_class_init(ObjectClass *klass, void *data)
336{
337 DeviceClass *dc = DEVICE_CLASS(klass);
338 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
339
340 k->realize = pci_cmd646_ide_realize;
341 k->exit = pci_cmd646_ide_exitfn;
342 k->vendor_id = PCI_VENDOR_ID_CMD;
343 k->device_id = PCI_DEVICE_ID_CMD_646;
344 k->revision = 0x07;
345 k->class_id = PCI_CLASS_STORAGE_IDE;
346 k->config_read = cmd646_pci_config_read;
347 k->config_write = cmd646_pci_config_write;
348 dc->props = cmd646_ide_properties;
349 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
350}
351
352static const TypeInfo cmd646_ide_info = {
353 .name = "cmd646-ide",
354 .parent = TYPE_PCI_IDE,
355 .class_init = cmd646_ide_class_init,
356};
357
358static void cmd646_ide_register_types(void)
359{
360 type_register_static(&cmd646_ide_info);
361}
362
363type_init(cmd646_ide_register_types)
364
