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63#include "qemu/osdep.h"
64#include "hw/hw.h"
65#include "hw/pci/msi.h"
66#include "hw/pci/pci.h"
67#include "qemu/module.h"
68#include "hw/isa/isa.h"
69#include "sysemu/dma.h"
70#include "hw/ide/pci.h"
71#include "ahci_internal.h"
72
73#define ICH9_MSI_CAP_OFFSET 0x80
74#define ICH9_SATA_CAP_OFFSET 0xA8
75
76#define ICH9_IDP_BAR 4
77#define ICH9_MEM_BAR 5
78
79#define ICH9_IDP_INDEX 0x10
80#define ICH9_IDP_INDEX_LOG2 0x04
81
82static const VMStateDescription vmstate_ich9_ahci = {
83 .name = "ich9_ahci",
84 .version_id = 1,
85 .fields = (VMStateField[]) {
86 VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
87 VMSTATE_AHCI(ahci, AHCIPCIState),
88 VMSTATE_END_OF_LIST()
89 },
90};
91
92static void pci_ich9_reset(DeviceState *dev)
93{
94 AHCIPCIState *d = ICH_AHCI(dev);
95
96 ahci_reset(&d->ahci);
97}
98
99static void pci_ich9_ahci_init(Object *obj)
100{
101 struct AHCIPCIState *d = ICH_AHCI(obj);
102
103 ahci_init(&d->ahci, DEVICE(obj));
104}
105
106static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
107{
108 struct AHCIPCIState *d;
109 int sata_cap_offset;
110 uint8_t *sata_cap;
111 d = ICH_AHCI(dev);
112 int ret;
113
114 ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
115
116 pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
117
118 dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
119 dev->config[PCI_LATENCY_TIMER] = 0x00;
120 pci_config_set_interrupt_pin(dev->config, 1);
121
122
123 dev->config[0x90] = 1 << 6;
124
125 d->ahci.irq = pci_allocate_irq(dev);
126
127 pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
128 &d->ahci.idp);
129 pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
130 &d->ahci.mem);
131
132 sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
133 ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE,
134 errp);
135 if (sata_cap_offset < 0) {
136 return;
137 }
138
139 sata_cap = dev->config + sata_cap_offset;
140 pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
141 pci_set_long(sata_cap + SATA_CAP_BAR,
142 (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
143 d->ahci.idp_offset = ICH9_IDP_INDEX;
144
145
146
147
148 ret = msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false, NULL);
149
150
151 assert(!ret || ret == -ENOTSUP);
152}
153
154static void pci_ich9_uninit(PCIDevice *dev)
155{
156 struct AHCIPCIState *d;
157 d = ICH_AHCI(dev);
158
159 msi_uninit(dev);
160 ahci_uninit(&d->ahci);
161 qemu_free_irq(d->ahci.irq);
162}
163
164static void ich_ahci_class_init(ObjectClass *klass, void *data)
165{
166 DeviceClass *dc = DEVICE_CLASS(klass);
167 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
168
169 k->realize = pci_ich9_ahci_realize;
170 k->exit = pci_ich9_uninit;
171 k->vendor_id = PCI_VENDOR_ID_INTEL;
172 k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
173 k->revision = 0x02;
174 k->class_id = PCI_CLASS_STORAGE_SATA;
175 dc->vmsd = &vmstate_ich9_ahci;
176 dc->reset = pci_ich9_reset;
177 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
178}
179
180static const TypeInfo ich_ahci_info = {
181 .name = TYPE_ICH9_AHCI,
182 .parent = TYPE_PCI_DEVICE,
183 .instance_size = sizeof(AHCIPCIState),
184 .instance_init = pci_ich9_ahci_init,
185 .class_init = ich_ahci_class_init,
186 .interfaces = (InterfaceInfo[]) {
187 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
188 { },
189 },
190};
191
192static void ich_ahci_register_types(void)
193{
194 type_register_static(&ich_ahci_info);
195}
196
197type_init(ich_ahci_register_types)
198
