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26#include "qemu/osdep.h"
27#include "hw/hw.h"
28#include "hw/pci/pci.h"
29#include "qemu/module.h"
30#include "sysemu/block-backend.h"
31#include "sysemu/sysemu.h"
32#include "sysemu/blockdev.h"
33#include "sysemu/dma.h"
34
35#include "hw/ide/pci.h"
36#include "trace.h"
37
38static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
39{
40 BMDMAState *bm = opaque;
41 uint32_t val;
42
43 if (size != 1) {
44 return ((uint64_t)1 << (size * 8)) - 1;
45 }
46
47 switch(addr & 3) {
48 case 0:
49 val = bm->cmd;
50 break;
51 case 2:
52 val = bm->status;
53 break;
54 default:
55 val = 0xff;
56 break;
57 }
58
59 trace_bmdma_read(addr, val);
60 return val;
61}
62
63static void bmdma_write(void *opaque, hwaddr addr,
64 uint64_t val, unsigned size)
65{
66 BMDMAState *bm = opaque;
67
68 if (size != 1) {
69 return;
70 }
71
72 trace_bmdma_write(addr, val);
73
74 switch(addr & 3) {
75 case 0:
76 bmdma_cmd_writeb(bm, val);
77 break;
78 case 2:
79 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
80 break;
81 }
82}
83
84static const MemoryRegionOps piix_bmdma_ops = {
85 .read = bmdma_read,
86 .write = bmdma_write,
87};
88
89static void bmdma_setup_bar(PCIIDEState *d)
90{
91 int i;
92
93 memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
94 for(i = 0;i < 2; i++) {
95 BMDMAState *bm = &d->bmdma[i];
96
97 memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
98 "piix-bmdma", 4);
99 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
100 memory_region_init_io(&bm->addr_ioport, OBJECT(d),
101 &bmdma_addr_ioport_ops, bm, "bmdma", 4);
102 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
103 }
104}
105
106static void piix3_reset(void *opaque)
107{
108 PCIIDEState *d = opaque;
109 PCIDevice *pd = PCI_DEVICE(d);
110 uint8_t *pci_conf = pd->config;
111 int i;
112
113 for (i = 0; i < 2; i++) {
114 ide_bus_reset(&d->bus[i]);
115 }
116
117
118 pci_conf[PCI_COMMAND] = 0x00;
119
120 pci_conf[PCI_COMMAND + 1] = 0x00;
121
122 pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
123 pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
124 pci_conf[0x20] = 0x01;
125}
126
127static void pci_piix_init_ports(PCIIDEState *d) {
128 static const struct {
129 int iobase;
130 int iobase2;
131 int isairq;
132 } port_info[] = {
133 {0x1f0, 0x3f6, 14},
134 {0x170, 0x376, 15},
135 };
136 int i;
137
138 for (i = 0; i < 2; i++) {
139 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
140 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
141 port_info[i].iobase2);
142 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
143
144 bmdma_init(&d->bus[i], &d->bmdma[i], d);
145 d->bmdma[i].bus = &d->bus[i];
146 ide_register_restart_cb(&d->bus[i]);
147 }
148}
149
150static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
151{
152 PCIIDEState *d = PCI_IDE(dev);
153 uint8_t *pci_conf = dev->config;
154
155 pci_conf[PCI_CLASS_PROG] = 0x80;
156
157 qemu_register_reset(piix3_reset, d);
158
159 bmdma_setup_bar(d);
160 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
161
162 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
163
164 pci_piix_init_ports(d);
165}
166
167int pci_piix3_xen_ide_unplug(DeviceState *dev, bool aux)
168{
169 PCIIDEState *pci_ide;
170 DriveInfo *di;
171 int i;
172 IDEDevice *idedev;
173
174 pci_ide = PCI_IDE(dev);
175
176 for (i = aux ? 1 : 0; i < 4; i++) {
177 di = drive_get_by_index(IF_IDE, i);
178 if (di != NULL && !di->media_cd) {
179 BlockBackend *blk = blk_by_legacy_dinfo(di);
180 DeviceState *ds = blk_get_attached_dev(blk);
181
182 blk_drain(blk);
183 blk_flush(blk);
184
185 if (ds) {
186 blk_detach_dev(blk, ds);
187 }
188 pci_ide->bus[di->bus].ifs[di->unit].blk = NULL;
189 if (!(i % 2)) {
190 idedev = pci_ide->bus[di->bus].master;
191 } else {
192 idedev = pci_ide->bus[di->bus].slave;
193 }
194 idedev->conf.blk = NULL;
195 monitor_remove_blk(blk);
196 blk_unref(blk);
197 }
198 }
199 qdev_reset_all(DEVICE(dev));
200 return 0;
201}
202
203PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
204{
205 PCIDevice *dev;
206
207 dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
208 pci_ide_create_devs(dev, hd_table);
209 return dev;
210}
211
212static void pci_piix_ide_exitfn(PCIDevice *dev)
213{
214 PCIIDEState *d = PCI_IDE(dev);
215 unsigned i;
216
217 for (i = 0; i < 2; ++i) {
218 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
219 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
220 }
221}
222
223
224
225PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
226{
227 PCIDevice *dev;
228
229 dev = pci_create_simple(bus, devfn, "piix3-ide");
230 pci_ide_create_devs(dev, hd_table);
231 return dev;
232}
233
234
235
236PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
237{
238 PCIDevice *dev;
239
240 dev = pci_create_simple(bus, devfn, "piix4-ide");
241 pci_ide_create_devs(dev, hd_table);
242 return dev;
243}
244
245static void piix3_ide_class_init(ObjectClass *klass, void *data)
246{
247 DeviceClass *dc = DEVICE_CLASS(klass);
248 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
249
250 k->realize = pci_piix_ide_realize;
251 k->exit = pci_piix_ide_exitfn;
252 k->vendor_id = PCI_VENDOR_ID_INTEL;
253 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
254 k->class_id = PCI_CLASS_STORAGE_IDE;
255 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
256 dc->hotpluggable = false;
257}
258
259static const TypeInfo piix3_ide_info = {
260 .name = "piix3-ide",
261 .parent = TYPE_PCI_IDE,
262 .class_init = piix3_ide_class_init,
263};
264
265static const TypeInfo piix3_ide_xen_info = {
266 .name = "piix3-ide-xen",
267 .parent = TYPE_PCI_IDE,
268 .class_init = piix3_ide_class_init,
269};
270
271static void piix4_ide_class_init(ObjectClass *klass, void *data)
272{
273 DeviceClass *dc = DEVICE_CLASS(klass);
274 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
275
276 k->realize = pci_piix_ide_realize;
277 k->exit = pci_piix_ide_exitfn;
278 k->vendor_id = PCI_VENDOR_ID_INTEL;
279 k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
280 k->class_id = PCI_CLASS_STORAGE_IDE;
281 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
282 dc->hotpluggable = false;
283}
284
285static const TypeInfo piix4_ide_info = {
286 .name = "piix4-ide",
287 .parent = TYPE_PCI_IDE,
288 .class_init = piix4_ide_class_init,
289};
290
291static void piix_ide_register_types(void)
292{
293 type_register_static(&piix3_ide_info);
294 type_register_static(&piix3_ide_xen_info);
295 type_register_static(&piix4_ide_info);
296}
297
298type_init(piix_ide_register_types)
299
