LXR qemu/hw/input/pl050.c

   1/*
   2 * Arm PrimeCell PL050 Keyboard / Mouse Interface
   3 *
   4 * Copyright (c) 2006-2007 CodeSourcery.
   5 * Written by Paul Brook
   6 *
   7 * This code is licensed under the GPL.
   8 */
   9
  10#include "qemu/osdep.h"
  11#include "hw/sysbus.h"
  12#include "hw/input/ps2.h"
  13#include "qemu/log.h"
  14#include "qemu/module.h"
  15
  16#define TYPE_PL050 "pl050"
  17#define PL050(obj) OBJECT_CHECK(PL050State, (obj), TYPE_PL050)
  18
  19typedef struct PL050State {
  20    SysBusDevice parent_obj;
  21
  22    MemoryRegion iomem;
  23    void *dev;
  24    uint32_t cr;
  25    uint32_t clk;
  26    uint32_t last;
  27    int pending;
  28    qemu_irq irq;
  29    bool is_mouse;
  30} PL050State;
  31
  32static const VMStateDescription vmstate_pl050 = {
  33    .name = "pl050",
  34    .version_id = 2,
  35    .minimum_version_id = 2,
  36    .fields = (VMStateField[]) {
  37        VMSTATE_UINT32(cr, PL050State),
  38        VMSTATE_UINT32(clk, PL050State),
  39        VMSTATE_UINT32(last, PL050State),
  40        VMSTATE_INT32(pending, PL050State),
  41        VMSTATE_END_OF_LIST()
  42    }
  43};
  44
  45#define PL050_TXEMPTY         (1 << 6)
  46#define PL050_TXBUSY          (1 << 5)
  47#define PL050_RXFULL          (1 << 4)
  48#define PL050_RXBUSY          (1 << 3)
  49#define PL050_RXPARITY        (1 << 2)
  50#define PL050_KMIC            (1 << 1)
  51#define PL050_KMID            (1 << 0)
  52
  53static const unsigned char pl050_id[] =
  54{ 0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  55
  56static void pl050_update(void *opaque, int level)
  57{
  58    PL050State *s = (PL050State *)opaque;
  59    int raise;
  60
  61    s->pending = level;
  62    raise = (s->pending && (s->cr & 0x10) != 0)
  63            || (s->cr & 0x08) != 0;
  64    qemu_set_irq(s->irq, raise);
  65}
  66
  67static uint64_t pl050_read(void *opaque, hwaddr offset,
  68                           unsigned size)
  69{
  70    PL050State *s = (PL050State *)opaque;
  71    if (offset >= 0xfe0 && offset < 0x1000)
  72        return pl050_id[(offset - 0xfe0) >> 2];
  73
  74    switch (offset >> 2) {
  75    case 0: /* KMICR */
  76        return s->cr;
  77    case 1: /* KMISTAT */
  78        {
  79            uint8_t val;
  80            uint32_t stat;
  81
  82            val = s->last;
  83            val = val ^ (val >> 4);
  84            val = val ^ (val >> 2);
  85            val = (val ^ (val >> 1)) & 1;
  86
  87            stat = PL050_TXEMPTY;
  88            if (val)
  89                stat |= PL050_RXPARITY;
  90            if (s->pending)
  91                stat |= PL050_RXFULL;
  92
  93            return stat;
  94        }
  95    case 2: /* KMIDATA */
  96        if (s->pending)
  97            s->last = ps2_read_data(s->dev);
  98        return s->last;
  99    case 3: /* KMICLKDIV */
 100        return s->clk;
 101    case 4: /* KMIIR */
 102        return s->pending | 2;
 103    default:
 104        qemu_log_mask(LOG_GUEST_ERROR,
 105                      "pl050_read: Bad offset %x\n", (int)offset);
 106        return 0;
 107    }
 108}
 109
 110static void pl050_write(void *opaque, hwaddr offset,
 111                        uint64_t value, unsigned size)
 112{
 113    PL050State *s = (PL050State *)opaque;
 114    switch (offset >> 2) {
 115    case 0: /* KMICR */
 116        s->cr = value;
 117        pl050_update(s, s->pending);
 118        /* ??? Need to implement the enable/disable bit.  */
 119        break;
 120    case 2: /* KMIDATA */
 121        /* ??? This should toggle the TX interrupt line.  */
 122        /* ??? This means kbd/mouse can block each other.  */
 123        if (s->is_mouse) {
 124            ps2_write_mouse(s->dev, value);
 125        } else {
 126            ps2_write_keyboard(s->dev, value);
 127        }
 128        break;
 129    case 3: /* KMICLKDIV */
 130        s->clk = value;
 131        return;
 132    default:
 133        qemu_log_mask(LOG_GUEST_ERROR,
 134                      "pl050_write: Bad offset %x\n", (int)offset);
 135    }
 136}
 137static const MemoryRegionOps pl050_ops = {
 138    .read = pl050_read,
 139    .write = pl050_write,
 140    .endianness = DEVICE_NATIVE_ENDIAN,
 141};
 142
 143static void pl050_realize(DeviceState *dev, Error **errp)
 144{
 145    PL050State *s = PL050(dev);
 146    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 147
 148    memory_region_init_io(&s->iomem, OBJECT(s), &pl050_ops, s, "pl050", 0x1000);
 149    sysbus_init_mmio(sbd, &s->iomem);
 150    sysbus_init_irq(sbd, &s->irq);
 151    if (s->is_mouse) {
 152        s->dev = ps2_mouse_init(pl050_update, s);
 153    } else {
 154        s->dev = ps2_kbd_init(pl050_update, s);
 155    }
 156}
 157
 158static void pl050_keyboard_init(Object *obj)
 159{
 160    PL050State *s = PL050(obj);
 161
 162    s->is_mouse = false;
 163}
 164
 165static void pl050_mouse_init(Object *obj)
 166{
 167    PL050State *s = PL050(obj);
 168
 169    s->is_mouse = true;
 170}
 171
 172static const TypeInfo pl050_kbd_info = {
 173    .name          = "pl050_keyboard",
 174    .parent        = TYPE_PL050,
 175    .instance_init = pl050_keyboard_init,
 176};
 177
 178static const TypeInfo pl050_mouse_info = {
 179    .name          = "pl050_mouse",
 180    .parent        = TYPE_PL050,
 181    .instance_init = pl050_mouse_init,
 182};
 183
 184static void pl050_class_init(ObjectClass *oc, void *data)
 185{
 186    DeviceClass *dc = DEVICE_CLASS(oc);
 187
 188    dc->realize = pl050_realize;
 189    dc->vmsd = &vmstate_pl050;
 190}
 191
 192static const TypeInfo pl050_type_info = {
 193    .name          = TYPE_PL050,
 194    .parent        = TYPE_SYS_BUS_DEVICE,
 195    .instance_size = sizeof(PL050State),
 196    .abstract      = true,
 197    .class_init    = pl050_class_init,
 198};
 199
 200static void pl050_register_types(void)
 201{
 202    type_register_static(&pl050_type_info);
 203    type_register_static(&pl050_kbd_info);
 204    type_register_static(&pl050_mouse_info);
 205}
 206
 207type_init(pl050_register_types)
 208