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18#include "qemu/osdep.h"
19#include "qapi/error.h"
20#include "qemu/module.h"
21#include "hw/sysbus.h"
22#include "hw/intc/arm_gicv3.h"
23#include "gicv3_internal.h"
24
25static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
26{
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32
33
34 if (prio < cs->hppi.prio) {
35 return true;
36 }
37
38
39
40
41 if (prio == cs->hppi.prio && irq <= cs->hppi.irq) {
42 return true;
43 }
44 return false;
45}
46
47static uint32_t gicd_int_pending(GICv3State *s, int irq)
48{
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60
61 uint32_t pend, grpmask;
62 uint32_t pending = *gic_bmp_ptr32(s->pending, irq);
63 uint32_t edge_trigger = *gic_bmp_ptr32(s->edge_trigger, irq);
64 uint32_t level = *gic_bmp_ptr32(s->level, irq);
65 uint32_t group = *gic_bmp_ptr32(s->group, irq);
66 uint32_t grpmod = *gic_bmp_ptr32(s->grpmod, irq);
67 uint32_t enable = *gic_bmp_ptr32(s->enabled, irq);
68 uint32_t active = *gic_bmp_ptr32(s->active, irq);
69
70 pend = pending | (~edge_trigger & level);
71 pend &= enable;
72 pend &= ~active;
73
74 if (s->gicd_ctlr & GICD_CTLR_DS) {
75 grpmod = 0;
76 }
77
78 grpmask = 0;
79 if (s->gicd_ctlr & GICD_CTLR_EN_GRP1NS) {
80 grpmask |= group;
81 }
82 if (s->gicd_ctlr & GICD_CTLR_EN_GRP1S) {
83 grpmask |= (~group & grpmod);
84 }
85 if (s->gicd_ctlr & GICD_CTLR_EN_GRP0) {
86 grpmask |= (~group & ~grpmod);
87 }
88 pend &= grpmask;
89
90 return pend;
91}
92
93static uint32_t gicr_int_pending(GICv3CPUState *cs)
94{
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106 uint32_t pend, grpmask, grpmod;
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108 pend = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level);
109 pend &= cs->gicr_ienabler0;
110 pend &= ~cs->gicr_iactiver0;
111
112 if (cs->gic->gicd_ctlr & GICD_CTLR_DS) {
113 grpmod = 0;
114 } else {
115 grpmod = cs->gicr_igrpmodr0;
116 }
117
118 grpmask = 0;
119 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) {
120 grpmask |= cs->gicr_igroupr0;
121 }
122 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1S) {
123 grpmask |= (~cs->gicr_igroupr0 & grpmod);
124 }
125 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP0) {
126 grpmask |= (~cs->gicr_igroupr0 & ~grpmod);
127 }
128 pend &= grpmask;
129
130 return pend;
131}
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135
136static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
137{
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141 bool seenbetter = false;
142 uint8_t prio;
143 int i;
144 uint32_t pend;
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149 pend = gicr_int_pending(cs);
150
151 if (pend) {
152 for (i = 0; i < GIC_INTERNAL; i++) {
153 if (!(pend & (1 << i))) {
154 continue;
155 }
156 prio = cs->gicr_ipriorityr[i];
157 if (irqbetter(cs, i, prio)) {
158 cs->hppi.irq = i;
159 cs->hppi.prio = prio;
160 seenbetter = true;
161 }
162 }
163 }
164
165 if (seenbetter) {
166 cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
167 }
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180 if (!seenbetter && cs->hppi.prio != 0xff && cs->hppi.irq < GIC_INTERNAL) {
181 gicv3_full_update_noirqset(cs->gic);
182 }
183}
184
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188
189void gicv3_redist_update(GICv3CPUState *cs)
190{
191 gicv3_redist_update_noirqset(cs);
192 gicv3_cpuif_update(cs);
193}
194
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198
199static void gicv3_update_noirqset(GICv3State *s, int start, int len)
200{
201 int i;
202 uint8_t prio;
203 uint32_t pend = 0;
204
205 assert(start >= GIC_INTERNAL);
206 assert(len > 0);
207
208 for (i = 0; i < s->num_cpu; i++) {
209 s->cpu[i].seenbetter = false;
210 }
211
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213 for (i = start; i < start + len; i++) {
214 GICv3CPUState *cs;
215
216 if (i == start || (i & 0x1f) == 0) {
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218 pend = gicd_int_pending(s, i & ~0x1f);
219 }
220
221 if (!(pend & (1 << (i & 0x1f)))) {
222 continue;
223 }
224 cs = s->gicd_irouter_target[i];
225 if (!cs) {
226
227
228
229 continue;
230 }
231 prio = s->gicd_ipriority[i];
232 if (irqbetter(cs, i, prio)) {
233 cs->hppi.irq = i;
234 cs->hppi.prio = prio;
235 cs->seenbetter = true;
236 }
237 }
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250 for (i = 0; i < s->num_cpu; i++) {
251 GICv3CPUState *cs = &s->cpu[i];
252
253 if (cs->seenbetter) {
254 cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
255 }
256
257 if (!cs->seenbetter && cs->hppi.prio != 0xff &&
258 cs->hppi.irq >= start && cs->hppi.irq < start + len) {
259 gicv3_full_update_noirqset(s);
260 break;
261 }
262 }
263}
264
265void gicv3_update(GICv3State *s, int start, int len)
266{
267 int i;
268
269 gicv3_update_noirqset(s, start, len);
270 for (i = 0; i < s->num_cpu; i++) {
271 gicv3_cpuif_update(&s->cpu[i]);
272 }
273}
274
275void gicv3_full_update_noirqset(GICv3State *s)
276{
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280 int i;
281
282 for (i = 0; i < s->num_cpu; i++) {
283 s->cpu[i].hppi.prio = 0xff;
284 }
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290
291 gicv3_update_noirqset(s, GIC_INTERNAL, s->num_irq - GIC_INTERNAL);
292
293 for (i = 0; i < s->num_cpu; i++) {
294 gicv3_redist_update_noirqset(&s->cpu[i]);
295 }
296}
297
298void gicv3_full_update(GICv3State *s)
299{
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301
302
303 int i;
304
305 gicv3_full_update_noirqset(s);
306 for (i = 0; i < s->num_cpu; i++) {
307 gicv3_cpuif_update(&s->cpu[i]);
308 }
309}
310
311
312static void gicv3_set_irq(void *opaque, int irq, int level)
313{
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320 GICv3State *s = opaque;
321
322 if (irq < (s->num_irq - GIC_INTERNAL)) {
323
324 gicv3_dist_set_irq(s, irq + GIC_INTERNAL, level);
325 } else {
326
327 int cpu;
328
329 irq -= (s->num_irq - GIC_INTERNAL);
330 cpu = irq / GIC_INTERNAL;
331 irq %= GIC_INTERNAL;
332 assert(cpu < s->num_cpu);
333
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336 assert(irq >= GIC_NR_SGIS);
337 gicv3_redist_set_irq(&s->cpu[cpu], irq, level);
338 }
339}
340
341static void arm_gicv3_post_load(GICv3State *s)
342{
343
344
345
346 gicv3_full_update_noirqset(s);
347
348 gicv3_cache_all_target_cpustates(s);
349}
350
351static const MemoryRegionOps gic_ops[] = {
352 {
353 .read_with_attrs = gicv3_dist_read,
354 .write_with_attrs = gicv3_dist_write,
355 .endianness = DEVICE_NATIVE_ENDIAN,
356 },
357 {
358 .read_with_attrs = gicv3_redist_read,
359 .write_with_attrs = gicv3_redist_write,
360 .endianness = DEVICE_NATIVE_ENDIAN,
361 }
362};
363
364static void arm_gic_realize(DeviceState *dev, Error **errp)
365{
366
367 GICv3State *s = ARM_GICV3(dev);
368 ARMGICv3Class *agc = ARM_GICV3_GET_CLASS(s);
369 Error *local_err = NULL;
370
371 agc->parent_realize(dev, &local_err);
372 if (local_err) {
373 error_propagate(errp, local_err);
374 return;
375 }
376
377 if (s->nb_redist_regions != 1) {
378 error_setg(errp, "VGICv3 redist region number(%d) not equal to 1",
379 s->nb_redist_regions);
380 return;
381 }
382
383 gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops, &local_err);
384 if (local_err) {
385 error_propagate(errp, local_err);
386 return;
387 }
388
389 gicv3_init_cpuif(s);
390}
391
392static void arm_gicv3_class_init(ObjectClass *klass, void *data)
393{
394 DeviceClass *dc = DEVICE_CLASS(klass);
395 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
396 ARMGICv3Class *agc = ARM_GICV3_CLASS(klass);
397
398 agcc->post_load = arm_gicv3_post_load;
399 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);
400}
401
402static const TypeInfo arm_gicv3_info = {
403 .name = TYPE_ARM_GICV3,
404 .parent = TYPE_ARM_GICV3_COMMON,
405 .instance_size = sizeof(GICv3State),
406 .class_init = arm_gicv3_class_init,
407 .class_size = sizeof(ARMGICv3Class),
408};
409
410static void arm_gicv3_register_types(void)
411{
412 type_register_static(&arm_gicv3_info);
413}
414
415type_init(arm_gicv3_register_types)
416