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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qemu/module.h"
27#include "qom/cpu.h"
28#include "hw/intc/arm_gicv3_common.h"
29#include "gicv3_internal.h"
30#include "hw/arm/linux-boot-if.h"
31#include "sysemu/kvm.h"
32
33
34static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs)
35{
36 if (cs->gicd_no_migration_shift_bug) {
37 return;
38 }
39
40
41
42
43
44
45
46
47 memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8,
48 sizeof(cs->group) - GIC_INTERNAL / 8);
49 memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8,
50 sizeof(cs->grpmod) - GIC_INTERNAL / 8);
51 memmove(cs->enabled, (uint8_t *)cs->enabled + GIC_INTERNAL / 8,
52 sizeof(cs->enabled) - GIC_INTERNAL / 8);
53 memmove(cs->pending, (uint8_t *)cs->pending + GIC_INTERNAL / 8,
54 sizeof(cs->pending) - GIC_INTERNAL / 8);
55 memmove(cs->active, (uint8_t *)cs->active + GIC_INTERNAL / 8,
56 sizeof(cs->active) - GIC_INTERNAL / 8);
57 memmove(cs->edge_trigger, (uint8_t *)cs->edge_trigger + GIC_INTERNAL / 8,
58 sizeof(cs->edge_trigger) - GIC_INTERNAL / 8);
59
60
61
62
63
64
65 cs->gicd_no_migration_shift_bug = true;
66}
67
68static int gicv3_pre_save(void *opaque)
69{
70 GICv3State *s = (GICv3State *)opaque;
71 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
72
73 if (c->pre_save) {
74 c->pre_save(s);
75 }
76
77 return 0;
78}
79
80static int gicv3_post_load(void *opaque, int version_id)
81{
82 GICv3State *s = (GICv3State *)opaque;
83 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
84
85 gicv3_gicd_no_migration_shift_bug_post_load(s);
86
87 if (c->post_load) {
88 c->post_load(s);
89 }
90 return 0;
91}
92
93static bool virt_state_needed(void *opaque)
94{
95 GICv3CPUState *cs = opaque;
96
97 return cs->num_list_regs != 0;
98}
99
100static const VMStateDescription vmstate_gicv3_cpu_virt = {
101 .name = "arm_gicv3_cpu/virt",
102 .version_id = 1,
103 .minimum_version_id = 1,
104 .needed = virt_state_needed,
105 .fields = (VMStateField[]) {
106 VMSTATE_UINT64_2DARRAY(ich_apr, GICv3CPUState, 3, 4),
107 VMSTATE_UINT64(ich_hcr_el2, GICv3CPUState),
108 VMSTATE_UINT64_ARRAY(ich_lr_el2, GICv3CPUState, GICV3_LR_MAX),
109 VMSTATE_UINT64(ich_vmcr_el2, GICv3CPUState),
110 VMSTATE_END_OF_LIST()
111 }
112};
113
114static int vmstate_gicv3_cpu_pre_load(void *opaque)
115{
116 GICv3CPUState *cs = opaque;
117
118
119
120
121
122
123 cs->icc_sre_el1 = 0x7;
124 return 0;
125}
126
127static bool icc_sre_el1_reg_needed(void *opaque)
128{
129 GICv3CPUState *cs = opaque;
130
131 return cs->icc_sre_el1 != 7;
132}
133
134const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
135 .name = "arm_gicv3_cpu/sre_el1",
136 .version_id = 1,
137 .minimum_version_id = 1,
138 .needed = icc_sre_el1_reg_needed,
139 .fields = (VMStateField[]) {
140 VMSTATE_UINT64(icc_sre_el1, GICv3CPUState),
141 VMSTATE_END_OF_LIST()
142 }
143};
144
145static const VMStateDescription vmstate_gicv3_cpu = {
146 .name = "arm_gicv3_cpu",
147 .version_id = 1,
148 .minimum_version_id = 1,
149 .pre_load = vmstate_gicv3_cpu_pre_load,
150 .fields = (VMStateField[]) {
151 VMSTATE_UINT32(level, GICv3CPUState),
152 VMSTATE_UINT32(gicr_ctlr, GICv3CPUState),
153 VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2),
154 VMSTATE_UINT32(gicr_waker, GICv3CPUState),
155 VMSTATE_UINT64(gicr_propbaser, GICv3CPUState),
156 VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState),
157 VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState),
158 VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState),
159 VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState),
160 VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState),
161 VMSTATE_UINT32(edge_trigger, GICv3CPUState),
162 VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState),
163 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
164 VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL),
165 VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2),
166 VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState),
167 VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3),
168 VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4),
169 VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3),
170 VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState),
171 VMSTATE_END_OF_LIST()
172 },
173 .subsections = (const VMStateDescription * []) {
174 &vmstate_gicv3_cpu_virt,
175 &vmstate_gicv3_cpu_sre_el1,
176 NULL
177 }
178};
179
180static int gicv3_pre_load(void *opaque)
181{
182 GICv3State *cs = opaque;
183
184
185
186
187
188
189
190
191
192
193
194
195 if (kvm_enabled()) {
196 cs->gicd_no_migration_shift_bug = false;
197 }
198
199 return 0;
200}
201
202static bool needed_always(void *opaque)
203{
204 return true;
205}
206
207const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = {
208 .name = "arm_gicv3/gicd_no_migration_shift_bug",
209 .version_id = 1,
210 .minimum_version_id = 1,
211 .needed = needed_always,
212 .fields = (VMStateField[]) {
213 VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State),
214 VMSTATE_END_OF_LIST()
215 }
216};
217
218static const VMStateDescription vmstate_gicv3 = {
219 .name = "arm_gicv3",
220 .version_id = 1,
221 .minimum_version_id = 1,
222 .pre_load = gicv3_pre_load,
223 .pre_save = gicv3_pre_save,
224 .post_load = gicv3_post_load,
225 .priority = MIG_PRI_GICV3,
226 .fields = (VMStateField[]) {
227 VMSTATE_UINT32(gicd_ctlr, GICv3State),
228 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
229 VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE),
230 VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE),
231 VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE),
232 VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE),
233 VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE),
234 VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE),
235 VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE),
236 VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ),
237 VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ),
238 VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State,
239 DIV_ROUND_UP(GICV3_MAXIRQ, 16)),
240 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
241 vmstate_gicv3_cpu, GICv3CPUState),
242 VMSTATE_END_OF_LIST()
243 },
244 .subsections = (const VMStateDescription * []) {
245 &vmstate_gicv3_gicd_no_migration_shift_bug,
246 NULL
247 }
248};
249
250void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
251 const MemoryRegionOps *ops, Error **errp)
252{
253 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
254 int rdist_capacity = 0;
255 int i;
256
257 for (i = 0; i < s->nb_redist_regions; i++) {
258 rdist_capacity += s->redist_region_count[i];
259 }
260 if (rdist_capacity < s->num_cpu) {
261 error_setg(errp, "Capacity of the redist regions(%d) "
262 "is less than number of vcpus(%d)",
263 rdist_capacity, s->num_cpu);
264 return;
265 }
266
267
268
269
270
271
272
273
274 i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
275 qdev_init_gpio_in(DEVICE(s), handler, i);
276
277 for (i = 0; i < s->num_cpu; i++) {
278 sysbus_init_irq(sbd, &s->cpu[i].parent_irq);
279 }
280 for (i = 0; i < s->num_cpu; i++) {
281 sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
282 }
283 for (i = 0; i < s->num_cpu; i++) {
284 sysbus_init_irq(sbd, &s->cpu[i].parent_virq);
285 }
286 for (i = 0; i < s->num_cpu; i++) {
287 sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
288 }
289
290 memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
291 "gicv3_dist", 0x10000);
292 sysbus_init_mmio(sbd, &s->iomem_dist);
293
294 s->iomem_redist = g_new0(MemoryRegion, s->nb_redist_regions);
295 for (i = 0; i < s->nb_redist_regions; i++) {
296 char *name = g_strdup_printf("gicv3_redist_region[%d]", i);
297
298 memory_region_init_io(&s->iomem_redist[i], OBJECT(s),
299 ops ? &ops[1] : NULL, s, name,
300 s->redist_region_count[i] * GICV3_REDIST_SIZE);
301 sysbus_init_mmio(sbd, &s->iomem_redist[i]);
302 g_free(name);
303 }
304}
305
306static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
307{
308 GICv3State *s = ARM_GICV3_COMMON(dev);
309 int i;
310
311
312
313
314
315
316 if (s->revision != 3) {
317 error_setg(errp, "unsupported GIC revision %d", s->revision);
318 return;
319 }
320
321 if (s->num_irq > GICV3_MAXIRQ) {
322 error_setg(errp,
323 "requested %u interrupt lines exceeds GIC maximum %d",
324 s->num_irq, GICV3_MAXIRQ);
325 return;
326 }
327 if (s->num_irq < GIC_INTERNAL) {
328 error_setg(errp,
329 "requested %u interrupt lines is below GIC minimum %d",
330 s->num_irq, GIC_INTERNAL);
331 return;
332 }
333
334
335
336
337
338
339 if (s->num_irq % 32) {
340 error_setg(errp,
341 "%d interrupt lines unsupported: not divisible by 32",
342 s->num_irq);
343 return;
344 }
345
346 s->cpu = g_new0(GICv3CPUState, s->num_cpu);
347
348 for (i = 0; i < s->num_cpu; i++) {
349 CPUState *cpu = qemu_get_cpu(i);
350 uint64_t cpu_affid;
351 int last;
352
353 s->cpu[i].cpu = cpu;
354 s->cpu[i].gic = s;
355
356 gicv3_set_gicv3state(cpu, &s->cpu[i]);
357
358
359
360
361
362
363
364
365
366
367
368
369
370 cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL);
371 last = (i == s->num_cpu - 1);
372
373
374
375
376 cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) |
377 (cpu_affid & 0xFFFFFF);
378 s->cpu[i].gicr_typer = (cpu_affid << 32) |
379 (1 << 24) |
380 (i << 8) |
381 (last << 4);
382 }
383}
384
385static void arm_gicv3_finalize(Object *obj)
386{
387 GICv3State *s = ARM_GICV3_COMMON(obj);
388
389 g_free(s->redist_region_count);
390}
391
392static void arm_gicv3_common_reset(DeviceState *dev)
393{
394 GICv3State *s = ARM_GICV3_COMMON(dev);
395 int i;
396
397 for (i = 0; i < s->num_cpu; i++) {
398 GICv3CPUState *cs = &s->cpu[i];
399
400 cs->level = 0;
401 cs->gicr_ctlr = 0;
402 cs->gicr_statusr[GICV3_S] = 0;
403 cs->gicr_statusr[GICV3_NS] = 0;
404 cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
405 cs->gicr_propbaser = 0;
406 cs->gicr_pendbaser = 0;
407
408
409
410
411
412 if (s->irq_reset_nonsecure) {
413 cs->gicr_igroupr0 = 0xffffffff;
414 } else {
415 cs->gicr_igroupr0 = 0;
416 }
417
418 cs->gicr_ienabler0 = 0;
419 cs->gicr_ipendr0 = 0;
420 cs->gicr_iactiver0 = 0;
421 cs->edge_trigger = 0xffff;
422 cs->gicr_igrpmodr0 = 0;
423 cs->gicr_nsacr = 0;
424 memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
425
426 cs->hppi.prio = 0xff;
427
428
429
430
431 }
432
433
434 if (s->security_extn) {
435 s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS;
436 } else {
437 s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE;
438 }
439
440 s->gicd_statusr[GICV3_S] = 0;
441 s->gicd_statusr[GICV3_NS] = 0;
442
443 memset(s->group, 0, sizeof(s->group));
444 memset(s->grpmod, 0, sizeof(s->grpmod));
445 memset(s->enabled, 0, sizeof(s->enabled));
446 memset(s->pending, 0, sizeof(s->pending));
447 memset(s->active, 0, sizeof(s->active));
448 memset(s->level, 0, sizeof(s->level));
449 memset(s->edge_trigger, 0, sizeof(s->edge_trigger));
450 memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority));
451 memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter));
452 memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr));
453
454
455
456
457
458
459 gicv3_cache_all_target_cpustates(s);
460
461 if (s->irq_reset_nonsecure) {
462
463
464
465
466
467 for (i = GIC_INTERNAL; i < s->num_irq; i++) {
468 gicv3_gicd_group_set(s, i);
469 }
470 }
471 s->gicd_no_migration_shift_bug = true;
472}
473
474static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
475 bool secure_boot)
476{
477 GICv3State *s = ARM_GICV3_COMMON(obj);
478
479 if (s->security_extn && !secure_boot) {
480
481
482
483
484
485
486
487 s->irq_reset_nonsecure = true;
488 }
489}
490
491static Property arm_gicv3_common_properties[] = {
492 DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
493 DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
494 DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
495 DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
496 DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
497 redist_region_count, qdev_prop_uint32, uint32_t),
498 DEFINE_PROP_END_OF_LIST(),
499};
500
501static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
502{
503 DeviceClass *dc = DEVICE_CLASS(klass);
504 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
505
506 dc->reset = arm_gicv3_common_reset;
507 dc->realize = arm_gicv3_common_realize;
508 dc->props = arm_gicv3_common_properties;
509 dc->vmsd = &vmstate_gicv3;
510 albifc->arm_linux_init = arm_gic_common_linux_init;
511}
512
513static const TypeInfo arm_gicv3_common_type = {
514 .name = TYPE_ARM_GICV3_COMMON,
515 .parent = TYPE_SYS_BUS_DEVICE,
516 .instance_size = sizeof(GICv3State),
517 .class_size = sizeof(ARMGICv3CommonClass),
518 .class_init = arm_gicv3_common_class_init,
519 .instance_finalize = arm_gicv3_finalize,
520 .abstract = true,
521 .interfaces = (InterfaceInfo []) {
522 { TYPE_ARM_LINUX_BOOT_IF },
523 { },
524 },
525};
526
527static void register_types(void)
528{
529 type_register_static(&arm_gicv3_common_type);
530}
531
532type_init(register_types)
533