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21#include "qemu/osdep.h"
22#include "hw/pci/msi.h"
23#include "hw/intc/arm_gicv3_its_common.h"
24#include "qemu/log.h"
25#include "qemu/module.h"
26
27static int gicv3_its_pre_save(void *opaque)
28{
29 GICv3ITSState *s = (GICv3ITSState *)opaque;
30 GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
31
32 if (c->pre_save) {
33 c->pre_save(s);
34 }
35
36 return 0;
37}
38
39static int gicv3_its_post_load(void *opaque, int version_id)
40{
41 GICv3ITSState *s = (GICv3ITSState *)opaque;
42 GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
43
44 if (c->post_load) {
45 c->post_load(s);
46 }
47 return 0;
48}
49
50static const VMStateDescription vmstate_its = {
51 .name = "arm_gicv3_its",
52 .pre_save = gicv3_its_pre_save,
53 .post_load = gicv3_its_post_load,
54 .priority = MIG_PRI_GICV3_ITS,
55 .fields = (VMStateField[]) {
56 VMSTATE_UINT32(ctlr, GICv3ITSState),
57 VMSTATE_UINT32(iidr, GICv3ITSState),
58 VMSTATE_UINT64(cbaser, GICv3ITSState),
59 VMSTATE_UINT64(cwriter, GICv3ITSState),
60 VMSTATE_UINT64(creadr, GICv3ITSState),
61 VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8),
62 VMSTATE_END_OF_LIST()
63 },
64};
65
66static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
67 uint64_t *data, unsigned size,
68 MemTxAttrs attrs)
69{
70 qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
71 *data = 0;
72 return MEMTX_OK;
73}
74
75static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
76 uint64_t value, unsigned size,
77 MemTxAttrs attrs)
78{
79 if (offset == 0x0040 && ((size == 2) || (size == 4))) {
80 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque);
81 GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
82 int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id);
83
84 if (ret <= 0) {
85 qemu_log_mask(LOG_GUEST_ERROR,
86 "ITS: Error sending MSI: %s\n", strerror(-ret));
87 }
88 } else {
89 qemu_log_mask(LOG_GUEST_ERROR,
90 "ITS write at bad offset 0x%"PRIx64"\n", offset);
91 }
92 return MEMTX_OK;
93}
94
95static const MemoryRegionOps gicv3_its_trans_ops = {
96 .read_with_attrs = gicv3_its_trans_read,
97 .write_with_attrs = gicv3_its_trans_write,
98 .endianness = DEVICE_NATIVE_ENDIAN,
99};
100
101void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
102{
103 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
104
105 memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
106 "control", ITS_CONTROL_SIZE);
107 memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
108 &gicv3_its_trans_ops, s,
109 "translation", ITS_TRANS_SIZE);
110
111
112
113
114 memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE);
115 memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl);
116 memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE,
117 &s->iomem_its_translation);
118 sysbus_init_mmio(sbd, &s->iomem_main);
119
120 msi_nonbroken = true;
121}
122
123static void gicv3_its_common_reset(DeviceState *dev)
124{
125 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
126
127 s->ctlr = 0;
128 s->cbaser = 0;
129 s->cwriter = 0;
130 s->creadr = 0;
131 s->iidr = 0;
132 memset(&s->baser, 0, sizeof(s->baser));
133}
134
135static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
136{
137 DeviceClass *dc = DEVICE_CLASS(klass);
138
139 dc->reset = gicv3_its_common_reset;
140 dc->vmsd = &vmstate_its;
141}
142
143static const TypeInfo gicv3_its_common_info = {
144 .name = TYPE_ARM_GICV3_ITS_COMMON,
145 .parent = TYPE_SYS_BUS_DEVICE,
146 .instance_size = sizeof(GICv3ITSState),
147 .class_size = sizeof(GICv3ITSCommonClass),
148 .class_init = gicv3_its_common_class_init,
149 .abstract = true,
150};
151
152static void gicv3_its_common_register_types(void)
153{
154 type_register_static(&gicv3_its_common_info);
155}
156
157type_init(gicv3_its_common_register_types)
158