1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#include "qemu/osdep.h"
21#include "qemu/units.h"
22#include "qemu/error-report.h"
23#include "cpu.h"
24#include "hw/sysbus.h"
25#include "hw/hw.h"
26#include "hw/block/flash.h"
27#include "hw/boards.h"
28#include "hw/loader.h"
29#include "elf.h"
30#include "lm32_hwsetup.h"
31#include "lm32.h"
32#include "exec/address-spaces.h"
33#include "sysemu/sysemu.h"
34
35typedef struct {
36 LM32CPU *cpu;
37 hwaddr bootstrap_pc;
38 hwaddr flash_base;
39 hwaddr hwsetup_base;
40 hwaddr initrd_base;
41 size_t initrd_size;
42 hwaddr cmdline_base;
43} ResetInfo;
44
45static void cpu_irq_handler(void *opaque, int irq, int level)
46{
47 LM32CPU *cpu = opaque;
48 CPUState *cs = CPU(cpu);
49
50 if (level) {
51 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
52 } else {
53 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
54 }
55}
56
57static void main_cpu_reset(void *opaque)
58{
59 ResetInfo *reset_info = opaque;
60 CPULM32State *env = &reset_info->cpu->env;
61
62 cpu_reset(CPU(reset_info->cpu));
63
64
65 env->pc = (uint32_t)reset_info->bootstrap_pc;
66 env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
67 env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
68 env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
69 env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
70 reset_info->initrd_size);
71 env->eba = reset_info->flash_base;
72 env->deba = reset_info->flash_base;
73}
74
75static void lm32_evr_init(MachineState *machine)
76{
77 const char *kernel_filename = machine->kernel_filename;
78 LM32CPU *cpu;
79 CPULM32State *env;
80 DriveInfo *dinfo;
81 MemoryRegion *address_space_mem = get_system_memory();
82 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
83 qemu_irq irq[32];
84 ResetInfo *reset_info;
85 int i;
86
87
88 hwaddr flash_base = 0x04000000;
89 size_t flash_sector_size = 256 * KiB;
90 size_t flash_size = 32 * MiB;
91 hwaddr ram_base = 0x08000000;
92 size_t ram_size = 64 * MiB;
93 hwaddr timer0_base = 0x80002000;
94 hwaddr uart0_base = 0x80006000;
95 hwaddr timer1_base = 0x8000a000;
96 int uart0_irq = 0;
97 int timer0_irq = 1;
98 int timer1_irq = 3;
99
100 reset_info = g_malloc0(sizeof(ResetInfo));
101
102 cpu = LM32_CPU(cpu_create(machine->cpu_type));
103
104 env = &cpu->env;
105 reset_info->cpu = cpu;
106
107 reset_info->flash_base = flash_base;
108
109 memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
110 ram_size);
111 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
112
113 dinfo = drive_get(IF_PFLASH, 0, 0);
114
115 pflash_cfi02_register(flash_base, "lm32_evr.flash", flash_size,
116 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
117 flash_sector_size,
118 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
119
120
121 env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
122 for (i = 0; i < 32; i++) {
123 irq[i] = qdev_get_gpio_in(env->pic_state, i);
124 }
125
126 lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0));
127 sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
128 sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
129
130
131 env->juart_state = lm32_juart_init(serial_hd(1));
132
133 reset_info->bootstrap_pc = flash_base;
134
135 if (kernel_filename) {
136 uint64_t entry;
137 int kernel_size;
138
139 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
140 &entry, NULL, NULL,
141 1, EM_LATTICEMICO32, 0, 0);
142 reset_info->bootstrap_pc = entry;
143
144 if (kernel_size < 0) {
145 kernel_size = load_image_targphys(kernel_filename, ram_base,
146 ram_size);
147 reset_info->bootstrap_pc = ram_base;
148 }
149
150 if (kernel_size < 0) {
151 error_report("could not load kernel '%s'", kernel_filename);
152 exit(1);
153 }
154 }
155
156 qemu_register_reset(main_cpu_reset, reset_info);
157}
158
159static void lm32_uclinux_init(MachineState *machine)
160{
161 const char *kernel_filename = machine->kernel_filename;
162 const char *kernel_cmdline = machine->kernel_cmdline;
163 const char *initrd_filename = machine->initrd_filename;
164 LM32CPU *cpu;
165 CPULM32State *env;
166 DriveInfo *dinfo;
167 MemoryRegion *address_space_mem = get_system_memory();
168 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
169 qemu_irq irq[32];
170 HWSetup *hw;
171 ResetInfo *reset_info;
172 int i;
173
174
175 hwaddr flash_base = 0x04000000;
176 size_t flash_sector_size = 256 * KiB;
177 size_t flash_size = 32 * MiB;
178 hwaddr ram_base = 0x08000000;
179 size_t ram_size = 64 * MiB;
180 hwaddr uart0_base = 0x80000000;
181 hwaddr timer0_base = 0x80002000;
182 hwaddr timer1_base = 0x80010000;
183 hwaddr timer2_base = 0x80012000;
184 int uart0_irq = 0;
185 int timer0_irq = 1;
186 int timer1_irq = 20;
187 int timer2_irq = 21;
188 hwaddr hwsetup_base = 0x0bffe000;
189 hwaddr cmdline_base = 0x0bfff000;
190 hwaddr initrd_base = 0x08400000;
191 size_t initrd_max = 0x01000000;
192
193 reset_info = g_malloc0(sizeof(ResetInfo));
194
195 cpu = LM32_CPU(cpu_create(machine->cpu_type));
196
197 env = &cpu->env;
198 reset_info->cpu = cpu;
199
200 reset_info->flash_base = flash_base;
201
202 memory_region_allocate_system_memory(phys_ram, NULL,
203 "lm32_uclinux.sdram", ram_size);
204 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
205
206 dinfo = drive_get(IF_PFLASH, 0, 0);
207
208 pflash_cfi02_register(flash_base, "lm32_uclinux.flash", flash_size,
209 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
210 flash_sector_size,
211 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
212
213
214 env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
215 for (i = 0; i < 32; i++) {
216 irq[i] = qdev_get_gpio_in(env->pic_state, i);
217 }
218
219 lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0));
220 sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
221 sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
222 sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
223
224
225 env->juart_state = lm32_juart_init(serial_hd(1));
226
227 reset_info->bootstrap_pc = flash_base;
228
229 if (kernel_filename) {
230 uint64_t entry;
231 int kernel_size;
232
233 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
234 &entry, NULL, NULL,
235 1, EM_LATTICEMICO32, 0, 0);
236 reset_info->bootstrap_pc = entry;
237
238 if (kernel_size < 0) {
239 kernel_size = load_image_targphys(kernel_filename, ram_base,
240 ram_size);
241 reset_info->bootstrap_pc = ram_base;
242 }
243
244 if (kernel_size < 0) {
245 error_report("could not load kernel '%s'", kernel_filename);
246 exit(1);
247 }
248 }
249
250
251 hw = hwsetup_init();
252 hwsetup_add_cpu(hw, "LM32", 75000000);
253 hwsetup_add_flash(hw, "flash", flash_base, flash_size);
254 hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
255 hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
256 hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
257 hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
258 hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
259 hwsetup_add_trailer(hw);
260 hwsetup_create_rom(hw, hwsetup_base);
261 hwsetup_free(hw);
262
263 reset_info->hwsetup_base = hwsetup_base;
264
265 if (kernel_cmdline && strlen(kernel_cmdline)) {
266 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
267 kernel_cmdline);
268 reset_info->cmdline_base = cmdline_base;
269 }
270
271 if (initrd_filename) {
272 size_t initrd_size;
273 initrd_size = load_image_targphys(initrd_filename, initrd_base,
274 initrd_max);
275 reset_info->initrd_base = initrd_base;
276 reset_info->initrd_size = initrd_size;
277 }
278
279 qemu_register_reset(main_cpu_reset, reset_info);
280}
281
282static void lm32_evr_class_init(ObjectClass *oc, void *data)
283{
284 MachineClass *mc = MACHINE_CLASS(oc);
285
286 mc->desc = "LatticeMico32 EVR32 eval system";
287 mc->init = lm32_evr_init;
288 mc->is_default = 1;
289 mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full");
290}
291
292static const TypeInfo lm32_evr_type = {
293 .name = MACHINE_TYPE_NAME("lm32-evr"),
294 .parent = TYPE_MACHINE,
295 .class_init = lm32_evr_class_init,
296};
297
298static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
299{
300 MachineClass *mc = MACHINE_CLASS(oc);
301
302 mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
303 mc->init = lm32_uclinux_init;
304 mc->is_default = 0;
305 mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full");
306}
307
308static const TypeInfo lm32_uclinux_type = {
309 .name = MACHINE_TYPE_NAME("lm32-uclinux"),
310 .parent = TYPE_MACHINE,
311 .class_init = lm32_uclinux_class_init,
312};
313
314static void lm32_machine_init(void)
315{
316 type_register_static(&lm32_evr_type);
317 type_register_static(&lm32_uclinux_type);
318}
319
320type_init(lm32_machine_init)
321
