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8#include "qemu/osdep.h"
9#include "qemu/units.h"
10#include "qemu/error-report.h"
11#include "qapi/error.h"
12#include "qemu-common.h"
13#include "cpu.h"
14#include "hw/hw.h"
15#include "hw/m68k/mcf.h"
16#include "hw/m68k/mcf_fec.h"
17#include "qemu/timer.h"
18#include "hw/ptimer.h"
19#include "sysemu/sysemu.h"
20#include "sysemu/qtest.h"
21#include "net/net.h"
22#include "hw/boards.h"
23#include "hw/loader.h"
24#include "hw/sysbus.h"
25#include "elf.h"
26#include "exec/address-spaces.h"
27
28#define SYS_FREQ 166666666
29
30#define ROM_SIZE 0x200000
31
32#define PCSR_EN 0x0001
33#define PCSR_RLD 0x0002
34#define PCSR_PIF 0x0004
35#define PCSR_PIE 0x0008
36#define PCSR_OVW 0x0010
37#define PCSR_DBG 0x0020
38#define PCSR_DOZE 0x0040
39#define PCSR_PRE_SHIFT 8
40#define PCSR_PRE_MASK 0x0f00
41
42typedef struct {
43 MemoryRegion iomem;
44 qemu_irq irq;
45 ptimer_state *timer;
46 uint16_t pcsr;
47 uint16_t pmr;
48 uint16_t pcntr;
49} m5208_timer_state;
50
51static void m5208_timer_update(m5208_timer_state *s)
52{
53 if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
54 qemu_irq_raise(s->irq);
55 else
56 qemu_irq_lower(s->irq);
57}
58
59static void m5208_timer_write(void *opaque, hwaddr offset,
60 uint64_t value, unsigned size)
61{
62 m5208_timer_state *s = (m5208_timer_state *)opaque;
63 int prescale;
64 int limit;
65 switch (offset) {
66 case 0:
67
68 if (value & PCSR_PIF) {
69 s->pcsr &= ~PCSR_PIF;
70 value &= ~PCSR_PIF;
71 }
72
73 if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
74 s->pcsr = value;
75 m5208_timer_update(s);
76 return;
77 }
78
79 if (s->pcsr & PCSR_EN)
80 ptimer_stop(s->timer);
81
82 s->pcsr = value;
83
84 prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
85 ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
86 if (s->pcsr & PCSR_RLD)
87 limit = s->pmr;
88 else
89 limit = 0xffff;
90 ptimer_set_limit(s->timer, limit, 0);
91
92 if (s->pcsr & PCSR_EN)
93 ptimer_run(s->timer, 0);
94 break;
95 case 2:
96 s->pmr = value;
97 s->pcsr &= ~PCSR_PIF;
98 if ((s->pcsr & PCSR_RLD) == 0) {
99 if (s->pcsr & PCSR_OVW)
100 ptimer_set_count(s->timer, value);
101 } else {
102 ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
103 }
104 break;
105 case 4:
106 break;
107 default:
108 hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
109 break;
110 }
111 m5208_timer_update(s);
112}
113
114static void m5208_timer_trigger(void *opaque)
115{
116 m5208_timer_state *s = (m5208_timer_state *)opaque;
117 s->pcsr |= PCSR_PIF;
118 m5208_timer_update(s);
119}
120
121static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
122 unsigned size)
123{
124 m5208_timer_state *s = (m5208_timer_state *)opaque;
125 switch (addr) {
126 case 0:
127 return s->pcsr;
128 case 2:
129 return s->pmr;
130 case 4:
131 return ptimer_get_count(s->timer);
132 default:
133 hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
134 return 0;
135 }
136}
137
138static const MemoryRegionOps m5208_timer_ops = {
139 .read = m5208_timer_read,
140 .write = m5208_timer_write,
141 .endianness = DEVICE_NATIVE_ENDIAN,
142};
143
144static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
145 unsigned size)
146{
147 switch (addr) {
148 case 0x110:
149 {
150 int n;
151 for (n = 0; n < 32; n++) {
152 if (ram_size < (2u << n))
153 break;
154 }
155 return (n - 1) | 0x40000000;
156 }
157 case 0x114:
158 return 0;
159
160 default:
161 hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
162 return 0;
163 }
164}
165
166static void m5208_sys_write(void *opaque, hwaddr addr,
167 uint64_t value, unsigned size)
168{
169 hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
170}
171
172static const MemoryRegionOps m5208_sys_ops = {
173 .read = m5208_sys_read,
174 .write = m5208_sys_write,
175 .endianness = DEVICE_NATIVE_ENDIAN,
176};
177
178static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
179{
180 MemoryRegion *iomem = g_new(MemoryRegion, 1);
181 m5208_timer_state *s;
182 QEMUBH *bh;
183 int i;
184
185
186 memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
187 memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
188
189 for (i = 0; i < 2; i++) {
190 s = g_new0(m5208_timer_state, 1);
191 bh = qemu_bh_new(m5208_timer_trigger, s);
192 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
193 memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
194 "m5208-timer", 0x00004000);
195 memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
196 &s->iomem);
197 s->irq = pic[4 + i];
198 }
199}
200
201static void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd, hwaddr base,
202 qemu_irq *irqs)
203{
204 DeviceState *dev;
205 SysBusDevice *s;
206 int i;
207
208 qemu_check_nic_model(nd, TYPE_MCF_FEC_NET);
209 dev = qdev_create(NULL, TYPE_MCF_FEC_NET);
210 qdev_set_nic_properties(dev, nd);
211 qdev_init_nofail(dev);
212
213 s = SYS_BUS_DEVICE(dev);
214 for (i = 0; i < FEC_NUM_IRQ; i++) {
215 sysbus_connect_irq(s, i, irqs[i]);
216 }
217
218 memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0));
219}
220
221static void mcf5208evb_init(MachineState *machine)
222{
223 ram_addr_t ram_size = machine->ram_size;
224 const char *kernel_filename = machine->kernel_filename;
225 M68kCPU *cpu;
226 CPUM68KState *env;
227 int kernel_size;
228 uint64_t elf_entry;
229 hwaddr entry;
230 qemu_irq *pic;
231 MemoryRegion *address_space_mem = get_system_memory();
232 MemoryRegion *rom = g_new(MemoryRegion, 1);
233 MemoryRegion *ram = g_new(MemoryRegion, 1);
234 MemoryRegion *sram = g_new(MemoryRegion, 1);
235
236 cpu = M68K_CPU(cpu_create(machine->cpu_type));
237 env = &cpu->env;
238
239
240 env->vbr = 0;
241
242
243
244 memory_region_init_rom(rom, NULL, "mcf5208.rom", ROM_SIZE, &error_fatal);
245 memory_region_add_subregion(address_space_mem, 0x00000000, rom);
246
247
248 memory_region_allocate_system_memory(ram, NULL, "mcf5208.ram", ram_size);
249 memory_region_add_subregion(address_space_mem, 0x40000000, ram);
250
251
252 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal);
253 memory_region_add_subregion(address_space_mem, 0x80000000, sram);
254
255
256 pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);
257
258 mcf_uart_mm_init(0xfc060000, pic[26], serial_hd(0));
259 mcf_uart_mm_init(0xfc064000, pic[27], serial_hd(1));
260 mcf_uart_mm_init(0xfc068000, pic[28], serial_hd(2));
261
262 mcf5208_sys_init(address_space_mem, pic);
263
264 if (nb_nics > 1) {
265 error_report("Too many NICs");
266 exit(1);
267 }
268 if (nd_table[0].used) {
269 mcf_fec_init(address_space_mem, &nd_table[0],
270 0xfc030000, pic + 36);
271 }
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296 if (bios_name) {
297 char *fn;
298 uint8_t *ptr;
299
300 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
301 if (!fn) {
302 error_report("Could not find ROM image '%s'", bios_name);
303 exit(1);
304 }
305 if (load_image_targphys(fn, 0x0, ROM_SIZE) < 8) {
306 error_report("Could not load ROM image '%s'", bios_name);
307 exit(1);
308 }
309 g_free(fn);
310
311 ptr = rom_ptr(0x4, 4);
312 assert(ptr != NULL);
313 env->pc = ldl_p(ptr);
314 }
315
316
317 if (!kernel_filename) {
318 if (qtest_enabled() || bios_name) {
319 return;
320 }
321 error_report("Kernel image must be specified");
322 exit(1);
323 }
324
325 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry,
326 NULL, NULL, 1, EM_68K, 0, 0);
327 entry = elf_entry;
328 if (kernel_size < 0) {
329 kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL,
330 NULL, NULL);
331 }
332 if (kernel_size < 0) {
333 kernel_size = load_image_targphys(kernel_filename, 0x40000000,
334 ram_size);
335 entry = 0x40000000;
336 }
337 if (kernel_size < 0) {
338 error_report("Could not load kernel '%s'", kernel_filename);
339 exit(1);
340 }
341
342 env->pc = entry;
343}
344
345static void mcf5208evb_machine_init(MachineClass *mc)
346{
347 mc->desc = "MCF5208EVB";
348 mc->init = mcf5208evb_init;
349 mc->is_default = 1;
350 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208");
351}
352
353DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init)
354
