LXR qemu/hw/misc/armsse-mhu.c

   1/*
   2 * ARM SSE-200 Message Handling Unit (MHU)
   3 *
   4 * Copyright (c) 2019 Linaro Limited
   5 * Written by Peter Maydell
   6 *
   7 *  This program is free software; you can redistribute it and/or modify
   8 *  it under the terms of the GNU General Public License version 2 or
   9 *  (at your option) any later version.
  10 */
  11
  12/*
  13 * This is a model of the Message Handling Unit (MHU) which is part of the
  14 * Arm SSE-200 and documented in
  15 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
  16 */
  17
  18#include "qemu/osdep.h"
  19#include "qemu/log.h"
  20#include "qemu/module.h"
  21#include "trace.h"
  22#include "qapi/error.h"
  23#include "sysemu/sysemu.h"
  24#include "hw/sysbus.h"
  25#include "hw/registerfields.h"
  26#include "hw/misc/armsse-mhu.h"
  27
  28REG32(CPU0INTR_STAT, 0x0)
  29REG32(CPU0INTR_SET, 0x4)
  30REG32(CPU0INTR_CLR, 0x8)
  31REG32(CPU1INTR_STAT, 0x10)
  32REG32(CPU1INTR_SET, 0x14)
  33REG32(CPU1INTR_CLR, 0x18)
  34REG32(PID4, 0xfd0)
  35REG32(PID5, 0xfd4)
  36REG32(PID6, 0xfd8)
  37REG32(PID7, 0xfdc)
  38REG32(PID0, 0xfe0)
  39REG32(PID1, 0xfe4)
  40REG32(PID2, 0xfe8)
  41REG32(PID3, 0xfec)
  42REG32(CID0, 0xff0)
  43REG32(CID1, 0xff4)
  44REG32(CID2, 0xff8)
  45REG32(CID3, 0xffc)
  46
  47/* Valid bits in the interrupt registers. If any are set the IRQ is raised */
  48#define INTR_MASK 0xf
  49
  50/* PID/CID values */
  51static const int armsse_mhu_id[] = {
  52    0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
  53    0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
  54    0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
  55};
  56
  57static void armsse_mhu_update(ARMSSEMHU *s)
  58{
  59    qemu_set_irq(s->cpu0irq, s->cpu0intr != 0);
  60    qemu_set_irq(s->cpu1irq, s->cpu1intr != 0);
  61}
  62
  63static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size)
  64{
  65    ARMSSEMHU *s = ARMSSE_MHU(opaque);
  66    uint64_t r;
  67
  68    switch (offset) {
  69    case A_CPU0INTR_STAT:
  70        r = s->cpu0intr;
  71        break;
  72
  73    case A_CPU1INTR_STAT:
  74        r = s->cpu1intr;
  75        break;
  76
  77    case A_PID4 ... A_CID3:
  78        r = armsse_mhu_id[(offset - A_PID4) / 4];
  79        break;
  80
  81    case A_CPU0INTR_SET:
  82    case A_CPU0INTR_CLR:
  83    case A_CPU1INTR_SET:
  84    case A_CPU1INTR_CLR:
  85        qemu_log_mask(LOG_GUEST_ERROR,
  86                      "SSE MHU: read of write-only register at offset 0x%x\n",
  87                      (int)offset);
  88        r = 0;
  89        break;
  90
  91    default:
  92        qemu_log_mask(LOG_GUEST_ERROR,
  93                      "SSE MHU read: bad offset 0x%x\n", (int)offset);
  94        r = 0;
  95        break;
  96    }
  97    trace_armsse_mhu_read(offset, r, size);
  98    return r;
  99}
 100
 101static void armsse_mhu_write(void *opaque, hwaddr offset,
 102                             uint64_t value, unsigned size)
 103{
 104    ARMSSEMHU *s = ARMSSE_MHU(opaque);
 105
 106    trace_armsse_mhu_write(offset, value, size);
 107
 108    switch (offset) {
 109    case A_CPU0INTR_SET:
 110        s->cpu0intr |= (value & INTR_MASK);
 111        break;
 112    case A_CPU0INTR_CLR:
 113        s->cpu0intr &= ~(value & INTR_MASK);
 114        break;
 115    case A_CPU1INTR_SET:
 116        s->cpu1intr |= (value & INTR_MASK);
 117        break;
 118    case A_CPU1INTR_CLR:
 119        s->cpu1intr &= ~(value & INTR_MASK);
 120        break;
 121
 122    case A_CPU0INTR_STAT:
 123    case A_CPU1INTR_STAT:
 124    case A_PID4 ... A_CID3:
 125        qemu_log_mask(LOG_GUEST_ERROR,
 126                      "SSE MHU: write to read-only register at offset 0x%x\n",
 127                      (int)offset);
 128        break;
 129
 130    default:
 131        qemu_log_mask(LOG_GUEST_ERROR,
 132                      "SSE MHU write: bad offset 0x%x\n", (int)offset);
 133        break;
 134    }
 135
 136    armsse_mhu_update(s);
 137}
 138
 139static const MemoryRegionOps armsse_mhu_ops = {
 140    .read = armsse_mhu_read,
 141    .write = armsse_mhu_write,
 142    .endianness = DEVICE_LITTLE_ENDIAN,
 143    .valid.min_access_size = 4,
 144    .valid.max_access_size = 4,
 145};
 146
 147static void armsse_mhu_reset(DeviceState *dev)
 148{
 149    ARMSSEMHU *s = ARMSSE_MHU(dev);
 150
 151    s->cpu0intr = 0;
 152    s->cpu1intr = 0;
 153}
 154
 155static const VMStateDescription armsse_mhu_vmstate = {
 156    .name = "armsse-mhu",
 157    .version_id = 1,
 158    .minimum_version_id = 1,
 159    .fields = (VMStateField[]) {
 160        VMSTATE_UINT32(cpu0intr, ARMSSEMHU),
 161        VMSTATE_UINT32(cpu1intr, ARMSSEMHU),
 162        VMSTATE_END_OF_LIST()
 163    },
 164};
 165
 166static void armsse_mhu_init(Object *obj)
 167{
 168    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 169    ARMSSEMHU *s = ARMSSE_MHU(obj);
 170
 171    memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops,
 172                          s, "armsse-mhu", 0x1000);
 173    sysbus_init_mmio(sbd, &s->iomem);
 174    sysbus_init_irq(sbd, &s->cpu0irq);
 175    sysbus_init_irq(sbd, &s->cpu1irq);
 176}
 177
 178static void armsse_mhu_class_init(ObjectClass *klass, void *data)
 179{
 180    DeviceClass *dc = DEVICE_CLASS(klass);
 181
 182    dc->reset = armsse_mhu_reset;
 183    dc->vmsd = &armsse_mhu_vmstate;
 184}
 185
 186static const TypeInfo armsse_mhu_info = {
 187    .name = TYPE_ARMSSE_MHU,
 188    .parent = TYPE_SYS_BUS_DEVICE,
 189    .instance_size = sizeof(ARMSSEMHU),
 190    .instance_init = armsse_mhu_init,
 191    .class_init = armsse_mhu_class_init,
 192};
 193
 194static void armsse_mhu_register_types(void)
 195{
 196    type_register_static(&armsse_mhu_info);
 197}
 198
 199type_init(armsse_mhu_register_types);
 200