LXR qemu/hw/misc/aspeed

   1/*
   2 * ASPEED SDRAM Memory Controller
   3 *
   4 * Copyright (C) 2016 IBM Corp.
   5 *
   6 * This code is licensed under the GPL version 2 or later.  See
   7 * the COPYING file in the top-level directory.
   8 */
   9
  10#include "qemu/osdep.h"
  11#include "qemu/log.h"
  12#include "qemu/module.h"
  13#include "qemu/error-report.h"
  14#include "hw/misc/aspeed_sdmc.h"
  15#include "hw/misc/aspeed_scu.h"
  16#include "hw/qdev-properties.h"
  17#include "qapi/error.h"
  18#include "trace.h"
  19
  20/* Protection Key Register */
  21#define R_PROT            (0x00 / 4)
  22#define   PROT_KEY_UNLOCK     0xFC600309
  23
  24/* Configuration Register */
  25#define R_CONF            (0x04 / 4)
  26
  27/* Control/Status Register #1 (ast2500) */
  28#define R_STATUS1         (0x60 / 4)
  29#define   PHY_BUSY_STATE      BIT(0)
  30
  31#define R_ECC_TEST_CTRL   (0x70 / 4)
  32#define   ECC_TEST_FINISHED   BIT(12)
  33#define   ECC_TEST_FAIL       BIT(13)
  34
  35/*
  36 * Configuration register Ox4 (for Aspeed AST2400 SOC)
  37 *
  38 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
  39 * what we care about right now as it is checked by U-Boot to
  40 * determine the RAM size.
  41 */
  42
  43#define ASPEED_SDMC_RESERVED            0xFFFFF800 /* 31:11 reserved */
  44#define ASPEED_SDMC_AST2300_COMPAT      (1 << 10)
  45#define ASPEED_SDMC_SCRAMBLE_PATTERN    (1 << 9)
  46#define ASPEED_SDMC_DATA_SCRAMBLE       (1 << 8)
  47#define ASPEED_SDMC_ECC_ENABLE          (1 << 7)
  48#define ASPEED_SDMC_VGA_COMPAT          (1 << 6) /* readonly */
  49#define ASPEED_SDMC_DRAM_BANK           (1 << 5)
  50#define ASPEED_SDMC_DRAM_BURST          (1 << 4)
  51#define ASPEED_SDMC_VGA_APERTURE(x)     ((x & 0x3) << 2) /* readonly */
  52#define     ASPEED_SDMC_VGA_8MB             0x0
  53#define     ASPEED_SDMC_VGA_16MB            0x1
  54#define     ASPEED_SDMC_VGA_32MB            0x2
  55#define     ASPEED_SDMC_VGA_64MB            0x3
  56#define ASPEED_SDMC_DRAM_SIZE(x)        (x & 0x3)
  57#define     ASPEED_SDMC_DRAM_64MB           0x0
  58#define     ASPEED_SDMC_DRAM_128MB          0x1
  59#define     ASPEED_SDMC_DRAM_256MB          0x2
  60#define     ASPEED_SDMC_DRAM_512MB          0x3
  61
  62#define ASPEED_SDMC_READONLY_MASK                       \
  63    (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT |    \
  64     ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
  65/*
  66 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
  67 *
  68 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
  69 * should be set to 1 for the AST2500 SOC.
  70 */
  71#define ASPEED_SDMC_HW_VERSION(x)       ((x & 0xf) << 28) /* readonly */
  72#define ASPEED_SDMC_SW_VERSION          ((x & 0xff) << 20)
  73#define ASPEED_SDMC_CACHE_INITIAL_DONE  (1 << 19)  /* readonly */
  74#define ASPEED_SDMC_AST2500_RESERVED    0x7C000 /* 18:14 reserved */
  75#define ASPEED_SDMC_CACHE_DDR4_CONF     (1 << 13)
  76#define ASPEED_SDMC_CACHE_INITIAL       (1 << 12)
  77#define ASPEED_SDMC_CACHE_RANGE_CTRL    (1 << 11)
  78#define ASPEED_SDMC_CACHE_ENABLE        (1 << 10) /* differs from AST2400 */
  79#define ASPEED_SDMC_DRAM_TYPE           (1 << 4)  /* differs from AST2400 */
  80
  81/* DRAM size definitions differs */
  82#define     ASPEED_SDMC_AST2500_128MB       0x0
  83#define     ASPEED_SDMC_AST2500_256MB       0x1
  84#define     ASPEED_SDMC_AST2500_512MB       0x2
  85#define     ASPEED_SDMC_AST2500_1024MB      0x3
  86
  87#define ASPEED_SDMC_AST2500_READONLY_MASK                               \
  88    (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE |     \
  89     ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT |            \
  90     ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
  91
  92static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
  93{
  94    AspeedSDMCState *s = ASPEED_SDMC(opaque);
  95
  96    addr >>= 2;
  97
  98    if (addr >= ARRAY_SIZE(s->regs)) {
  99        qemu_log_mask(LOG_GUEST_ERROR,
 100                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 101                      __func__, addr);
 102        return 0;
 103    }
 104
 105    return s->regs[addr];
 106}
 107
 108static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
 109                             unsigned int size)
 110{
 111    AspeedSDMCState *s = ASPEED_SDMC(opaque);
 112
 113    addr >>= 2;
 114
 115    if (addr >= ARRAY_SIZE(s->regs)) {
 116        qemu_log_mask(LOG_GUEST_ERROR,
 117                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 118                      __func__, addr);
 119        return;
 120    }
 121
 122    if (addr == R_PROT) {
 123        s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
 124        return;
 125    }
 126
 127    if (!s->regs[R_PROT]) {
 128        qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
 129        return;
 130    }
 131
 132    if (addr == R_CONF) {
 133        /* Make sure readonly bits are kept */
 134        switch (s->silicon_rev) {
 135        case AST2400_A0_SILICON_REV:
 136        case AST2400_A1_SILICON_REV:
 137            data &= ~ASPEED_SDMC_READONLY_MASK;
 138            data |= s->fixed_conf;
 139            break;
 140        case AST2500_A0_SILICON_REV:
 141        case AST2500_A1_SILICON_REV:
 142            data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
 143            data |= s->fixed_conf;
 144            break;
 145        default:
 146            g_assert_not_reached();
 147        }
 148    }
 149    if (s->silicon_rev == AST2500_A0_SILICON_REV ||
 150            s->silicon_rev == AST2500_A1_SILICON_REV) {
 151        switch (addr) {
 152        case R_STATUS1:
 153            /* Will never return 'busy' */
 154            data &= ~PHY_BUSY_STATE;
 155            break;
 156        case R_ECC_TEST_CTRL:
 157            /* Always done, always happy */
 158            data |= ECC_TEST_FINISHED;
 159            data &= ~ECC_TEST_FAIL;
 160            break;
 161        default:
 162            break;
 163        }
 164    }
 165
 166    s->regs[addr] = data;
 167}
 168
 169static const MemoryRegionOps aspeed_sdmc_ops = {
 170    .read = aspeed_sdmc_read,
 171    .write = aspeed_sdmc_write,
 172    .endianness = DEVICE_LITTLE_ENDIAN,
 173    .valid.min_access_size = 4,
 174    .valid.max_access_size = 4,
 175};
 176
 177static int ast2400_rambits(AspeedSDMCState *s)
 178{
 179    switch (s->ram_size >> 20) {
 180    case 64:
 181        return ASPEED_SDMC_DRAM_64MB;
 182    case 128:
 183        return ASPEED_SDMC_DRAM_128MB;
 184    case 256:
 185        return ASPEED_SDMC_DRAM_256MB;
 186    case 512:
 187        return ASPEED_SDMC_DRAM_512MB;
 188    default:
 189        break;
 190    }
 191
 192    /* use a common default */
 193    warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 256M",
 194                s->ram_size);
 195    s->ram_size = 256 << 20;
 196    return ASPEED_SDMC_DRAM_256MB;
 197}
 198
 199static int ast2500_rambits(AspeedSDMCState *s)
 200{
 201    switch (s->ram_size >> 20) {
 202    case 128:
 203        return ASPEED_SDMC_AST2500_128MB;
 204    case 256:
 205        return ASPEED_SDMC_AST2500_256MB;
 206    case 512:
 207        return ASPEED_SDMC_AST2500_512MB;
 208    case 1024:
 209        return ASPEED_SDMC_AST2500_1024MB;
 210    default:
 211        break;
 212    }
 213
 214    /* use a common default */
 215    warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M",
 216                s->ram_size);
 217    s->ram_size = 512 << 20;
 218    return ASPEED_SDMC_AST2500_512MB;
 219}
 220
 221static void aspeed_sdmc_reset(DeviceState *dev)
 222{
 223    AspeedSDMCState *s = ASPEED_SDMC(dev);
 224
 225    memset(s->regs, 0, sizeof(s->regs));
 226
 227    /* Set ram size bit and defaults values */
 228    s->regs[R_CONF] = s->fixed_conf;
 229}
 230
 231static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
 232{
 233    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 234    AspeedSDMCState *s = ASPEED_SDMC(dev);
 235
 236    if (!is_supported_silicon_rev(s->silicon_rev)) {
 237        error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
 238                s->silicon_rev);
 239        return;
 240    }
 241
 242    switch (s->silicon_rev) {
 243    case AST2400_A0_SILICON_REV:
 244    case AST2400_A1_SILICON_REV:
 245        s->ram_bits = ast2400_rambits(s);
 246        s->max_ram_size = 512 << 20;
 247        s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
 248            ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
 249        break;
 250    case AST2500_A0_SILICON_REV:
 251    case AST2500_A1_SILICON_REV:
 252        s->ram_bits = ast2500_rambits(s);
 253        s->max_ram_size = 1024 << 20;
 254        s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
 255            ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
 256            ASPEED_SDMC_CACHE_INITIAL_DONE |
 257            ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
 258        break;
 259    default:
 260        g_assert_not_reached();
 261    }
 262
 263    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
 264                          TYPE_ASPEED_SDMC, 0x1000);
 265    sysbus_init_mmio(sbd, &s->iomem);
 266}
 267
 268static const VMStateDescription vmstate_aspeed_sdmc = {
 269    .name = "aspeed.sdmc",
 270    .version_id = 1,
 271    .minimum_version_id = 1,
 272    .fields = (VMStateField[]) {
 273        VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
 274        VMSTATE_END_OF_LIST()
 275    }
 276};
 277
 278static Property aspeed_sdmc_properties[] = {
 279    DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
 280    DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
 281    DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
 282    DEFINE_PROP_END_OF_LIST(),
 283};
 284
 285static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
 286{
 287    DeviceClass *dc = DEVICE_CLASS(klass);
 288    dc->realize = aspeed_sdmc_realize;
 289    dc->reset = aspeed_sdmc_reset;
 290    dc->desc = "ASPEED SDRAM Memory Controller";
 291    dc->vmsd = &vmstate_aspeed_sdmc;
 292    dc->props = aspeed_sdmc_properties;
 293}
 294
 295static const TypeInfo aspeed_sdmc_info = {
 296    .name = TYPE_ASPEED_SDMC,
 297    .parent = TYPE_SYS_BUS_DEVICE,
 298    .instance_size = sizeof(AspeedSDMCState),
 299    .class_init = aspeed_sdmc_class_init,
 300};
 301
 302static void aspeed_sdmc_register_types(void)
 303{
 304    type_register_static(&aspeed_sdmc_info);
 305}
 306
 307type_init(aspeed_sdmc_register_types);
 308