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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "qemu/module.h"
30#include "sysemu/sysemu.h"
31
32#ifndef DEBUG_PMU
33#define DEBUG_PMU 0
34#endif
35
36#ifndef DEBUG_PMU_EXTEND
37#define DEBUG_PMU_EXTEND 0
38#endif
39
40#if DEBUG_PMU
41#define PRINT_DEBUG(fmt, args...) \
42 do { \
43 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
44 } while (0)
45
46#if DEBUG_PMU_EXTEND
47#define PRINT_DEBUG_EXTEND(fmt, args...) \
48 do { \
49 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
50 } while (0)
51#else
52#define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
53#endif
54
55#else
56#define PRINT_DEBUG(fmt, args...) do {} while (0)
57#define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
58#endif
59
60
61
62
63#define OM_STAT 0x0000
64#define RTC_CLKO_SEL 0x000C
65#define GNSS_RTC_OUT_CTRL 0x0010
66
67#define SYSTEM_POWER_DOWN_CTRL 0x0200
68
69#define SYSTEM_POWER_DOWN_OPTION 0x0208
70#define SWRESET 0x0400
71#define RST_STAT 0x0404
72#define WAKEUP_STAT 0x0600
73#define EINT_WAKEUP_MASK 0x0604
74#define WAKEUP_MASK 0x0608
75#define HDMI_PHY_CONTROL 0x0700
76#define USBDEVICE_PHY_CONTROL 0x0704
77#define USBHOST_PHY_CONTROL 0x0708
78#define DAC_PHY_CONTROL 0x070C
79#define MIPI_PHY0_CONTROL 0x0710
80#define MIPI_PHY1_CONTROL 0x0714
81#define ADC_PHY_CONTROL 0x0718
82#define PCIe_PHY_CONTROL 0x071C
83#define SATA_PHY_CONTROL 0x0720
84#define INFORM0 0x0800
85#define INFORM1 0x0804
86#define INFORM2 0x0808
87#define INFORM3 0x080C
88#define INFORM4 0x0810
89#define INFORM5 0x0814
90#define INFORM6 0x0818
91#define INFORM7 0x081C
92#define PMU_DEBUG 0x0A00
93
94#define ARM_CORE0_SYS_PWR_REG 0x1000
95#define ARM_CORE1_SYS_PWR_REG 0x1010
96#define ARM_COMMON_SYS_PWR_REG 0x1080
97#define ARM_CPU_L2_0_SYS_PWR_REG 0x10C0
98#define ARM_CPU_L2_1_SYS_PWR_REG 0x10C4
99#define CMU_ACLKSTOP_SYS_PWR_REG 0x1100
100#define CMU_SCLKSTOP_SYS_PWR_REG 0x1104
101#define CMU_RESET_SYS_PWR_REG 0x110C
102#define APLL_SYSCLK_SYS_PWR_REG 0x1120
103#define MPLL_SYSCLK_SYS_PWR_REG 0x1124
104#define VPLL_SYSCLK_SYS_PWR_REG 0x1128
105#define EPLL_SYSCLK_SYS_PWR_REG 0x112C
106#define CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG 0x1138
107#define CMU_RESET_GPS_ALIVE_SYS_PWR_REG 0x113C
108#define CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140
109#define CMU_CLKSTOP_TV_SYS_PWR_REG 0x1144
110#define CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148
111#define CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C
112#define CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150
113#define CMU_CLKSTOP_LCD1_SYS_PWR_REG 0x1154
114#define CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158
115#define CMU_CLKSTOP_GPS_SYS_PWR_REG 0x115C
116#define CMU_RESET_CAM_SYS_PWR_REG 0x1160
117#define CMU_RESET_TV_SYS_PWR_REG 0x1164
118#define CMU_RESET_MFC_SYS_PWR_REG 0x1168
119#define CMU_RESET_G3D_SYS_PWR_REG 0x116C
120#define CMU_RESET_LCD0_SYS_PWR_REG 0x1170
121#define CMU_RESET_LCD1_SYS_PWR_REG 0x1174
122#define CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178
123#define CMU_RESET_GPS_SYS_PWR_REG 0x117C
124#define TOP_BUS_SYS_PWR_REG 0x1180
125#define TOP_RETENTION_SYS_PWR_REG 0x1184
126#define TOP_PWR_SYS_PWR_REG 0x1188
127#define LOGIC_RESET_SYS_PWR_REG 0x11A0
128#define OneNANDXL_MEM_SYS_PWR_REG 0x11C0
129#define MODEMIF_MEM_SYS_PWR_REG 0x11C4
130#define USBDEVICE_MEM_SYS_PWR_REG 0x11CC
131#define SDMMC_MEM_SYS_PWR_REG 0x11D0
132#define CSSYS_MEM_SYS_PWR_REG 0x11D4
133#define SECSS_MEM_SYS_PWR_REG 0x11D8
134#define PCIe_MEM_SYS_PWR_REG 0x11E0
135#define SATA_MEM_SYS_PWR_REG 0x11E4
136#define PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
137#define PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204
138#define PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
139#define PAD_RETENTION_UART_SYS_PWR_REG 0x1224
140#define PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
141#define PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
142#define PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
143#define PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
144#define PAD_ISOLATION_SYS_PWR_REG 0x1240
145#define PAD_ALV_SEL_SYS_PWR_REG 0x1260
146#define XUSBXTI_SYS_PWR_REG 0x1280
147#define XXTI_SYS_PWR_REG 0x1284
148#define EXT_REGULATOR_SYS_PWR_REG 0x12C0
149#define GPIO_MODE_SYS_PWR_REG 0x1300
150#define GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340
151#define CAM_SYS_PWR_REG 0x1380
152#define TV_SYS_PWR_REG 0x1384
153#define MFC_SYS_PWR_REG 0x1388
154#define G3D_SYS_PWR_REG 0x138C
155#define LCD0_SYS_PWR_REG 0x1390
156#define LCD1_SYS_PWR_REG 0x1394
157#define MAUDIO_SYS_PWR_REG 0x1398
158#define GPS_SYS_PWR_REG 0x139C
159#define GPS_ALIVE_SYS_PWR_REG 0x13A0
160#define ARM_CORE0_CONFIGURATION 0x2000
161#define ARM_CORE0_STATUS 0x2004
162#define ARM_CORE0_OPTION 0x2008
163#define ARM_CORE1_CONFIGURATION 0x2080
164#define ARM_CORE1_STATUS 0x2084
165#define ARM_CORE1_OPTION 0x2088
166#define ARM_COMMON_OPTION 0x2408
167
168#define ARM_CPU_L2_0_CONFIGURATION 0x2600
169#define ARM_CPU_L2_0_STATUS 0x2604
170
171#define ARM_CPU_L2_1_CONFIGURATION 0x2620
172#define ARM_CPU_L2_1_STATUS 0x2624
173
174#define PAD_RETENTION_MAUDIO_OPTION 0x3028
175
176#define PAD_RETENTION_GPIO_OPTION 0x3108
177
178#define PAD_RETENTION_UART_OPTION 0x3128
179
180#define PAD_RETENTION_MMCA_OPTION 0x3148
181
182#define PAD_RETENTION_MMCB_OPTION 0x3168
183
184#define PAD_RETENTION_EBIA_OPTION 0x3188
185
186#define PAD_RETENTION_EBIB_OPTION 0x31A8
187#define PS_HOLD_CONTROL 0x330C
188#define XUSBXTI_CONFIGURATION 0x3400
189#define XUSBXTI_STATUS 0x3404
190
191#define XUSBXTI_DURATION 0x341C
192#define XXTI_CONFIGURATION 0x3420
193#define XXTI_STATUS 0x3424
194
195#define XXTI_DURATION 0x343C
196
197#define EXT_REGULATOR_DURATION 0x361C
198#define CAM_CONFIGURATION 0x3C00
199#define CAM_STATUS 0x3C04
200#define CAM_OPTION 0x3C08
201#define TV_CONFIGURATION 0x3C20
202#define TV_STATUS 0x3C24
203#define TV_OPTION 0x3C28
204#define MFC_CONFIGURATION 0x3C40
205#define MFC_STATUS 0x3C44
206#define MFC_OPTION 0x3C48
207#define G3D_CONFIGURATION 0x3C60
208#define G3D_STATUS 0x3C64
209#define G3D_OPTION 0x3C68
210#define LCD0_CONFIGURATION 0x3C80
211#define LCD0_STATUS 0x3C84
212#define LCD0_OPTION 0x3C88
213#define LCD1_CONFIGURATION 0x3CA0
214#define LCD1_STATUS 0x3CA4
215#define LCD1_OPTION 0x3CA8
216#define GPS_CONFIGURATION 0x3CE0
217#define GPS_STATUS 0x3CE4
218#define GPS_OPTION 0x3CE8
219#define GPS_ALIVE_CONFIGURATION 0x3D00
220#define GPS_ALIVE_STATUS 0x3D04
221#define GPS_ALIVE_OPTION 0x3D08
222
223#define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c
224
225typedef struct Exynos4210PmuReg {
226 const char *name;
227 uint32_t offset;
228 uint32_t reset_value;
229} Exynos4210PmuReg;
230
231static const Exynos4210PmuReg exynos4210_pmu_regs[] = {
232 {"OM_STAT", OM_STAT, 0x00000000},
233 {"RTC_CLKO_SEL", RTC_CLKO_SEL, 0x00000000},
234 {"GNSS_RTC_OUT_CTRL", GNSS_RTC_OUT_CTRL, 0x00000001},
235 {"SYSTEM_POWER_DOWN_CTRL", SYSTEM_POWER_DOWN_CTRL, 0x00010000},
236 {"SYSTEM_POWER_DOWN_OPTION", SYSTEM_POWER_DOWN_OPTION, 0x03030000},
237 {"SWRESET", SWRESET, 0x00000000},
238 {"RST_STAT", RST_STAT, 0x00000000},
239 {"WAKEUP_STAT", WAKEUP_STAT, 0x00000000},
240 {"EINT_WAKEUP_MASK", EINT_WAKEUP_MASK, 0x00000000},
241 {"WAKEUP_MASK", WAKEUP_MASK, 0x00000000},
242 {"HDMI_PHY_CONTROL", HDMI_PHY_CONTROL, 0x00960000},
243 {"USBDEVICE_PHY_CONTROL", USBDEVICE_PHY_CONTROL, 0x00000000},
244 {"USBHOST_PHY_CONTROL", USBHOST_PHY_CONTROL, 0x00000000},
245 {"DAC_PHY_CONTROL", DAC_PHY_CONTROL, 0x00000000},
246 {"MIPI_PHY0_CONTROL", MIPI_PHY0_CONTROL, 0x00000000},
247 {"MIPI_PHY1_CONTROL", MIPI_PHY1_CONTROL, 0x00000000},
248 {"ADC_PHY_CONTROL", ADC_PHY_CONTROL, 0x00000001},
249 {"PCIe_PHY_CONTROL", PCIe_PHY_CONTROL, 0x00000000},
250 {"SATA_PHY_CONTROL", SATA_PHY_CONTROL, 0x00000000},
251 {"INFORM0", INFORM0, 0x00000000},
252 {"INFORM1", INFORM1, 0x00000000},
253 {"INFORM2", INFORM2, 0x00000000},
254 {"INFORM3", INFORM3, 0x00000000},
255 {"INFORM4", INFORM4, 0x00000000},
256 {"INFORM5", INFORM5, 0x00000000},
257 {"INFORM6", INFORM6, 0x00000000},
258 {"INFORM7", INFORM7, 0x00000000},
259 {"PMU_DEBUG", PMU_DEBUG, 0x00000000},
260 {"ARM_CORE0_SYS_PWR_REG", ARM_CORE0_SYS_PWR_REG, 0xFFFFFFFF},
261 {"ARM_CORE1_SYS_PWR_REG", ARM_CORE1_SYS_PWR_REG, 0xFFFFFFFF},
262 {"ARM_COMMON_SYS_PWR_REG", ARM_COMMON_SYS_PWR_REG, 0xFFFFFFFF},
263 {"ARM_CPU_L2_0_SYS_PWR_REG", ARM_CPU_L2_0_SYS_PWR_REG, 0xFFFFFFFF},
264 {"ARM_CPU_L2_1_SYS_PWR_REG", ARM_CPU_L2_1_SYS_PWR_REG, 0xFFFFFFFF},
265 {"CMU_ACLKSTOP_SYS_PWR_REG", CMU_ACLKSTOP_SYS_PWR_REG, 0xFFFFFFFF},
266 {"CMU_SCLKSTOP_SYS_PWR_REG", CMU_SCLKSTOP_SYS_PWR_REG, 0xFFFFFFFF},
267 {"CMU_RESET_SYS_PWR_REG", CMU_RESET_SYS_PWR_REG, 0xFFFFFFFF},
268 {"APLL_SYSCLK_SYS_PWR_REG", APLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
269 {"MPLL_SYSCLK_SYS_PWR_REG", MPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
270 {"VPLL_SYSCLK_SYS_PWR_REG", VPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
271 {"EPLL_SYSCLK_SYS_PWR_REG", EPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
272 {"CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG", CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG,
273 0xFFFFFFFF},
274 {"CMU_RESET_GPS_ALIVE_SYS_PWR_REG", CMU_RESET_GPS_ALIVE_SYS_PWR_REG,
275 0xFFFFFFFF},
276 {"CMU_CLKSTOP_CAM_SYS_PWR_REG", CMU_CLKSTOP_CAM_SYS_PWR_REG, 0xFFFFFFFF},
277 {"CMU_CLKSTOP_TV_SYS_PWR_REG", CMU_CLKSTOP_TV_SYS_PWR_REG, 0xFFFFFFFF},
278 {"CMU_CLKSTOP_MFC_SYS_PWR_REG", CMU_CLKSTOP_MFC_SYS_PWR_REG, 0xFFFFFFFF},
279 {"CMU_CLKSTOP_G3D_SYS_PWR_REG", CMU_CLKSTOP_G3D_SYS_PWR_REG, 0xFFFFFFFF},
280 {"CMU_CLKSTOP_LCD0_SYS_PWR_REG", CMU_CLKSTOP_LCD0_SYS_PWR_REG, 0xFFFFFFFF},
281 {"CMU_CLKSTOP_LCD1_SYS_PWR_REG", CMU_CLKSTOP_LCD1_SYS_PWR_REG, 0xFFFFFFFF},
282 {"CMU_CLKSTOP_MAUDIO_SYS_PWR_REG", CMU_CLKSTOP_MAUDIO_SYS_PWR_REG,
283 0xFFFFFFFF},
284 {"CMU_CLKSTOP_GPS_SYS_PWR_REG", CMU_CLKSTOP_GPS_SYS_PWR_REG, 0xFFFFFFFF},
285 {"CMU_RESET_CAM_SYS_PWR_REG", CMU_RESET_CAM_SYS_PWR_REG, 0xFFFFFFFF},
286 {"CMU_RESET_TV_SYS_PWR_REG", CMU_RESET_TV_SYS_PWR_REG, 0xFFFFFFFF},
287 {"CMU_RESET_MFC_SYS_PWR_REG", CMU_RESET_MFC_SYS_PWR_REG, 0xFFFFFFFF},
288 {"CMU_RESET_G3D_SYS_PWR_REG", CMU_RESET_G3D_SYS_PWR_REG, 0xFFFFFFFF},
289 {"CMU_RESET_LCD0_SYS_PWR_REG", CMU_RESET_LCD0_SYS_PWR_REG, 0xFFFFFFFF},
290 {"CMU_RESET_LCD1_SYS_PWR_REG", CMU_RESET_LCD1_SYS_PWR_REG, 0xFFFFFFFF},
291 {"CMU_RESET_MAUDIO_SYS_PWR_REG", CMU_RESET_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
292 {"CMU_RESET_GPS_SYS_PWR_REG", CMU_RESET_GPS_SYS_PWR_REG, 0xFFFFFFFF},
293 {"TOP_BUS_SYS_PWR_REG", TOP_BUS_SYS_PWR_REG, 0xFFFFFFFF},
294 {"TOP_RETENTION_SYS_PWR_REG", TOP_RETENTION_SYS_PWR_REG, 0xFFFFFFFF},
295 {"TOP_PWR_SYS_PWR_REG", TOP_PWR_SYS_PWR_REG, 0xFFFFFFFF},
296 {"LOGIC_RESET_SYS_PWR_REG", LOGIC_RESET_SYS_PWR_REG, 0xFFFFFFFF},
297 {"OneNANDXL_MEM_SYS_PWR_REG", OneNANDXL_MEM_SYS_PWR_REG, 0xFFFFFFFF},
298 {"MODEMIF_MEM_SYS_PWR_REG", MODEMIF_MEM_SYS_PWR_REG, 0xFFFFFFFF},
299 {"USBDEVICE_MEM_SYS_PWR_REG", USBDEVICE_MEM_SYS_PWR_REG, 0xFFFFFFFF},
300 {"SDMMC_MEM_SYS_PWR_REG", SDMMC_MEM_SYS_PWR_REG, 0xFFFFFFFF},
301 {"CSSYS_MEM_SYS_PWR_REG", CSSYS_MEM_SYS_PWR_REG, 0xFFFFFFFF},
302 {"SECSS_MEM_SYS_PWR_REG", SECSS_MEM_SYS_PWR_REG, 0xFFFFFFFF},
303 {"PCIe_MEM_SYS_PWR_REG", PCIe_MEM_SYS_PWR_REG, 0xFFFFFFFF},
304 {"SATA_MEM_SYS_PWR_REG", SATA_MEM_SYS_PWR_REG, 0xFFFFFFFF},
305 {"PAD_RETENTION_DRAM_SYS_PWR_REG", PAD_RETENTION_DRAM_SYS_PWR_REG,
306 0xFFFFFFFF},
307 {"PAD_RETENTION_MAUDIO_SYS_PWR_REG", PAD_RETENTION_MAUDIO_SYS_PWR_REG,
308 0xFFFFFFFF},
309 {"PAD_RETENTION_GPIO_SYS_PWR_REG", PAD_RETENTION_GPIO_SYS_PWR_REG,
310 0xFFFFFFFF},
311 {"PAD_RETENTION_UART_SYS_PWR_REG", PAD_RETENTION_UART_SYS_PWR_REG,
312 0xFFFFFFFF},
313 {"PAD_RETENTION_MMCA_SYS_PWR_REG", PAD_RETENTION_MMCA_SYS_PWR_REG,
314 0xFFFFFFFF},
315 {"PAD_RETENTION_MMCB_SYS_PWR_REG", PAD_RETENTION_MMCB_SYS_PWR_REG,
316 0xFFFFFFFF},
317 {"PAD_RETENTION_EBIA_SYS_PWR_REG", PAD_RETENTION_EBIA_SYS_PWR_REG,
318 0xFFFFFFFF},
319 {"PAD_RETENTION_EBIB_SYS_PWR_REG", PAD_RETENTION_EBIB_SYS_PWR_REG,
320 0xFFFFFFFF},
321 {"PAD_ISOLATION_SYS_PWR_REG", PAD_ISOLATION_SYS_PWR_REG, 0xFFFFFFFF},
322 {"PAD_ALV_SEL_SYS_PWR_REG", PAD_ALV_SEL_SYS_PWR_REG, 0xFFFFFFFF},
323 {"XUSBXTI_SYS_PWR_REG", XUSBXTI_SYS_PWR_REG, 0xFFFFFFFF},
324 {"XXTI_SYS_PWR_REG", XXTI_SYS_PWR_REG, 0xFFFFFFFF},
325 {"EXT_REGULATOR_SYS_PWR_REG", EXT_REGULATOR_SYS_PWR_REG, 0xFFFFFFFF},
326 {"GPIO_MODE_SYS_PWR_REG", GPIO_MODE_SYS_PWR_REG, 0xFFFFFFFF},
327 {"GPIO_MODE_MAUDIO_SYS_PWR_REG", GPIO_MODE_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
328 {"CAM_SYS_PWR_REG", CAM_SYS_PWR_REG, 0xFFFFFFFF},
329 {"TV_SYS_PWR_REG", TV_SYS_PWR_REG, 0xFFFFFFFF},
330 {"MFC_SYS_PWR_REG", MFC_SYS_PWR_REG, 0xFFFFFFFF},
331 {"G3D_SYS_PWR_REG", G3D_SYS_PWR_REG, 0xFFFFFFFF},
332 {"LCD0_SYS_PWR_REG", LCD0_SYS_PWR_REG, 0xFFFFFFFF},
333 {"LCD1_SYS_PWR_REG", LCD1_SYS_PWR_REG, 0xFFFFFFFF},
334 {"MAUDIO_SYS_PWR_REG", MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
335 {"GPS_SYS_PWR_REG", GPS_SYS_PWR_REG, 0xFFFFFFFF},
336 {"GPS_ALIVE_SYS_PWR_REG", GPS_ALIVE_SYS_PWR_REG, 0xFFFFFFFF},
337 {"ARM_CORE0_CONFIGURATION", ARM_CORE0_CONFIGURATION, 0x00000003},
338 {"ARM_CORE0_STATUS", ARM_CORE0_STATUS, 0x00030003},
339 {"ARM_CORE0_OPTION", ARM_CORE0_OPTION, 0x01010001},
340 {"ARM_CORE1_CONFIGURATION", ARM_CORE1_CONFIGURATION, 0x00000003},
341 {"ARM_CORE1_STATUS", ARM_CORE1_STATUS, 0x00030003},
342 {"ARM_CORE1_OPTION", ARM_CORE1_OPTION, 0x01010001},
343 {"ARM_COMMON_OPTION", ARM_COMMON_OPTION, 0x00000001},
344 {"ARM_CPU_L2_0_CONFIGURATION", ARM_CPU_L2_0_CONFIGURATION, 0x00000003},
345 {"ARM_CPU_L2_0_STATUS", ARM_CPU_L2_0_STATUS, 0x00000003},
346 {"ARM_CPU_L2_1_CONFIGURATION", ARM_CPU_L2_1_CONFIGURATION, 0x00000003},
347 {"ARM_CPU_L2_1_STATUS", ARM_CPU_L2_1_STATUS, 0x00000003},
348 {"PAD_RETENTION_MAUDIO_OPTION", PAD_RETENTION_MAUDIO_OPTION, 0x00000000},
349 {"PAD_RETENTION_GPIO_OPTION", PAD_RETENTION_GPIO_OPTION, 0x00000000},
350 {"PAD_RETENTION_UART_OPTION", PAD_RETENTION_UART_OPTION, 0x00000000},
351 {"PAD_RETENTION_MMCA_OPTION", PAD_RETENTION_MMCA_OPTION, 0x00000000},
352 {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000},
353 {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000},
354 {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000},
355
356
357
358
359 {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)},
360 {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001},
361 {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001},
362 {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000},
363 {"XXTI_CONFIGURATION", XXTI_CONFIGURATION, 0x00000001},
364 {"XXTI_STATUS", XXTI_STATUS, 0x00000001},
365 {"XXTI_DURATION", XXTI_DURATION, 0xFFF00000},
366 {"EXT_REGULATOR_DURATION", EXT_REGULATOR_DURATION, 0xFFF03FFF},
367 {"CAM_CONFIGURATION", CAM_CONFIGURATION, 0x00000007},
368 {"CAM_STATUS", CAM_STATUS, 0x00060007},
369 {"CAM_OPTION", CAM_OPTION, 0x00000001},
370 {"TV_CONFIGURATION", TV_CONFIGURATION, 0x00000007},
371 {"TV_STATUS", TV_STATUS, 0x00060007},
372 {"TV_OPTION", TV_OPTION, 0x00000001},
373 {"MFC_CONFIGURATION", MFC_CONFIGURATION, 0x00000007},
374 {"MFC_STATUS", MFC_STATUS, 0x00060007},
375 {"MFC_OPTION", MFC_OPTION, 0x00000001},
376 {"G3D_CONFIGURATION", G3D_CONFIGURATION, 0x00000007},
377 {"G3D_STATUS", G3D_STATUS, 0x00060007},
378 {"G3D_OPTION", G3D_OPTION, 0x00000001},
379 {"LCD0_CONFIGURATION", LCD0_CONFIGURATION, 0x00000007},
380 {"LCD0_STATUS", LCD0_STATUS, 0x00060007},
381 {"LCD0_OPTION", LCD0_OPTION, 0x00000001},
382 {"LCD1_CONFIGURATION", LCD1_CONFIGURATION, 0x00000007},
383 {"LCD1_STATUS", LCD1_STATUS, 0x00060007},
384 {"LCD1_OPTION", LCD1_OPTION, 0x00000001},
385 {"GPS_CONFIGURATION", GPS_CONFIGURATION, 0x00000007},
386 {"GPS_STATUS", GPS_STATUS, 0x00060007},
387 {"GPS_OPTION", GPS_OPTION, 0x00000001},
388 {"GPS_ALIVE_CONFIGURATION", GPS_ALIVE_CONFIGURATION, 0x00000007},
389 {"GPS_ALIVE_STATUS", GPS_ALIVE_STATUS, 0x00060007},
390 {"GPS_ALIVE_OPTION", GPS_ALIVE_OPTION, 0x00000001},
391};
392
393#define PMU_NUM_OF_REGISTERS ARRAY_SIZE(exynos4210_pmu_regs)
394
395#define TYPE_EXYNOS4210_PMU "exynos4210.pmu"
396#define EXYNOS4210_PMU(obj) \
397 OBJECT_CHECK(Exynos4210PmuState, (obj), TYPE_EXYNOS4210_PMU)
398
399typedef struct Exynos4210PmuState {
400 SysBusDevice parent_obj;
401
402 MemoryRegion iomem;
403 uint32_t reg[PMU_NUM_OF_REGISTERS];
404} Exynos4210PmuState;
405
406static void exynos4210_pmu_poweroff(void)
407{
408 PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n");
409 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
410}
411
412static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
413 unsigned size)
414{
415 Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
416 const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
417 unsigned int i;
418
419 for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
420 if (reg_p->offset == offset) {
421 PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name,
422 (uint32_t)offset, s->reg[i]);
423 return s->reg[i];
424 }
425 reg_p++;
426 }
427 PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset);
428 return 0;
429}
430
431static void exynos4210_pmu_write(void *opaque, hwaddr offset,
432 uint64_t val, unsigned size)
433{
434 Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
435 const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
436 unsigned int i;
437
438 for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
439 if (reg_p->offset == offset) {
440 PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,
441 (uint32_t)offset, (uint32_t)val);
442 s->reg[i] = val;
443 if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) {
444
445
446
447
448 exynos4210_pmu_poweroff();
449 }
450 return;
451 }
452 reg_p++;
453 }
454 PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset);
455}
456
457static const MemoryRegionOps exynos4210_pmu_ops = {
458 .read = exynos4210_pmu_read,
459 .write = exynos4210_pmu_write,
460 .endianness = DEVICE_NATIVE_ENDIAN,
461 .valid = {
462 .min_access_size = 4,
463 .max_access_size = 4,
464 .unaligned = false
465 }
466};
467
468static void exynos4210_pmu_reset(DeviceState *dev)
469{
470 Exynos4210PmuState *s = EXYNOS4210_PMU(dev);
471 unsigned i;
472
473
474 for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
475 s->reg[i] = exynos4210_pmu_regs[i].reset_value;
476 }
477}
478
479static void exynos4210_pmu_init(Object *obj)
480{
481 Exynos4210PmuState *s = EXYNOS4210_PMU(obj);
482 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
483
484
485 memory_region_init_io(&s->iomem, obj, &exynos4210_pmu_ops, s,
486 "exynos4210.pmu", EXYNOS4210_PMU_REGS_MEM_SIZE);
487 sysbus_init_mmio(dev, &s->iomem);
488}
489
490static const VMStateDescription exynos4210_pmu_vmstate = {
491 .name = "exynos4210.pmu",
492 .version_id = 1,
493 .minimum_version_id = 1,
494 .fields = (VMStateField[]) {
495 VMSTATE_UINT32_ARRAY(reg, Exynos4210PmuState, PMU_NUM_OF_REGISTERS),
496 VMSTATE_END_OF_LIST()
497 }
498};
499
500static void exynos4210_pmu_class_init(ObjectClass *klass, void *data)
501{
502 DeviceClass *dc = DEVICE_CLASS(klass);
503
504 dc->reset = exynos4210_pmu_reset;
505 dc->vmsd = &exynos4210_pmu_vmstate;
506}
507
508static const TypeInfo exynos4210_pmu_info = {
509 .name = TYPE_EXYNOS4210_PMU,
510 .parent = TYPE_SYS_BUS_DEVICE,
511 .instance_size = sizeof(Exynos4210PmuState),
512 .instance_init = exynos4210_pmu_init,
513 .class_init = exynos4210_pmu_class_init,
514};
515
516static void exynos4210_pmu_register(void)
517{
518 type_register_static(&exynos4210_pmu_info);
519}
520
521type_init(exynos4210_pmu_register)
522