LXR qemu/hw/misc/puv3

   1/*
   2 * Power Management device simulation in PKUnity SoC
   3 *
   4 * Copyright (C) 2010-2012 Guan Xuetao
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation, or any later version.
   9 * See the COPYING file in the top-level directory.
  10 */
  11
  12#include "qemu/osdep.h"
  13#include "hw/hw.h"
  14#include "hw/sysbus.h"
  15
  16#undef DEBUG_PUV3
  17#include "hw/unicore32/puv3.h"
  18#include "qemu/module.h"
  19
  20#define TYPE_PUV3_PM "puv3_pm"
  21#define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM)
  22
  23typedef struct PUV3PMState {
  24    SysBusDevice parent_obj;
  25
  26    MemoryRegion iomem;
  27
  28    uint32_t reg_PMCR;
  29    uint32_t reg_PCGR;
  30    uint32_t reg_PLL_SYS_CFG;
  31    uint32_t reg_PLL_DDR_CFG;
  32    uint32_t reg_PLL_VGA_CFG;
  33    uint32_t reg_DIVCFG;
  34} PUV3PMState;
  35
  36static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
  37        unsigned size)
  38{
  39    PUV3PMState *s = opaque;
  40    uint32_t ret = 0;
  41
  42    switch (offset) {
  43    case 0x14:
  44        ret = s->reg_PCGR;
  45        break;
  46    case 0x18:
  47        ret = s->reg_PLL_SYS_CFG;
  48        break;
  49    case 0x1c:
  50        ret = s->reg_PLL_DDR_CFG;
  51        break;
  52    case 0x20:
  53        ret = s->reg_PLL_VGA_CFG;
  54        break;
  55    case 0x24:
  56        ret = s->reg_DIVCFG;
  57        break;
  58    case 0x28: /* PLL SYS STATUS */
  59        ret = 0x00002401;
  60        break;
  61    case 0x2c: /* PLL DDR STATUS */
  62        ret = 0x00100c00;
  63        break;
  64    case 0x30: /* PLL VGA STATUS */
  65        ret = 0x00003801;
  66        break;
  67    case 0x34: /* DIV STATUS */
  68        ret = 0x22f52015;
  69        break;
  70    case 0x38: /* SW RESET */
  71        ret = 0x0;
  72        break;
  73    case 0x44: /* PLL DFC DONE */
  74        ret = 0x7;
  75        break;
  76    default:
  77        DPRINTF("Bad offset 0x%x\n", offset);
  78    }
  79    DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  80
  81    return ret;
  82}
  83
  84static void puv3_pm_write(void *opaque, hwaddr offset,
  85        uint64_t value, unsigned size)
  86{
  87    PUV3PMState *s = opaque;
  88
  89    switch (offset) {
  90    case 0x0:
  91        s->reg_PMCR = value;
  92        break;
  93    case 0x14:
  94        s->reg_PCGR = value;
  95        break;
  96    case 0x18:
  97        s->reg_PLL_SYS_CFG = value;
  98        break;
  99    case 0x1c:
 100        s->reg_PLL_DDR_CFG = value;
 101        break;
 102    case 0x20:
 103        s->reg_PLL_VGA_CFG = value;
 104        break;
 105    case 0x24:
 106    case 0x38:
 107        break;
 108    default:
 109        DPRINTF("Bad offset 0x%x\n", offset);
 110    }
 111    DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
 112}
 113
 114static const MemoryRegionOps puv3_pm_ops = {
 115    .read = puv3_pm_read,
 116    .write = puv3_pm_write,
 117    .impl = {
 118        .min_access_size = 4,
 119        .max_access_size = 4,
 120    },
 121    .endianness = DEVICE_NATIVE_ENDIAN,
 122};
 123
 124static void puv3_pm_realize(DeviceState *dev, Error **errp)
 125{
 126    PUV3PMState *s = PUV3_PM(dev);
 127
 128    s->reg_PCGR = 0x0;
 129
 130    memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",
 131            PUV3_REGS_OFFSET);
 132    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 133}
 134
 135static void puv3_pm_class_init(ObjectClass *klass, void *data)
 136{
 137    DeviceClass *dc = DEVICE_CLASS(klass);
 138
 139    dc->realize = puv3_pm_realize;
 140}
 141
 142static const TypeInfo puv3_pm_info = {
 143    .name = TYPE_PUV3_PM,
 144    .parent = TYPE_SYS_BUS_DEVICE,
 145    .instance_size = sizeof(PUV3PMState),
 146    .class_init = puv3_pm_class_init,
 147};
 148
 149static void puv3_pm_register_type(void)
 150{
 151    type_register_static(&puv3_pm_info);
 152}
 153
 154type_init(puv3_pm_register_type)
 155