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28#include "qemu/osdep.h"
29#include "qemu/event_notifier.h"
30#include "qemu/module.h"
31#include "qemu/thread.h"
32#include "qemu/sockets.h"
33#include "qapi/error.h"
34#include "chardev/char.h"
35#include "hw/hw.h"
36#include "hw/pci/pci.h"
37#include "net/can_emu.h"
38
39#include "can_sja1000.h"
40
41#define TYPE_CAN_PCI_DEV "mioe3680_pci"
42
43#define MIOe3680_PCI_DEV(obj) \
44 OBJECT_CHECK(Mioe3680PCIState, (obj), TYPE_CAN_PCI_DEV)
45
46
47#ifndef MIOe3680_PCI_VENDOR_ID1
48#define MIOe3680_PCI_VENDOR_ID1 0x13fe
49#endif
50
51#ifndef MIOe3680_PCI_DEVICE_ID1
52#define MIOe3680_PCI_DEVICE_ID1 0xc302
53#endif
54
55#define MIOe3680_PCI_SJA_COUNT 2
56#define MIOe3680_PCI_SJA_RANGE 0x400
57
58#define MIOe3680_PCI_BYTES_PER_SJA 0x80
59
60typedef struct Mioe3680PCIState {
61
62 PCIDevice dev;
63
64 MemoryRegion sja_io[MIOe3680_PCI_SJA_COUNT];
65
66 CanSJA1000State sja_state[MIOe3680_PCI_SJA_COUNT];
67 qemu_irq irq;
68
69 char *model;
70 CanBusState *canbus[MIOe3680_PCI_SJA_COUNT];
71} Mioe3680PCIState;
72
73static void mioe3680_pci_reset(DeviceState *dev)
74{
75 Mioe3680PCIState *d = MIOe3680_PCI_DEV(dev);
76 int i;
77
78 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) {
79 can_sja_hardware_reset(&d->sja_state[i]);
80 }
81}
82
83static uint64_t mioe3680_pci_sja1_io_read(void *opaque, hwaddr addr,
84 unsigned size)
85{
86 Mioe3680PCIState *d = opaque;
87 CanSJA1000State *s = &d->sja_state[0];
88
89 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) {
90 return 0;
91 }
92
93 return can_sja_mem_read(s, addr >> 2, size);
94}
95
96static void mioe3680_pci_sja1_io_write(void *opaque, hwaddr addr, uint64_t data,
97 unsigned size)
98{
99 Mioe3680PCIState *d = opaque;
100 CanSJA1000State *s = &d->sja_state[0];
101
102 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) {
103 return;
104 }
105
106 can_sja_mem_write(s, addr >> 2, data, size);
107}
108
109static uint64_t mioe3680_pci_sja2_io_read(void *opaque, hwaddr addr,
110 unsigned size)
111{
112 Mioe3680PCIState *d = opaque;
113 CanSJA1000State *s = &d->sja_state[1];
114
115 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) {
116 return 0;
117 }
118
119 return can_sja_mem_read(s, addr >> 2, size);
120}
121
122static void mioe3680_pci_sja2_io_write(void *opaque, hwaddr addr, uint64_t data,
123 unsigned size)
124{
125 Mioe3680PCIState *d = opaque;
126 CanSJA1000State *s = &d->sja_state[1];
127
128 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) {
129 return;
130 }
131
132 can_sja_mem_write(s, addr >> 2, data, size);
133}
134
135static const MemoryRegionOps mioe3680_pci_sja1_io_ops = {
136 .read = mioe3680_pci_sja1_io_read,
137 .write = mioe3680_pci_sja1_io_write,
138 .endianness = DEVICE_LITTLE_ENDIAN,
139 .impl = {
140 .max_access_size = 1,
141 },
142};
143
144static const MemoryRegionOps mioe3680_pci_sja2_io_ops = {
145 .read = mioe3680_pci_sja2_io_read,
146 .write = mioe3680_pci_sja2_io_write,
147 .endianness = DEVICE_LITTLE_ENDIAN,
148 .impl = {
149 .max_access_size = 1,
150 },
151};
152
153static void mioe3680_pci_realize(PCIDevice *pci_dev, Error **errp)
154{
155 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev);
156 uint8_t *pci_conf;
157 int i;
158
159 pci_conf = pci_dev->config;
160 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
161
162 d->irq = pci_allocate_irq(&d->dev);
163
164 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) {
165 can_sja_init(&d->sja_state[i], d->irq);
166 }
167
168 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) {
169 if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) {
170 error_setg(errp, "can_sja_connect_to_bus failed");
171 return;
172 }
173 }
174
175 memory_region_init_io(&d->sja_io[0], OBJECT(d), &mioe3680_pci_sja1_io_ops,
176 d, "mioe3680_pci-sja1", MIOe3680_PCI_SJA_RANGE);
177 memory_region_init_io(&d->sja_io[1], OBJECT(d), &mioe3680_pci_sja2_io_ops,
178 d, "mioe3680_pci-sja2", MIOe3680_PCI_SJA_RANGE);
179
180 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) {
181 pci_register_bar(&d->dev, i, PCI_BASE_ADDRESS_SPACE_IO,
182 &d->sja_io[i]);
183 }
184}
185
186static void mioe3680_pci_exit(PCIDevice *pci_dev)
187{
188 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev);
189 int i;
190
191 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) {
192 can_sja_disconnect(&d->sja_state[i]);
193 }
194
195 qemu_free_irq(d->irq);
196}
197
198static const VMStateDescription vmstate_mioe3680_pci = {
199 .name = "mioe3680_pci",
200 .version_id = 1,
201 .minimum_version_id = 1,
202 .minimum_version_id_old = 1,
203 .fields = (VMStateField[]) {
204 VMSTATE_PCI_DEVICE(dev, Mioe3680PCIState),
205 VMSTATE_STRUCT(sja_state[0], Mioe3680PCIState, 0, vmstate_can_sja,
206 CanSJA1000State),
207 VMSTATE_STRUCT(sja_state[1], Mioe3680PCIState, 0, vmstate_can_sja,
208 CanSJA1000State),
209 VMSTATE_END_OF_LIST()
210 }
211};
212
213static void mioe3680_pci_instance_init(Object *obj)
214{
215 Mioe3680PCIState *d = MIOe3680_PCI_DEV(obj);
216
217 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
218 (Object **)&d->canbus[0],
219 qdev_prop_allow_set_link_before_realize,
220 0, &error_abort);
221 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
222 (Object **)&d->canbus[1],
223 qdev_prop_allow_set_link_before_realize,
224 0, &error_abort);
225}
226
227static void mioe3680_pci_class_init(ObjectClass *klass, void *data)
228{
229 DeviceClass *dc = DEVICE_CLASS(klass);
230 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
231
232 k->realize = mioe3680_pci_realize;
233 k->exit = mioe3680_pci_exit;
234 k->vendor_id = MIOe3680_PCI_VENDOR_ID1;
235 k->device_id = MIOe3680_PCI_DEVICE_ID1;
236 k->revision = 0x00;
237 k->class_id = 0x000c09;
238 k->subsystem_vendor_id = MIOe3680_PCI_VENDOR_ID1;
239 k->subsystem_id = MIOe3680_PCI_DEVICE_ID1;
240 dc->desc = "Mioe3680 PCICANx";
241 dc->vmsd = &vmstate_mioe3680_pci;
242 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
243 dc->reset = mioe3680_pci_reset;
244}
245
246static const TypeInfo mioe3680_pci_info = {
247 .name = TYPE_CAN_PCI_DEV,
248 .parent = TYPE_PCI_DEVICE,
249 .instance_size = sizeof(Mioe3680PCIState),
250 .class_init = mioe3680_pci_class_init,
251 .instance_init = mioe3680_pci_instance_init,
252 .interfaces = (InterfaceInfo[]) {
253 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
254 { },
255 },
256};
257
258static void mioe3680_pci_register_types(void)
259{
260 type_register_static(&mioe3680_pci_info);
261}
262
263type_init(mioe3680_pci_register_types)
264
