1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29#include "qemu/osdep.h"
30#include "sysemu/sysemu.h"
31#include "hw/sysbus.h"
32#include "hw/ptimer.h"
33#include "etsec.h"
34#include "registers.h"
35#include "qemu/log.h"
36#include "qemu/module.h"
37
38
39
40
41#ifdef DEBUG_REGISTER
42static const int debug_etsec = 1;
43#else
44static const int debug_etsec;
45#endif
46
47#define DPRINTF(fmt, ...) do { \
48 if (debug_etsec) { \
49 qemu_log(fmt , ## __VA_ARGS__); \
50 } \
51 } while (0)
52
53
54void etsec_update_irq(eTSEC *etsec)
55{
56 uint32_t ievent = etsec->regs[IEVENT].value;
57 uint32_t imask = etsec->regs[IMASK].value;
58 uint32_t active = ievent & imask;
59
60 int tx = !!(active & IEVENT_TX_MASK);
61 int rx = !!(active & IEVENT_RX_MASK);
62 int err = !!(active & IEVENT_ERR_MASK);
63
64 DPRINTF("%s IRQ ievent=%"PRIx32" imask=%"PRIx32" %c%c%c",
65 __func__, ievent, imask,
66 tx ? 'T' : '_',
67 rx ? 'R' : '_',
68 err ? 'E' : '_');
69
70 qemu_set_irq(etsec->tx_irq, tx);
71 qemu_set_irq(etsec->rx_irq, rx);
72 qemu_set_irq(etsec->err_irq, err);
73}
74
75static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size)
76{
77 eTSEC *etsec = opaque;
78 uint32_t reg_index = addr / 4;
79 eTSEC_Register *reg = NULL;
80 uint32_t ret = 0x0;
81
82 assert(reg_index < ETSEC_REG_NUMBER);
83
84 reg = &etsec->regs[reg_index];
85
86
87 switch (reg->access) {
88 case ACC_WO:
89 ret = 0x00000000;
90 break;
91
92 case ACC_RW:
93 case ACC_W1C:
94 case ACC_RO:
95 default:
96 ret = reg->value;
97 break;
98 }
99
100 DPRINTF("Read 0x%08x @ 0x" TARGET_FMT_plx
101 " : %s (%s)\n",
102 ret, addr, reg->name, reg->desc);
103
104 return ret;
105}
106
107static void write_tstat(eTSEC *etsec,
108 eTSEC_Register *reg,
109 uint32_t reg_index,
110 uint32_t value)
111{
112 int i = 0;
113
114 for (i = 0; i < 8; i++) {
115
116 if (value & (1 << (31 - i))) {
117 etsec_walk_tx_ring(etsec, i);
118 }
119 }
120
121
122 reg->value &= ~value;
123}
124
125static void write_rstat(eTSEC *etsec,
126 eTSEC_Register *reg,
127 uint32_t reg_index,
128 uint32_t value)
129{
130 int i = 0;
131
132 for (i = 0; i < 8; i++) {
133
134 if (value & (1 << (23 - i)) && !(reg->value & (1 << (23 - i)))) {
135 etsec_walk_rx_ring(etsec, i);
136 }
137 }
138
139
140 reg->value &= ~value;
141}
142
143static void write_tbasex(eTSEC *etsec,
144 eTSEC_Register *reg,
145 uint32_t reg_index,
146 uint32_t value)
147{
148 reg->value = value & ~0x7;
149
150
151 etsec->regs[TBPTR0 + (reg_index - TBASE0)].value = value & ~0x7;
152}
153
154static void write_rbasex(eTSEC *etsec,
155 eTSEC_Register *reg,
156 uint32_t reg_index,
157 uint32_t value)
158{
159 reg->value = value & ~0x7;
160
161
162 etsec->regs[RBPTR0 + (reg_index - RBASE0)].value = value & ~0x7;
163}
164
165static void write_dmactrl(eTSEC *etsec,
166 eTSEC_Register *reg,
167 uint32_t reg_index,
168 uint32_t value)
169{
170 reg->value = value;
171
172 if (value & DMACTRL_GRS) {
173
174 if (etsec->rx_buffer_len != 0) {
175
176 } else {
177
178 etsec->regs[IEVENT].value |= IEVENT_GRSC;
179 etsec_update_irq(etsec);
180 }
181 }
182
183 if (value & DMACTRL_GTS) {
184
185 if (etsec->tx_buffer_len != 0) {
186
187 } else {
188
189 etsec->regs[IEVENT].value |= IEVENT_GTSC;
190 etsec_update_irq(etsec);
191 }
192 }
193
194 if (!(value & DMACTRL_WOP)) {
195
196 ptimer_stop(etsec->ptimer);
197 ptimer_set_count(etsec->ptimer, 1);
198 ptimer_run(etsec->ptimer, 1);
199 }
200}
201
202static void etsec_write(void *opaque,
203 hwaddr addr,
204 uint64_t value,
205 unsigned size)
206{
207 eTSEC *etsec = opaque;
208 uint32_t reg_index = addr / 4;
209 eTSEC_Register *reg = NULL;
210 uint32_t before = 0x0;
211
212 assert(reg_index < ETSEC_REG_NUMBER);
213
214 reg = &etsec->regs[reg_index];
215 before = reg->value;
216
217 switch (reg_index) {
218 case IEVENT:
219
220 reg->value &= ~value;
221
222 etsec_update_irq(etsec);
223 break;
224
225 case IMASK:
226 reg->value = value;
227
228 etsec_update_irq(etsec);
229 break;
230
231 case DMACTRL:
232 write_dmactrl(etsec, reg, reg_index, value);
233 break;
234
235 case TSTAT:
236 write_tstat(etsec, reg, reg_index, value);
237 break;
238
239 case RSTAT:
240 write_rstat(etsec, reg, reg_index, value);
241 break;
242
243 case TBASE0 ... TBASE7:
244 write_tbasex(etsec, reg, reg_index, value);
245 break;
246
247 case RBASE0 ... RBASE7:
248 write_rbasex(etsec, reg, reg_index, value);
249 break;
250
251 case MIIMCFG ... MIIMIND:
252 etsec_write_miim(etsec, reg, reg_index, value);
253 break;
254
255 default:
256
257 switch (reg->access) {
258
259 case ACC_RW:
260 case ACC_WO:
261 reg->value = value;
262 break;
263
264 case ACC_W1C:
265 reg->value &= ~value;
266 break;
267
268 case ACC_RO:
269 default:
270
271 break;
272 }
273 }
274
275 DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx
276 " val:0x%08x->0x%08x : %s (%s)\n",
277 (unsigned int)value, addr, before, reg->value,
278 reg->name, reg->desc);
279}
280
281static const MemoryRegionOps etsec_ops = {
282 .read = etsec_read,
283 .write = etsec_write,
284 .endianness = DEVICE_NATIVE_ENDIAN,
285 .impl = {
286 .min_access_size = 4,
287 .max_access_size = 4,
288 },
289};
290
291static void etsec_timer_hit(void *opaque)
292{
293 eTSEC *etsec = opaque;
294
295 ptimer_stop(etsec->ptimer);
296
297 if (!(etsec->regs[DMACTRL].value & DMACTRL_WOP)) {
298
299 if (!(etsec->regs[DMACTRL].value & DMACTRL_GTS)) {
300 etsec_walk_tx_ring(etsec, 0);
301 }
302 ptimer_set_count(etsec->ptimer, 1);
303 ptimer_run(etsec->ptimer, 1);
304 }
305}
306
307static void etsec_reset(DeviceState *d)
308{
309 eTSEC *etsec = ETSEC_COMMON(d);
310 int i = 0;
311 int reg_index = 0;
312
313
314 for (i = 0; i < ETSEC_REG_NUMBER; i++) {
315 etsec->regs[i].name = "Reserved";
316 etsec->regs[i].desc = "";
317 etsec->regs[i].access = ACC_UNKNOWN;
318 etsec->regs[i].value = 0x00000000;
319 }
320
321
322 for (i = 0; eTSEC_registers_def[i].name != NULL; i++) {
323
324 reg_index = eTSEC_registers_def[i].offset / 4;
325
326 etsec->regs[reg_index].name = eTSEC_registers_def[i].name;
327 etsec->regs[reg_index].desc = eTSEC_registers_def[i].desc;
328 etsec->regs[reg_index].access = eTSEC_registers_def[i].access;
329 etsec->regs[reg_index].value = eTSEC_registers_def[i].reset;
330 }
331
332 etsec->tx_buffer = NULL;
333 etsec->tx_buffer_len = 0;
334 etsec->rx_buffer = NULL;
335 etsec->rx_buffer_len = 0;
336
337 etsec->phy_status =
338 MII_SR_EXTENDED_CAPS | MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS |
339 MII_SR_AUTONEG_COMPLETE | MII_SR_PREAMBLE_SUPPRESS |
340 MII_SR_EXTENDED_STATUS | MII_SR_100T2_HD_CAPS | MII_SR_100T2_FD_CAPS |
341 MII_SR_10T_HD_CAPS | MII_SR_10T_FD_CAPS | MII_SR_100X_HD_CAPS |
342 MII_SR_100X_FD_CAPS | MII_SR_100T4_CAPS;
343
344 etsec_update_irq(etsec);
345}
346
347static ssize_t etsec_receive(NetClientState *nc,
348 const uint8_t *buf,
349 size_t size)
350{
351 ssize_t ret;
352 eTSEC *etsec = qemu_get_nic_opaque(nc);
353
354#if defined(HEX_DUMP)
355 fprintf(stderr, "%s receive size:%zd\n", nc->name, size);
356 qemu_hexdump((void *)buf, stderr, "", size);
357#endif
358
359 etsec->need_flush = false;
360 ret = etsec_rx_ring_write(etsec, buf, size);
361 if (ret == 0) {
362
363
364 etsec->need_flush = true;
365 }
366 return ret;
367}
368
369
370static void etsec_set_link_status(NetClientState *nc)
371{
372 eTSEC *etsec = qemu_get_nic_opaque(nc);
373
374 etsec_miim_link_status(etsec, nc);
375}
376
377static NetClientInfo net_etsec_info = {
378 .type = NET_CLIENT_DRIVER_NIC,
379 .size = sizeof(NICState),
380 .receive = etsec_receive,
381 .link_status_changed = etsec_set_link_status,
382};
383
384static void etsec_realize(DeviceState *dev, Error **errp)
385{
386 eTSEC *etsec = ETSEC_COMMON(dev);
387
388 etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
389 object_get_typename(OBJECT(dev)), dev->id, etsec);
390 qemu_format_nic_info_str(qemu_get_queue(etsec->nic), etsec->conf.macaddr.a);
391
392
393 etsec->bh = qemu_bh_new(etsec_timer_hit, etsec);
394 etsec->ptimer = ptimer_init(etsec->bh, PTIMER_POLICY_DEFAULT);
395 ptimer_set_freq(etsec->ptimer, 100);
396}
397
398static void etsec_instance_init(Object *obj)
399{
400 eTSEC *etsec = ETSEC_COMMON(obj);
401 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
402
403 memory_region_init_io(&etsec->io_area, OBJECT(etsec), &etsec_ops, etsec,
404 "eTSEC", 0x1000);
405 sysbus_init_mmio(sbd, &etsec->io_area);
406
407 sysbus_init_irq(sbd, &etsec->tx_irq);
408 sysbus_init_irq(sbd, &etsec->rx_irq);
409 sysbus_init_irq(sbd, &etsec->err_irq);
410}
411
412static Property etsec_properties[] = {
413 DEFINE_NIC_PROPERTIES(eTSEC, conf),
414 DEFINE_PROP_END_OF_LIST(),
415};
416
417static void etsec_class_init(ObjectClass *klass, void *data)
418{
419 DeviceClass *dc = DEVICE_CLASS(klass);
420
421 dc->realize = etsec_realize;
422 dc->reset = etsec_reset;
423 dc->props = etsec_properties;
424
425 dc->user_creatable = true;
426}
427
428static TypeInfo etsec_info = {
429 .name = "eTSEC",
430 .parent = TYPE_SYS_BUS_DEVICE,
431 .instance_size = sizeof(eTSEC),
432 .class_init = etsec_class_init,
433 .instance_init = etsec_instance_init,
434};
435
436static void etsec_register_types(void)
437{
438 type_register_static(&etsec_info);
439}
440
441type_init(etsec_register_types)
442
443DeviceState *etsec_create(hwaddr base,
444 MemoryRegion * mr,
445 NICInfo * nd,
446 qemu_irq tx_irq,
447 qemu_irq rx_irq,
448 qemu_irq err_irq)
449{
450 DeviceState *dev;
451
452 dev = qdev_create(NULL, "eTSEC");
453 qdev_set_nic_properties(dev, nd);
454 qdev_init_nofail(dev);
455
456 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);
457 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);
458 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, err_irq);
459
460 memory_region_add_subregion(mr, base,
461 SYS_BUS_DEVICE(dev)->mmio[0].memory);
462
463 return dev;
464}
465
