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25#include "qemu/osdep.h"
26#include "net/eth.h"
27#include "qemu/module.h"
28#include "ne2000.h"
29#include "sysemu/sysemu.h"
30#include "trace.h"
31
32
33
34
35#define MAX_ETH_FRAME_SIZE 1514
36
37#define E8390_CMD 0x00
38
39#define EN0_CLDALO 0x01
40#define EN0_STARTPG 0x01
41#define EN0_CLDAHI 0x02
42#define EN0_STOPPG 0x02
43#define EN0_BOUNDARY 0x03
44#define EN0_TSR 0x04
45#define EN0_TPSR 0x04
46#define EN0_NCR 0x05
47#define EN0_TCNTLO 0x05
48#define EN0_FIFO 0x06
49#define EN0_TCNTHI 0x06
50#define EN0_ISR 0x07
51#define EN0_CRDALO 0x08
52#define EN0_RSARLO 0x08
53#define EN0_CRDAHI 0x09
54#define EN0_RSARHI 0x09
55#define EN0_RCNTLO 0x0a
56#define EN0_RTL8029ID0 0x0a
57#define EN0_RCNTHI 0x0b
58#define EN0_RTL8029ID1 0x0b
59#define EN0_RSR 0x0c
60#define EN0_RXCR 0x0c
61#define EN0_TXCR 0x0d
62#define EN0_COUNTER0 0x0d
63#define EN0_DCFG 0x0e
64#define EN0_COUNTER1 0x0e
65#define EN0_IMR 0x0f
66#define EN0_COUNTER2 0x0f
67
68#define EN1_PHYS 0x11
69#define EN1_CURPAG 0x17
70#define EN1_MULT 0x18
71
72#define EN2_STARTPG 0x21
73#define EN2_STOPPG 0x22
74
75#define EN3_CONFIG0 0x33
76#define EN3_CONFIG1 0x34
77#define EN3_CONFIG2 0x35
78#define EN3_CONFIG3 0x36
79
80
81#define E8390_STOP 0x01
82#define E8390_START 0x02
83#define E8390_TRANS 0x04
84#define E8390_RREAD 0x08
85#define E8390_RWRITE 0x10
86#define E8390_NODMA 0x20
87#define E8390_PAGE0 0x00
88#define E8390_PAGE1 0x40
89#define E8390_PAGE2 0x80
90
91
92#define ENISR_RX 0x01
93#define ENISR_TX 0x02
94#define ENISR_RX_ERR 0x04
95#define ENISR_TX_ERR 0x08
96#define ENISR_OVER 0x10
97#define ENISR_COUNTERS 0x20
98#define ENISR_RDC 0x40
99#define ENISR_RESET 0x80
100#define ENISR_ALL 0x3f
101
102
103#define ENRSR_RXOK 0x01
104#define ENRSR_CRC 0x02
105#define ENRSR_FAE 0x04
106#define ENRSR_FO 0x08
107#define ENRSR_MPA 0x10
108#define ENRSR_PHY 0x20
109#define ENRSR_DIS 0x40
110#define ENRSR_DEF 0x80
111
112
113#define ENTSR_PTX 0x01
114#define ENTSR_ND 0x02
115#define ENTSR_COL 0x04
116#define ENTSR_ABT 0x08
117#define ENTSR_CRS 0x10
118#define ENTSR_FU 0x20
119#define ENTSR_CDH 0x40
120#define ENTSR_OWC 0x80
121
122void ne2000_reset(NE2000State *s)
123{
124 int i;
125
126 s->isr = ENISR_RESET;
127 memcpy(s->mem, &s->c.macaddr, 6);
128 s->mem[14] = 0x57;
129 s->mem[15] = 0x57;
130
131
132 for(i = 15;i >= 0; i--) {
133 s->mem[2 * i] = s->mem[i];
134 s->mem[2 * i + 1] = s->mem[i];
135 }
136}
137
138static void ne2000_update_irq(NE2000State *s)
139{
140 int isr;
141 isr = (s->isr & s->imr) & 0x7f;
142#if defined(DEBUG_NE2000)
143 printf("NE2000: Set IRQ to %d (%02x %02x)\n",
144 isr ? 1 : 0, s->isr, s->imr);
145#endif
146 qemu_set_irq(s->irq, (isr != 0));
147}
148
149static int ne2000_buffer_full(NE2000State *s)
150{
151 int avail, index, boundary;
152
153 if (s->stop <= s->start) {
154 return 1;
155 }
156
157 index = s->curpag << 8;
158 boundary = s->boundary << 8;
159 if (index < boundary)
160 avail = boundary - index;
161 else
162 avail = (s->stop - s->start) - (index - boundary);
163 if (avail < (MAX_ETH_FRAME_SIZE + 4))
164 return 1;
165 return 0;
166}
167
168#define MIN_BUF_SIZE 60
169
170ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
171{
172 NE2000State *s = qemu_get_nic_opaque(nc);
173 size_t size = size_;
174 uint8_t *p;
175 unsigned int total_len, next, avail, len, index, mcast_idx;
176 uint8_t buf1[60];
177 static const uint8_t broadcast_macaddr[6] =
178 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
179
180#if defined(DEBUG_NE2000)
181 printf("NE2000: received len=%zu\n", size);
182#endif
183
184 if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
185 return -1;
186
187
188 if (s->rxcr & 0x10) {
189
190 } else {
191 if (!memcmp(buf, broadcast_macaddr, 6)) {
192
193 if (!(s->rxcr & 0x04))
194 return size;
195 } else if (buf[0] & 0x01) {
196
197 if (!(s->rxcr & 0x08))
198 return size;
199 mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
200 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
201 return size;
202 } else if (s->mem[0] == buf[0] &&
203 s->mem[2] == buf[1] &&
204 s->mem[4] == buf[2] &&
205 s->mem[6] == buf[3] &&
206 s->mem[8] == buf[4] &&
207 s->mem[10] == buf[5]) {
208
209 } else {
210 return size;
211 }
212 }
213
214
215
216 if (size < MIN_BUF_SIZE) {
217 memcpy(buf1, buf, size);
218 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
219 buf = buf1;
220 size = MIN_BUF_SIZE;
221 }
222
223 index = s->curpag << 8;
224 if (index >= NE2000_PMEM_END) {
225 index = s->start;
226 }
227
228 total_len = size + 4;
229
230 next = index + ((total_len + 4 + 255) & ~0xff);
231 if (next >= s->stop)
232 next -= (s->stop - s->start);
233
234 p = s->mem + index;
235 s->rsr = ENRSR_RXOK;
236
237 if (buf[0] & 0x01)
238 s->rsr |= ENRSR_PHY;
239 p[0] = s->rsr;
240 p[1] = next >> 8;
241 p[2] = total_len;
242 p[3] = total_len >> 8;
243 index += 4;
244
245
246 while (size > 0) {
247 if (index <= s->stop)
248 avail = s->stop - index;
249 else
250 break;
251 len = size;
252 if (len > avail)
253 len = avail;
254 memcpy(s->mem + index, buf, len);
255 buf += len;
256 index += len;
257 if (index == s->stop)
258 index = s->start;
259 size -= len;
260 }
261 s->curpag = next >> 8;
262
263
264 s->isr |= ENISR_RX;
265 ne2000_update_irq(s);
266
267 return size_;
268}
269
270static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
271{
272 NE2000State *s = opaque;
273 int offset, page, index;
274
275 addr &= 0xf;
276 trace_ne2000_ioport_write(addr, val);
277 if (addr == E8390_CMD) {
278
279 s->cmd = val;
280 if (!(val & E8390_STOP)) {
281 s->isr &= ~ENISR_RESET;
282
283 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
284 s->rcnt == 0) {
285 s->isr |= ENISR_RDC;
286 ne2000_update_irq(s);
287 }
288 if (val & E8390_TRANS) {
289 index = (s->tpsr << 8);
290
291 if (index >= NE2000_PMEM_END)
292 index -= NE2000_PMEM_SIZE;
293
294 if (index + s->tcnt <= NE2000_PMEM_END) {
295 qemu_send_packet(qemu_get_queue(s->nic), s->mem + index,
296 s->tcnt);
297 }
298
299 s->tsr = ENTSR_PTX;
300 s->isr |= ENISR_TX;
301 s->cmd &= ~E8390_TRANS;
302 ne2000_update_irq(s);
303 }
304 }
305 } else {
306 page = s->cmd >> 6;
307 offset = addr | (page << 4);
308 switch(offset) {
309 case EN0_STARTPG:
310 if (val << 8 <= NE2000_PMEM_END) {
311 s->start = val << 8;
312 }
313 break;
314 case EN0_STOPPG:
315 if (val << 8 <= NE2000_PMEM_END) {
316 s->stop = val << 8;
317 }
318 break;
319 case EN0_BOUNDARY:
320 if (val << 8 < NE2000_PMEM_END) {
321 s->boundary = val;
322 }
323 break;
324 case EN0_IMR:
325 s->imr = val;
326 ne2000_update_irq(s);
327 break;
328 case EN0_TPSR:
329 s->tpsr = val;
330 break;
331 case EN0_TCNTLO:
332 s->tcnt = (s->tcnt & 0xff00) | val;
333 break;
334 case EN0_TCNTHI:
335 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
336 break;
337 case EN0_RSARLO:
338 s->rsar = (s->rsar & 0xff00) | val;
339 break;
340 case EN0_RSARHI:
341 s->rsar = (s->rsar & 0x00ff) | (val << 8);
342 break;
343 case EN0_RCNTLO:
344 s->rcnt = (s->rcnt & 0xff00) | val;
345 break;
346 case EN0_RCNTHI:
347 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
348 break;
349 case EN0_RXCR:
350 s->rxcr = val;
351 break;
352 case EN0_DCFG:
353 s->dcfg = val;
354 break;
355 case EN0_ISR:
356 s->isr &= ~(val & 0x7f);
357 ne2000_update_irq(s);
358 break;
359 case EN1_PHYS ... EN1_PHYS + 5:
360 s->phys[offset - EN1_PHYS] = val;
361 break;
362 case EN1_CURPAG:
363 if (val << 8 < NE2000_PMEM_END) {
364 s->curpag = val;
365 }
366 break;
367 case EN1_MULT ... EN1_MULT + 7:
368 s->mult[offset - EN1_MULT] = val;
369 break;
370 }
371 }
372}
373
374static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
375{
376 NE2000State *s = opaque;
377 int offset, page, ret;
378
379 addr &= 0xf;
380 if (addr == E8390_CMD) {
381 ret = s->cmd;
382 } else {
383 page = s->cmd >> 6;
384 offset = addr | (page << 4);
385 switch(offset) {
386 case EN0_TSR:
387 ret = s->tsr;
388 break;
389 case EN0_BOUNDARY:
390 ret = s->boundary;
391 break;
392 case EN0_ISR:
393 ret = s->isr;
394 break;
395 case EN0_RSARLO:
396 ret = s->rsar & 0x00ff;
397 break;
398 case EN0_RSARHI:
399 ret = s->rsar >> 8;
400 break;
401 case EN1_PHYS ... EN1_PHYS + 5:
402 ret = s->phys[offset - EN1_PHYS];
403 break;
404 case EN1_CURPAG:
405 ret = s->curpag;
406 break;
407 case EN1_MULT ... EN1_MULT + 7:
408 ret = s->mult[offset - EN1_MULT];
409 break;
410 case EN0_RSR:
411 ret = s->rsr;
412 break;
413 case EN2_STARTPG:
414 ret = s->start >> 8;
415 break;
416 case EN2_STOPPG:
417 ret = s->stop >> 8;
418 break;
419 case EN0_RTL8029ID0:
420 ret = 0x50;
421 break;
422 case EN0_RTL8029ID1:
423 ret = 0x43;
424 break;
425 case EN3_CONFIG0:
426 ret = 0;
427 break;
428 case EN3_CONFIG2:
429 ret = 0x40;
430 break;
431 case EN3_CONFIG3:
432 ret = 0x40;
433 break;
434 default:
435 ret = 0x00;
436 break;
437 }
438 }
439 trace_ne2000_ioport_read(addr, ret);
440 return ret;
441}
442
443static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
444 uint32_t val)
445{
446 if (addr < 32 ||
447 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
448 s->mem[addr] = val;
449 }
450}
451
452static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
453 uint32_t val)
454{
455 addr &= ~1;
456 if (addr < 32 ||
457 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
458 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
459 }
460}
461
462static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
463 uint32_t val)
464{
465 addr &= ~1;
466 if (addr < 32
467 || (addr >= NE2000_PMEM_START
468 && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
469 stl_le_p(s->mem + addr, val);
470 }
471}
472
473static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
474{
475 if (addr < 32 ||
476 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
477 return s->mem[addr];
478 } else {
479 return 0xff;
480 }
481}
482
483static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
484{
485 addr &= ~1;
486 if (addr < 32 ||
487 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
488 return le16_to_cpu(*(uint16_t *)(s->mem + addr));
489 } else {
490 return 0xffff;
491 }
492}
493
494static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
495{
496 addr &= ~1;
497 if (addr < 32
498 || (addr >= NE2000_PMEM_START
499 && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
500 return ldl_le_p(s->mem + addr);
501 } else {
502 return 0xffffffff;
503 }
504}
505
506static inline void ne2000_dma_update(NE2000State *s, int len)
507{
508 s->rsar += len;
509
510
511 if (s->rsar == s->stop)
512 s->rsar = s->start;
513
514 if (s->rcnt <= len) {
515 s->rcnt = 0;
516
517 s->isr |= ENISR_RDC;
518 ne2000_update_irq(s);
519 } else {
520 s->rcnt -= len;
521 }
522}
523
524static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
525{
526 NE2000State *s = opaque;
527
528#ifdef DEBUG_NE2000
529 printf("NE2000: asic write val=0x%04x\n", val);
530#endif
531 if (s->rcnt == 0)
532 return;
533 if (s->dcfg & 0x01) {
534
535 ne2000_mem_writew(s, s->rsar, val);
536 ne2000_dma_update(s, 2);
537 } else {
538
539 ne2000_mem_writeb(s, s->rsar, val);
540 ne2000_dma_update(s, 1);
541 }
542}
543
544static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
545{
546 NE2000State *s = opaque;
547 int ret;
548
549 if (s->dcfg & 0x01) {
550
551 ret = ne2000_mem_readw(s, s->rsar);
552 ne2000_dma_update(s, 2);
553 } else {
554
555 ret = ne2000_mem_readb(s, s->rsar);
556 ne2000_dma_update(s, 1);
557 }
558#ifdef DEBUG_NE2000
559 printf("NE2000: asic read val=0x%04x\n", ret);
560#endif
561 return ret;
562}
563
564static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
565{
566 NE2000State *s = opaque;
567
568#ifdef DEBUG_NE2000
569 printf("NE2000: asic writel val=0x%04x\n", val);
570#endif
571 if (s->rcnt == 0)
572 return;
573
574 ne2000_mem_writel(s, s->rsar, val);
575 ne2000_dma_update(s, 4);
576}
577
578static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
579{
580 NE2000State *s = opaque;
581 int ret;
582
583
584 ret = ne2000_mem_readl(s, s->rsar);
585 ne2000_dma_update(s, 4);
586#ifdef DEBUG_NE2000
587 printf("NE2000: asic readl val=0x%04x\n", ret);
588#endif
589 return ret;
590}
591
592static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
593{
594
595}
596
597static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
598{
599 NE2000State *s = opaque;
600 ne2000_reset(s);
601 return 0;
602}
603
604static int ne2000_post_load(void* opaque, int version_id)
605{
606 NE2000State* s = opaque;
607
608 if (version_id < 2) {
609 s->rxcr = 0x0c;
610 }
611 return 0;
612}
613
614const VMStateDescription vmstate_ne2000 = {
615 .name = "ne2000",
616 .version_id = 2,
617 .minimum_version_id = 0,
618 .post_load = ne2000_post_load,
619 .fields = (VMStateField[]) {
620 VMSTATE_UINT8_V(rxcr, NE2000State, 2),
621 VMSTATE_UINT8(cmd, NE2000State),
622 VMSTATE_UINT32(start, NE2000State),
623 VMSTATE_UINT32(stop, NE2000State),
624 VMSTATE_UINT8(boundary, NE2000State),
625 VMSTATE_UINT8(tsr, NE2000State),
626 VMSTATE_UINT8(tpsr, NE2000State),
627 VMSTATE_UINT16(tcnt, NE2000State),
628 VMSTATE_UINT16(rcnt, NE2000State),
629 VMSTATE_UINT32(rsar, NE2000State),
630 VMSTATE_UINT8(rsr, NE2000State),
631 VMSTATE_UINT8(isr, NE2000State),
632 VMSTATE_UINT8(dcfg, NE2000State),
633 VMSTATE_UINT8(imr, NE2000State),
634 VMSTATE_BUFFER(phys, NE2000State),
635 VMSTATE_UINT8(curpag, NE2000State),
636 VMSTATE_BUFFER(mult, NE2000State),
637 VMSTATE_UNUSED(4),
638 VMSTATE_BUFFER(mem, NE2000State),
639 VMSTATE_END_OF_LIST()
640 }
641};
642
643static uint64_t ne2000_read(void *opaque, hwaddr addr,
644 unsigned size)
645{
646 NE2000State *s = opaque;
647 uint64_t val;
648
649 if (addr < 0x10 && size == 1) {
650 val = ne2000_ioport_read(s, addr);
651 } else if (addr == 0x10) {
652 if (size <= 2) {
653 val = ne2000_asic_ioport_read(s, addr);
654 } else {
655 val = ne2000_asic_ioport_readl(s, addr);
656 }
657 } else if (addr == 0x1f && size == 1) {
658 val = ne2000_reset_ioport_read(s, addr);
659 } else {
660 val = ((uint64_t)1 << (size * 8)) - 1;
661 }
662 trace_ne2000_read(addr, val);
663
664 return val;
665}
666
667static void ne2000_write(void *opaque, hwaddr addr,
668 uint64_t data, unsigned size)
669{
670 NE2000State *s = opaque;
671
672 trace_ne2000_write(addr, data);
673 if (addr < 0x10 && size == 1) {
674 ne2000_ioport_write(s, addr, data);
675 } else if (addr == 0x10) {
676 if (size <= 2) {
677 ne2000_asic_ioport_write(s, addr, data);
678 } else {
679 ne2000_asic_ioport_writel(s, addr, data);
680 }
681 } else if (addr == 0x1f && size == 1) {
682 ne2000_reset_ioport_write(s, addr, data);
683 }
684}
685
686static const MemoryRegionOps ne2000_ops = {
687 .read = ne2000_read,
688 .write = ne2000_write,
689 .endianness = DEVICE_LITTLE_ENDIAN,
690};
691
692
693
694
695void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size)
696{
697 memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size);
698}
699